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Column-associative caches: a technique for reducing the miss rate of direct-mapped caches

Authors:

Anant Agarwal,

Stephen D. PudarAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 21, Issue 2

Pages 179 - 190

https://doi.org/10.1145/173682.165153

Published: 01 May 1993 Publication History

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Cited By

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Ho NKaufmann PPlatzner M(2020)Evolution of application-specific cache mappingsInternational Journal of Hybrid Intelligent Systems10.3233/HIS-200281(1-13)Online publication date: 3-Jul-2020
https://doi.org/10.3233/HIS-200281
Teran EChishti ZWang ZWilkerson CJiménez DKaeli DPericàs M(2018)Flexible associativity for DRAM cachesProceedings of the 15th ACM International Conference on Computing Frontiers10.1145/3203217.3203283(88-96)Online publication date: 8-May-2018
https://dl.acm.org/doi/10.1145/3203217.3203283
Young VChou CJaleel AQureshi M(2018)ACCORDProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00036(328-339)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00036
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Index Terms

Column-associative caches: a technique for reducing the miss rate of direct-mapped caches
1. General and reference
  1. Cross-computing tools and techniques
    1. Measurement
    2. Metrics
2. Hardware
  1. Hardware test
    1. Test-pattern generation and fault simulation
  2. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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PACT '01: Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques

Abstract: While set-associative caches typically incur fewer misses than direct-mapped caches, set-associative caches have slower hit times. We propose the reactive-associative cache (r-a cache), which provides flexible associativity by placing most ...
Snug set-associative caches: Reducing leakage power of instruction and data caches with no performance penalties

As transistors keep shrinking and on-chip caches keep growing, static power dissipation resulting from leakage of caches takes an increasing fraction of total power in processors. Several techniques have already been proposed to reduce leakage power by ...
LRU-based column-associative caches

The column-associative cache is a direct-mapped cache that may be accessed more than once, each time with a different hash function, to satisfy a memory request. In the column-associative cache, the possible locations that a line can reside in defines ...

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 21, Issue 2

Special Issue: Proceedings of the 20th annual international symposium on Computer architecture (ISCA '93)

May 1993

348 pages

ISSN:0163-5964

DOI:10.1145/173682

Editor:
Doug DeGroot
Texas Instruments Inc., Dallas, TX

Issue’s Table of Contents

ISCA '93: Proceedings of the 20th annual international symposium on computer architecture
June 1993
361 pages
ISBN:0818638109
DOI:10.1145/165123
Chairman:
Alan Jay Smith

Publisher

Association for Computing Machinery

New York, NY, United States

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Published: 01 May 1993

Published in SIGARCH Volume 21, Issue 2

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Cited By

View all

Ho NKaufmann PPlatzner M(2020)Evolution of application-specific cache mappingsInternational Journal of Hybrid Intelligent Systems10.3233/HIS-200281(1-13)Online publication date: 3-Jul-2020
https://doi.org/10.3233/HIS-200281
Teran EChishti ZWang ZWilkerson CJiménez DKaeli DPericàs M(2018)Flexible associativity for DRAM cachesProceedings of the 15th ACM International Conference on Computing Frontiers10.1145/3203217.3203283(88-96)Online publication date: 8-May-2018
https://dl.acm.org/doi/10.1145/3203217.3203283
Young VChou CJaleel AQureshi M(2018)ACCORDProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00036(328-339)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00036
Shatnawi AAlsaedeen M(2018)Reducing the second-level cache conflict misses using a set folding techniqueThe Journal of Supercomputing10.1007/s11227-017-2174-874:2(970-993)Online publication date: 1-Feb-2018
https://dl.acm.org/doi/10.1007/s11227-017-2174-8
Choo KTroendle DGad EJang B(2017)Contention-Aware Selective Caching to Mitigate Intra-Warp Contention on GPUs2017 16th International Symposium on Parallel and Distributed Computing (ISPDC)10.1109/ISPDC.2017.17(1-8)Online publication date: Jul-2017
https://doi.org/10.1109/ISPDC.2017.17
González AAliagas C(2014)Author retrospective for the dual data cacheACM International Conference on Supercomputing 25th Anniversary Volume10.1145/2591635.2591652(32-34)Online publication date: 10-Jun-2014
https://dl.acm.org/doi/10.1145/2591635.2591652
Bournoutian GOrailoglu A(2013)Application-aware adaptive cache architecture for power-sensitive mobile processorsACM Transactions on Embedded Computing Systems10.1145/2539036.253903713:3(1-26)Online publication date: 24-Dec-2013
https://dl.acm.org/doi/10.1145/2539036.2539037
Baer J(2012)The Cache HierarchyMicroprocessor Architecture10.1017/CBO9780511811258.007(208-259)Online publication date: 5-Jun-2012
https://doi.org/10.1017/CBO9780511811258.007
Chang FHuang H(2012)A refactoring method for cache-efficient swarm intelligence algorithmsInformation Sciences: an International Journal10.1016/j.ins.2010.02.025192(39-49)Online publication date: 1-Jun-2012
https://dl.acm.org/doi/10.1016/j.ins.2010.02.025
Ang-Chih Hsieh TingTing Hwang (2010)Run-time Reconfiguration of expandable cache for embedded systemsProceedings of 2010 International Symposium on VLSI Design, Automation and Test10.1109/VDAT.2010.5496726(207-210)Online publication date: Apr-2010
https://doi.org/10.1109/VDAT.2010.5496726
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Reactive-Associative Caches

Snug set-associative caches: Reducing leakage power of instruction and data caches with no performance penalties

LRU-based column-associative caches

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