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Serial fault emulation

Published: 01 June 1996 Publication History
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References

[1]
M. Abramovici, M. A. Breuer and A. D. Friedman "Digital Systems Testing and Testable Design", New York, W.H. Freeman and Company, 1990, p. 134
[2]
R S. Bottorff "Test Generation and Fault Simulation", VLSI Testing, North Holland Ed., 1985, pp. 29-64
[3]
R.K. Brayton, G.D. Hatchel and A.L. Sangiovanni-Vincentelli "Multilevel Logic Synthesis", Proc. of the IEEE, Vol. 78, No 2, Feb. 1990, pp. 264-300
[4]
M. Butts, J. Bacheler and J. Varghese "An Efficient Logic Emulation System", Proc. ICCD, 1992, pp. 138-141
[5]
W. T. Cheng and M.L. Yu "Differential Fault Simulation - A Fast Method Using Minimal Memory", Proc. 26th DAC, 1989, pp. 424- 428
[6]
S. Gai and E L. Montessoro "Creator : New Advanced Concepts in Concurrent Simulation", IEEE Trans. on CAD, Vol 13, No 6, June 1994, pp. 786-795
[7]
J. Gateley et al. "UltraSPARC-IEmulation", Proc. 32nd DAC, 1995, pp. 535-540
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D. Harel and B. Krishnamurthy "Is There Hope for Linear Time Fault Simulation ?", Fault Tolerant Computing Symposium, July 1987, pp.28-33
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D.D. Hill and D.R. Cassiday "Preliminary Description of Tabula Rasa, an Electrically Reconfigurable Hardware Engine", Proc. ICCD, Sept. 1990, pp. 391-395
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H-C. Hsieh et al. "A Second Generation User-Programmable Gate Array", Proc. Custom Integrated Circuit Conference, 1987, pp. 515- 521
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U. R. Khan, H.L. Owen and J. L. A. Hughes "FPGA Architectures for ASIC Hardware Emulator", Proc. 6th IEEE ASIC Conference, 1993, pp. 336-340
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H.K. Lee and D.S. Ha "HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits", Proc. 29th DAC, 1992 pp. 336-340
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H.K. Lee and D.S. Ha "New Techniques for Improving Parallel Fault Simulation in Synchronous Sequential Circuits", Proc. IC- CAD, 1993 pp. 10-17
[14]
E. W. Thomson and S. A. Szygenda "Parallel Fault Simulation", Computer, Vol. 8, No 3, March. 1975, pp. 177-188
[15]
E.G. Ulrich and T. Baker"Concurrent Simulation of nearly Identical Digital Networks", Computer, Vol. 7, April 1974, pp. 204-209
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N. Van Brunt "The Zycad Logic Evaluator and its Application to Modern System Design", Proc. ICCD, 1983, pp. 232-233
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S. Walters "Computer-aided Prototyping for ASIC-based Systems", IEEE Design and Test, June 1991, pp. 4-10

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      cover image ACM Conferences
      DAC '96: Proceedings of the 33rd annual Design Automation Conference
      June 1996
      839 pages
      ISBN:0897917790
      DOI:10.1145/240518
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 01 June 1996

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      June 3 - 7, 1996
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      DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;
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      Cited By

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      • (2020)Application Domain-Based Overview of IoT Network Traffic CharacteristicsACM Computing Surveys10.1145/339966953:4(1-33)Online publication date: 11-Jul-2020
      • (2014)Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs2014 24th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2014.6927478(1-6)Online publication date: Sep-2014
      • (2013)StML: Bridging the gap between FPGA design and HDL circuit description2013 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2013.6718366(278-285)Online publication date: Dec-2013
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      • (2011)A probabilistic analysis of coverage methodsACM Transactions on Design Automation of Electronic Systems10.1145/2003695.200369816:4(1-20)Online publication date: 27-Oct-2011
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