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Clock Tree synthesis for TSV-based 3D IC designs

Authors:

Taewhan KimAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 16, Issue 4

Article No.: 48, Pages 1 - 21

https://doi.org/10.1145/2003695.2003708

Published: 27 October 2011 Publication History

Abstract

For the cost-effective implementation of clock trees in through-silicon via (TSV)-based 3D IC designs, we propose core algorithms for 3D clock tree synthesis. For a given abstract tree topology, we propose DLE-3D (deferred layer embedding for 3D ICs), which optimally finds the embedding layers of tree nodes, so that the TSV cost required for a tree topology is minimized, and DME-3D (deferred merge embedding for 3D ICs), which is an extended algorithm of the 2D merging segment, to minimize the total wirelength in 3D design space, with the consideration of the TSV effect on delay. In addition, when an abstract tree topology is not given, we propose NN-3D (nearest neighbor selection for 3D ICs), which constructs a (TSV and wirelength) cost-effective abstract tree topology for 3D ICs. Through experimentation, we have confirmed that the clock tree synthesis flow using the proposed algorithms is very effective, outperforming the existing 3D clock tree synthesis in terms of the number of TSVs, total wirelength, and clock power consumption.

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Cited By

Yang XChen HZhang YHou TRen PWang RJi ZHuang R(2024)Physics-Informed Learning Based Multiphysics Simulation for Fast Transient TSV Electromigration AnalysisACM Transactions on Design Automation of Electronic Systems10.1145/370610630:2(1-22)Online publication date: 29-Nov-2024
https://dl.acm.org/doi/10.1145/3706106
Pavlidis CSketopoulos NSotiriou CPavlidis V(2024)Ternary Clock Tree Synthesis for 3D ICs2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)10.1109/SMACD61181.2024.10745448(1-4)Online publication date: 2-Jul-2024
https://doi.org/10.1109/SMACD61181.2024.10745448
Lee JLee J(2022)Specializing CGRAs for Light-Weight Convolutional Neural NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312317841:10(3387-3399)Online publication date: 1-Oct-2022
https://dl.acm.org/doi/10.1109/TCAD.2021.3123178
Show More Cited By

Index Terms

Clock Tree synthesis for TSV-based 3D IC designs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 16, Issue 4

October 2011

326 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2003695

Issue’s Table of Contents

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 27 October 2011

Accepted: 01 April 2011

Revised: 01 January 2011

Received: 01 October 2010

Published in TODAES Volume 16, Issue 4

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Cited By

Yang XChen HZhang YHou TRen PWang RJi ZHuang R(2024)Physics-Informed Learning Based Multiphysics Simulation for Fast Transient TSV Electromigration AnalysisACM Transactions on Design Automation of Electronic Systems10.1145/370610630:2(1-22)Online publication date: 29-Nov-2024
https://dl.acm.org/doi/10.1145/3706106
Pavlidis CSketopoulos NSotiriou CPavlidis V(2024)Ternary Clock Tree Synthesis for 3D ICs2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)10.1109/SMACD61181.2024.10745448(1-4)Online publication date: 2-Jul-2024
https://doi.org/10.1109/SMACD61181.2024.10745448
Lee JLee J(2022)Specializing CGRAs for Light-Weight Convolutional Neural NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312317841:10(3387-3399)Online publication date: 1-Oct-2022
https://dl.acm.org/doi/10.1109/TCAD.2021.3123178
Paulino NFerreira JCardoso J(2020)Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A SurveyACM Computing Surveys10.1145/336976453:1(1-36)Online publication date: 6-Feb-2020
https://dl.acm.org/doi/10.1145/3369764
Oh DChoi MKim J(2019)Thermal-aware 3D Symmetrical Buffered Clock Tree SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/331379824:3(1-22)Online publication date: 5-Apr-2019
https://dl.acm.org/doi/10.1145/3313798
Oh DChoi MKim J(2018)Thermal-Aware 3D Symmetrical Buffered Clock Tree Synthesis2018 IEEE 36th International Conference on Computer Design (ICCD)10.1109/ICCD.2018.00013(9-16)Online publication date: Oct-2018
https://doi.org/10.1109/ICCD.2018.00013
Lu TSrivastava A(2017)Low-Power Clock Tree Synthesis for 3D-ICsACM Transactions on Design Automation of Electronic Systems10.1145/301961022:3(1-24)Online publication date: 5-Apr-2017
https://dl.acm.org/doi/10.1145/3019610
Lu TSerafy CYang ZSamal SLim SSrivastava A(2017)TSV-Based 3-D ICs: Design Methods and ToolsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.266660436:10(1593-1619)Online publication date: 1-Oct-2017
https://dl.acm.org/doi/10.1109/TCAD.2017.2666604
Daulagala ISavidis I(2017)Clock tree synthesis for heterogeneous 3-D integrated circuits2017 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)10.1109/SLIP.2017.7974911(1-6)Online publication date: 27-Jun-2017
https://doi.org/10.1109/SLIP.2017.7974911
Joo DKim T(2017)Clock buffer polarity assignment under useful skew constraintsIntegration, the VLSI Journal10.1016/j.vlsi.2016.11.00757:C(52-61)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.11.007
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