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On-chip memory architecture exploration framework for DSP processor-based embedded system on chip

Authors:

T.S. Rajesh Kumar,

R. Govindarajan,

C.P. RavikumarAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 11, Issue 1

Article No.: 5, Pages 1 - 25

https://doi.org/10.1145/2146417.2146422

Published: 05 April 2012 Publication History

Abstract

Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The memory architecture of embedded SoCs strongly influences the power and performance of the entire system. Further, the memory subsystem constitutes a major part (typically up to 70%) of the silicon area for the current day SoC. In this article, we address the on-chip memory architecture exploration for DSP processors which are organized as multiple memory banks, where banks can be single/dual ported with non-uniform bank sizes. In this paper we propose two different methods for physical memory architecture exploration and identify the strengths and applicability of these methods in a systematic way. Both methods address the memory architecture exploration for a given target application by considering the application's data access characteristics and generates a set of Pareto-optimal design points that are interesting from a power, performance and VLSI area perspective. To the best of our knowledge, this is the first comprehensive work on memory space exploration at physical memory level that integrates data layout and memory exploration to address the system objectives from both hardware design and application software development perspective. Further we propose an automatic framework that explores the design space identifying 100's of Pareto-optimal design points within a few hours of running on a standard desktop configuration.

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Cited By

Wang BVandierendonck HKarakonstantis GNikolopoulos D(2018)Userspace Hypervisor Data Characterization in Virtualized Environment2018 IEEE 24th International Conference on Parallel and Distributed Systems (ICPADS)10.1109/PADSW.2018.8644612(638-645)Online publication date: Dec-2018
https://doi.org/10.1109/PADSW.2018.8644612
Eusse JFernandez FLeupers RAscheid G(2016)Concurrent memory subsystem and application optimization for ASIP design2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)10.1109/SAMOS.2016.7818325(1-10)Online publication date: Jul-2016
https://doi.org/10.1109/SAMOS.2016.7818325
Pilato CMantovani PDi Guglielmo GCarloni LMarculescu RNicolescu G(2014)System-level memory optimization for high-level synthesis of component-based SoCsProceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis10.1145/2656075.2656098(1-10)Online publication date: 12-Oct-2014
https://dl.acm.org/doi/10.1145/2656075.2656098
Show More Cited By

Index Terms

On-chip memory architecture exploration framework for DSP processor-based embedded system on chip
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems

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Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 11, Issue 1

March 2012

248 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/2146417

Issue’s Table of Contents

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 05 April 2012

Accepted: 01 June 2010

Received: 01 November 2008

Published in TECS Volume 11, Issue 1

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Cited By

Wang BVandierendonck HKarakonstantis GNikolopoulos D(2018)Userspace Hypervisor Data Characterization in Virtualized Environment2018 IEEE 24th International Conference on Parallel and Distributed Systems (ICPADS)10.1109/PADSW.2018.8644612(638-645)Online publication date: Dec-2018
https://doi.org/10.1109/PADSW.2018.8644612
Eusse JFernandez FLeupers RAscheid G(2016)Concurrent memory subsystem and application optimization for ASIP design2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)10.1109/SAMOS.2016.7818325(1-10)Online publication date: Jul-2016
https://doi.org/10.1109/SAMOS.2016.7818325
Pilato CMantovani PDi Guglielmo GCarloni LMarculescu RNicolescu G(2014)System-level memory optimization for high-level synthesis of component-based SoCsProceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis10.1145/2656075.2656098(1-10)Online publication date: 12-Oct-2014
https://dl.acm.org/doi/10.1145/2656075.2656098
Pilato CMantovani PDi Guglielmo GCarloni LMarculescu RNicolescu G(2014)System-level memory optimization for high-level synthesis of component-based SoCsProceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis10.1145/2565075.2656098(1-10)Online publication date: 12-Oct-2014
https://dl.acm.org/doi/10.1145/2565075.2656098
Li YJu LJia ZWang YShao Z(2013)Thermal-Aware On-Chip Memory Architecture ExplorationProceedings of the 2013 12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications10.1109/TrustCom.2013.167(1386-1393)Online publication date: 16-Jul-2013
https://dl.acm.org/doi/10.1109/TrustCom.2013.167
Huang MLai C(2013)Accelerating Applications Using GPUs on Embedded Systems and Mobile Devices2013 IEEE 10th International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing10.1109/HPCC.and.EUC.2013.146(1031-1038)Online publication date: Nov-2013
https://doi.org/10.1109/HPCC.and.EUC.2013.146

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