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Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency

Authors:

Junhee Yoo,

Sungjoo Yoo,

Kiyoung ChoiAuthors Info & Claims

DAC '09: Proceedings of the 46th Annual Design Automation Conference

Pages 806 - 811

https://doi.org/10.1145/1629911.1630118

Published: 26 July 2009 Publication History

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Abstract

Memory access latency and memory-related operations are often the performance bottleneck in parallel applications. In this paper, we present a concept of active memory operations which is an on-chip network transaction that operates based on the microcode provided by the software designer. Utilizing the active memory operation, we can replace multiple transactions of memory accesses over the on-chip network and related local processing element computation with a smaller number of high-level transactions and near-memory computation. We implemented a processor called active memory processor which is located near the memory and executes the active memory operations. In our case studies, we applied the concept to three real-world applications (parallelized JPEG, FFT, and text indexing for data mining) running on a 36-tile architecture with 32 cores and 4 memories and found that the programmable transaction approach can improve performance by 34.3% to 618% at the cost of additional design effort.

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Cited By

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Wang YZhang ZHuang LJi W(2015)Memory-Aware NoC Application Mapping Based on Adaptive Genetic AlgorithmAlgorithms and Architectures for Parallel Processing10.1007/978-3-319-27119-4_7(91-102)Online publication date: 16-Dec-2015
https://doi.org/10.1007/978-3-319-27119-4_7
Lee JChung MCho YRyu SAhn JChoi K(2013)Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory ConstraintIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.226640532:11(1748-1761)Online publication date: 1-Nov-2013
https://dl.acm.org/doi/10.1109/TCAD.2013.2266405
Seiculescu CBenini LDe Micheli GJerraya ACarloni LChang NFummi F(2012)A distributed interleaving scheme for efficient access to WideIO DRAM memoryProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2380445.2380467(103-112)Online publication date: 7-Oct-2012
https://dl.acm.org/doi/10.1145/2380445.2380467
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Index Terms

Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency
1. Computer systems organization
  1. Architectures
    1. Distributed architectures

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DAC '09: Proceedings of the 46th Annual Design Automation Conference

July 2009

994 pages

ISBN:9781605584973

DOI:10.1145/1629911

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 26 July 2009

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DAC '09: The 46th Annual Design Automation Conference 2009

July 26 - 31, 2009

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Wang YZhang ZHuang LJi W(2015)Memory-Aware NoC Application Mapping Based on Adaptive Genetic AlgorithmAlgorithms and Architectures for Parallel Processing10.1007/978-3-319-27119-4_7(91-102)Online publication date: 16-Dec-2015
https://doi.org/10.1007/978-3-319-27119-4_7
Lee JChung MCho YRyu SAhn JChoi K(2013)Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory ConstraintIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.226640532:11(1748-1761)Online publication date: 1-Nov-2013
https://dl.acm.org/doi/10.1109/TCAD.2013.2266405
Seiculescu CBenini LDe Micheli GJerraya ACarloni LChang NFummi F(2012)A distributed interleaving scheme for efficient access to WideIO DRAM memoryProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2380445.2380467(103-112)Online publication date: 7-Oct-2012
https://dl.acm.org/doi/10.1145/2380445.2380467
Yoo JYoo SChoi K(2012)Active Memory Processor for Network-on-Chip-Based ArchitectureIEEE Transactions on Computers10.1109/TC.2011.6661:5(622-635)Online publication date: 1-May-2012
https://dl.acm.org/doi/10.1109/TC.2011.66
Jinho Lee Choi K(2012)Memory-aware mapping and scheduling of tasks and communications on many-core SoC17th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2012.6164985(419-424)Online publication date: Jan-2012
https://doi.org/10.1109/ASPDAC.2012.6164985

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Phase-change memory: An architectural perspective

Active Memory Processor for Network-on-Chip-Based Architecture

Enabling Hybrid PCM Memory System with Inherent Memory Management

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