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EDA ecosystem's fantastic supports and innovations have helped achieve better logic, memory, wafer-level packaging, and AI chips and systems [1] [2] and [3], for decades. We look forward to the continuous win-win collaborations among university ...

Internet-of-Things (IoT) edge devices have limited resources in terms of area and power. Machine Learning based intelligent filtering can be effective in reducing the data footprint. In this work, we report a feasibility study of using decision trees (...

Machine learning methods have exploded in the past half-dozen years. Machine learning is being applied to a huge range of problems across the spectrum of applications. Initial results relied on server-oriented computations. But many applications will ...

The design of microelectronic systems requires integration and cooperation across multiple disciplines, but most curriculum is taught in unconnected pieces. This makes the creation of manageable projects that reflect the design experience very difficult. ...

Deep neural network (DNN) has become a pivotal machine learning and object recognition technology in the big data era. The softmax layer is one of the key component layers for completing multi-classification tasks. However, the softmax layer contains ...

FPGAs provide a promising implementation option for many machine learning applications. Although simulations or software models can be used to explore the design space of these applications, often the final behaviour can not be evaluated until the ...

The paper presents "MC3A"- Markov Chain Monte Carlo Many Core Accelerator, a high-throughput, domain-specific, programmable manycore accelerator, which effectively generates samples from a provided target distribution. MCMC samplers are used in machine ...

The progressive miniaturization of technology and the unequal scalability of the BEOL and FEOL layers aggravate the routing congestion problem and have a negative impact on manufacturability. Standard cells are designed in a way that they can be treated ...

In the past two decades, there has been tremendous progress in video compression technologies. Meanwhile, the use of these technologies, along with the ever-increasing demand for emerging ultra-high-definition applications greatly challenges the design ...

Design rule check (DRC) violations after detailed routing prevent a design from being taped out. To solve this problem, state-of-the-art commercial EDA tools global-route the design to produce a global-route congestion map; this map is used by the ...

Polar codes, as the new generation of channel codes, have potential applications in communication and storage systems. Successive-cancellation list (SCL) algorithm is the main decoding approach for improving the error-correcting performance of polar ...

Fast digital timing simulations based on continuous-time, digital-value circuit models are an attractive and heavily used alternative to analog simulations. Models based on analytic delay formulas are particularly interesting here, as they also ...

Performance of single walled carbon nanotube (SWCNT) bundle- based VLSI interconnects has been studied under the strong influence of scatterings induced by self-heating. Landauer Büttiker formalism along with Fourier heat transfer equation have been ...

This paper presents a new approach for hardware-based QR-decomposition using an efficient computation scheme of the Givens-Rotation. In detail, the angle of rotation and its application to the Givens-Matrix are processed in a direct, straightforward ...

Bounded Model Checking (BMC), as a formal method of verifying VLSI circuits, shows violation of a given circuit property by finding a counter-example to the property along bounded state paths of the circuit. In this paper, we present an emulation ...

This paper introduces a novel multi-voltage domain clock mesh design methodology that is effective under multiple process corners. In multi-voltage designs, a single clock mesh that spans multiple voltage domains is infeasible due to the incompatibility ...

This paper introduces a methodology that optimizes the performance of a low swing clock tree under a skew bound. Low-swing clock trees are preferred for a reduction in the clock switching power, with an expected trade-off in clock slew and skew. In this ...

The latest design specs have arrived and it is now clear that timing runs will not fit in our machines. What to do! Is hierarchical STA the perfect solution? Will it work exactly like flat? How will it interact with the hierarchical design ...