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Analog placement is a crucial phase in analog integrated circuit synthesis, impacting the quality and performance of the final circuits. This process involves determining the physical positions of analog building blocks while minimizing chip area and ...

Analog IC designers and design houses have been accumulating their own design knowledge and constructing their own analog design repositories, including various design specifications, applications, and process technologies. As most of the analog layouts ...

At the Institute for Electronic Design Automation of Technische Universität München (TUM), founded in 1975 by Prof. Kurt Antreich as Germany's first university institute dedicated to EDA, a broad range of research has been performed in the past 40 ...

The FinFET technology has been regarded as a better alternative among different device technologies at 22nm node and beyond due to more effective channel control and lower power consumption. However, the gate misalignment problem resulting from process ...

Switched capacitors are commonly used in analog design. The circuit performance based on this technique relies on the accuracy of capacitance ratios, which are affected by random and systematic mismatches. To meet the accuracy requirement, designers can ...

To obtain good layout quality and reliability, placement is a very important stage during the physical design of analog circuits. Many works have been proposed to consider topological constraints for analog placement, and they devote to generate compact ...

One of the most important issues during the analog layout phase is to achieve accurate capacitance ratios. However, systematic and random mismatches will affect the accuracy of the capacitance ratios. A common-centroid placement is helpful to reduce the ...

To reduce parasitic mismatches in analog design, we usually care about the property of symmetric placement for symmetry groups, which would form several symmetry islands in a chip. However, routing is greatly affected by placement results. If modules ...

With the thermal effect, improper analog placements may degrade circuit performance because the thermal impact from power devices can affect electrical characteristics of the thermally-sensitive devices. There is not much previous work that considers ...

In analog layout design, it is very important to reduce the parasitic coupling effects and improve the circuit performance. Consequently, the most important device-level placement constraints are matching, symmetry, and proximity. However, many previous ...

In this paper, we present the first amortized linear-time packing algorithm for the placement with symmetry constraints. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected ...

This paper advances a new methodology based on signal-path information to resolve the problem of device-level placement for analog layout. This methodology is mainly based on three observations: thinking of hierarchical design for analog, structural ...