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Optimization of NULL convention self-timed circuits

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Integration, the VLSI Journal, Volume 37, Issue 3

Pages 135 - 165

https://doi.org/10.1016/j.vlsi.2003.12.004

Published: 01 August 2004 Publication History

Abstract

Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within the NULL Convention Logic (NCL) paradigm. NCL logic functions are realized using 27 distinct transistor networks implementing the set of all functions of four or fewer variables, thus facilitating a variety of gate-level optimizations. TCR optimizations are formalized for NCL and then assessed by comparing levels of gate delays, gate counts, transistor counts, and power utilization of the resulting designs. The methods are illustrated to produce (1) fundamental logic functions that are 2.2-2.3 times faster and require 40-45% fewer transistors than conventional canonical designs, (2) a Full Adder with reduced critical path delay and transistor count over various alternative gate-level synthesis approaches, resulting in a circuit with at least 48% fewer transistors, half as many gate delays to generate the carry output, and the same number of gate delays to generate the sum output, as its nearest competitors, and (3) time, space, and power optimized increment circuits for a 4-bit up-counter, resulting in a throughput-optimized design that is 14% and 82% faster than area- and power-optimized designs, respectively, an area-optimized design that requires 22% and 42% fewer transistors than the speed- and power-optimized designs, respectively, and a power-optimized design that dissipates 63% and 42% less power than the speed- and area-optimized designs, respectively. Results demonstrate support for a variety of optimizations utilizing conventional Boolean minimization followed by table-driven gate substitutions, providing for an NCL design method that is readily automatable.

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Cited By

Yang WMa YYan JChen YXiao SYu Z(2022)A dual-rail/single-rail hybrid system using null convention logic circuitsMicroelectronics Journal10.1016/j.mejo.2022.105446125:COnline publication date: 1-Jul-2022
https://dl.acm.org/doi/10.1016/j.mejo.2022.105446
Bai YHu BKuang WLin MCoskun AMargala MBehjat LHan J(2016)Ultra-Robust Null Convention Logic Circuit with Emerging Domain Wall DevicesProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2903019(251-256)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2903019
Balasubramanian P(2016)Comments on "Dual-rail asynchronous logic multi-level implementation"Integration, the VLSI Journal10.1016/j.vlsi.2015.08.00152:C(34-40)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1016/j.vlsi.2015.08.001
Show More Cited By

Index Terms

Optimization of NULL convention self-timed circuits
1. Hardware

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Published In

cover image Integration, the VLSI Journal

Integration, the VLSI Journal Volume 37, Issue 3

August 2004

54 pages

ISSN:0167-9260

Issue’s Table of Contents

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Elsevier Science Publishers B. V.

Netherlands

Publication History

Published: 01 August 2004

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Cited By

Yang WMa YYan JChen YXiao SYu Z(2022)A dual-rail/single-rail hybrid system using null convention logic circuitsMicroelectronics Journal10.1016/j.mejo.2022.105446125:COnline publication date: 1-Jul-2022
https://dl.acm.org/doi/10.1016/j.mejo.2022.105446
Bai YHu BKuang WLin MCoskun AMargala MBehjat LHan J(2016)Ultra-Robust Null Convention Logic Circuit with Emerging Domain Wall DevicesProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2903019(251-256)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2903019
Balasubramanian P(2016)Comments on "Dual-rail asynchronous logic multi-level implementation"Integration, the VLSI Journal10.1016/j.vlsi.2015.08.00152:C(34-40)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1016/j.vlsi.2015.08.001
Nakahodo MYamada CNagata Y(2007)Threshold gate with hysteresis using neuron MOSProceedings of the 7th Conference on 7th WSEAS International Conference on Systems Theory and Scientific Computation - Volume 710.5555/1347895.1347922(157-162)Online publication date: 24-Aug-2007
https://dl.acm.org/doi/10.5555/1347895.1347922
Smith SDeHon AHutton M(2007)Design of a logic element for implementing an asynchronous FPGAProceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays10.1145/1216919.1216922(13-22)Online publication date: 18-Feb-2007
https://dl.acm.org/doi/10.1145/1216919.1216922
Satagopan VBhaskaran BAl-Assadi WSmith SKakarla S(2007)DFT techniques and automation for asynchronous NULL conventional logic circuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.90394515:10(1155-1159)Online publication date: 1-Oct-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.903945
Smith S(2007)Design of an FPGA logic element for implementing asynchronous NULL convention logic circuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89872615:6(672-683)Online publication date: 1-Jun-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.898726
Zhou YSokolov DYakovlev AHassoun S(2006)Cost-aware synthesis of asynchronous circuits based on partial acknowledgementProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233533(158-163)Online publication date: 5-Nov-2006
https://dl.acm.org/doi/10.1145/1233501.1233533
Smith S(2006)Speedup of NULL convention digital circuits using NULL cycle reductionJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2005.12.00252:7(411-422)Online publication date: 1-Jul-2006
https://dl.acm.org/doi/10.1016/j.sysarc.2005.12.002

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