Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers
Pages 56 - 61
Abstract
Asynchronous controllers are very efficient to operate as high performance interfaces in heterogeneous synchronous/ asynchronous systems. Asynchronous controllers may be designed to operate either in the generalized fundamental mode (GFM) or in the input-output (I/O) mode. The latter are more robust to temperature variation and technology migration and may operate in faster environments. However, none of the existing synthesis tools, targeting circuits that operate in the I/O mode accept non-monotonic level sensitive signals (usually adopted to describe conditions in heterogeneous systems). Another limitation of these synthesis tools concerns the number of signals that may be present in the initial specification. This limitation comes from the input description that must be either a signal transition graph (STG) or a state graph (SG). In this article we present Miriã-SI, an extension of the Miriã-GFM synthesis tool that can synthesize such circuits. It starts from a state transition description known as multi-burst graph that is able to accept up to 200 signals. Non-monotonic signals are nicely handled. The resulting controllers, implemented in the feedback set-dominant latch architecture are guaranteed to be hazard free.
References
[1]
S. Hauck, Asynchronous Design Methodologies: An Overview, Proc. of the IEEE, January 1995, Vol. 83:1 pp.69--93.
[2]
S. H. Unger, Asynchronous Sequential Switching Circuits, John Wiley & Sons Inc, 1969.
[3]
D. E. Muller and W. S. Bartky, A Theory of Asynchronous Circuits, Proc. Int. Symp. Theory of Switching, pp.204-243, 1959.
[4]
D. L. Dill, Trace Theory of Automatic Hierarchical Verification of Speed-Independent, ACM Distinguished Dissertations, 1989.
[5]
S. M. Nowick, Automatic Synthesis of Burst-Mode Asynchronous Controllers, Ph.D. thesis, Stanford University, 1993.
[6]
K. Y. Yun, Synthesis of Asynchronous Controllers for Heterogeneous Systems, Ph.D. thesis, Stanford University, 1994.
[7]
K. Y. Yun and D. L. Dill, A High-Performance Asynchronous SCSI Controller, Proc. Int. Conf. Computer Design (ICCD), pp.44--49, 1995.
[8]
K. Y. Yun and D. L. Dill, Automatic Synthesis of Extended Burst-Mode Circuits: Part I (Specification and Hazard-.Free Implementation), IEEE Trans. on CAD of Integrated Circuit and Systems, Vol. 18:2, February 1999, pp. 101--117.
[9]
K. Y. Yun and D. L. Dill, Automatic Synthesis of Extended Burst-Mode Circuits: Part II (Automatic Synthesis), IEEE Trans. on CAD of Integrated Circuit and Systems, Vol. 18:2, February 1999, pp. 118--132.
[10]
Tam-Anh Chu, Synthesis of Self-Timed VLSI Circuits from Graph-Theory Specifications, Ph.D. thesis, June, 1987, Dept. of EECS, MIT.
[11]
L. Lavagno, Synthesis and Testing of Bounded wire delay asynchronous circuits from signal transition graphs, Ph.D. dissertation, University California, Berkeley, 1992.
[12]
A. Semenov, et al. Synthesis of Speed-Independent Circuits from STG-Unfolding Segment, Proc. ACM/IEEE DAC, pp.16--21, 1997
[13]
A. Kondratyev et. al. Logic Decomposition of Speed-Independent Circuits, Proc. of the IEEE, vol. 87, NO. 2, February 1999.
[14]
J. Cortadella, et al. Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers, IEICE Trans. on Information and Systems, E80-D(3), pp.315--325.
[15]
P. A. Beerel, C. J. Myers and T. H. Meng, Covering Conditions and Algorithms for the Synthesis of Speed-Independent Circuits, IEEE Trans on CAD of Int. Circuits and Systems, vol.17, no.3, March, 1998.
[16]
C. Ykman-Couvreur, C.; B. Lin, Efficient state assignment framework for asynchronous state graphs, Proc. of the Int. Conf. Computer Design, pp. 692--697, 1995b.
[17]
H. M. Jacobson and C. J. Myer, Efficient algorithms for exact two-level hazard-free logic minimization, IEEE on Trans. CAD of integrated Circuits and Systems, vol.21, no.11, pp 1269--1283, November, 2002.
[18]
D. L. Oliveira, M. Strum, W. J. Chau and W. C. Cunha, Miriã: a CAD toll synthesize multi-burst controllers for heterogeneous systems, Microelectronics Reliability, 43 (2003) 209--213.
[19]
D. L. Oliveira, Two-Level Hazard-free Logic Minimization of Speed-independent Extended Burst-Mode Controllers, Technical Report, Number. 3/2004-Instituto Tecnológico de Aeronautica - Brazil.
[20]
E. Pastor, J. Cortadella, A. Kondratyev and O. Roig, Structural methods for the synthesis of speed-independent circuits, IEEE Trans. CAD, vol 17, pp. 1108--1129, November,1998.
Index Terms
- Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers
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Published In
September 2005
271 pages
ISBN:1595931740
DOI:10.1145/1081081
- General Chair:
- Carlos Galup-Montoro,
- Program Chairs:
- Sergio Bampi,
- Alex Orailoglu
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Published: 04 September 2005
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SBCCI05: 18th Symposium on Integrated Circuits and System Design
September 4 - 7, 2005
Florianolpolis, Brazil
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