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Jonathan E. Proesel
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- affiliation: IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
- affiliation: Nubis Communications, New Providence, NJ, USA
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2020 – today
- 2024
- [c28]Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, John F. Bulzacchelli, Marcel A. Kossel, Pier Andrea Francese, Thomas Morf, Jonathan E. Proesel, Herschel A. Ainspan, Matthias Brändli, Mounir Meghelli:
Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration. CICC 2024: 1-8 - [c27]Zeynep Toprak Deniz, Timothy O. Dickson, Martin Cochet, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Matthias Brändli, Thomas Morf, Michael P. Beakes, Mounir Meghelli:
A 0.88pJ/bit 112Gb/s PAM4 Transmitter with $1\mathrm{V}_{\text{ppd}}$ Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j9]Timothy O. Dickson
, Zeynep Toprak Deniz
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. IEEE J. Solid State Circuits 58(4): 1074-1086 (2023) - 2022
- [c26]Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. VLSI Technology and Circuits 2022: 28-29 - [c25]Serdar S. Yonar, Pier Andrea Francese
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. VLSI Technology and Circuits 2022: 168-169 - 2020
- [j8]Zeynep Toprak Deniz
A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS. IEEE J. Solid State Circuits 55(1): 19-26 (2020) - [j7]Zeynep Toprak Deniz
Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS". IEEE J. Solid State Circuits 55(4): 1124 (2020) - [c24]Nicolas Dupuis, Jonathan E. Proesel, Nicolas Boyer, Herschel A. Ainspan, Christian W. Baks, Fuad E. Doany, Elaine Cyr, Benjamin G. Lee:
An 8×8 Silicon Photonic Switch Module with Nanosecond-Scale Reconfigurability. OFC 2020: 1-3 - [c23]Jonathan E. Proesel, Nicolas Dupuis, Herschel A. Ainspan, Christian W. Baks, Fuad E. Doany, Nicolas Boyer, Elaine Cyr, Benjamin G. Lee:
A Monolithically Integrated Silicon Photonics 8×8 Switch in 90nm SOI CMOS. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c22]Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli:
A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS. ISSCC 2019: 122-124 - [c21]Daniel M. Kuchta, Jonathan E. Proesel, Fuad E. Doany, Wooram Lee, Timothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli, Petar K. Pepeljugoski, Xiaoxiong Gu, Michael P. Beakes, Mark Schultz, Marc Taubenblatt, Paul Fortier, Catherine Dufort, Éric Turcotte, Marc-Olivier Pion, Charles Bureau, Frank Flens, Greta Light, Blake Trekell, Kevin Koski:
Multi-Wavelength Optical Transceivers Integrated on Node (MOTION). OFC 2019: 1-3 - [c20]Benjamin G. Lee, Nicolas Dupuis, Fuad E. Doany, Laurent Schares, Nicolas Boyer, Nathalie Normand, Herschel A. Ainspan, Christian W. Baks, Jonathan E. Proesel, Isabel De Sousa, Mounir Meghelli, Marc A. Taubenblatt:
Toward Optical Networks using Rapid Amplified Multi-Wavelength Photonic Switches. OFC 2019: 1-3 - 2018
- [j6]Jonathan E. Proesel
A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS. IEEE J. Solid State Circuits 53(4): 1214-1226 (2018) - [j5]Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese
A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 53(4): 1227-1237 (2018) - [c19]Benjamin G. Lee, Nicolas Dupuis, Jason Orcutt, Javier Ayala, Karen Nummy, Herschel A. Ainspan, Jonathan E. Proesel, Christian W. Baks, Douglas M. Gill, Mounir Meghelli, William M. J. Green:
FEC-Free 60-Gb/s Silicon Photonic Link Using SiGe-Driver ICs Hybrid-Integrated with Photonics-Enabled CMOS. OFC 2018: 1-3 - 2017
- [j4]Ilter Özkaya
A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 52(12): 3458-3473 (2017) - [c18]Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese
29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET. ISSCC 2017: 482-483 - 2016
- [c17]Jason S. Orcutt, Douglas M. Gill, Jonathan E. Proesel, John J. Ellis-Monaghan, Folkert Horst, Tymon Barwicz, Chi Xiong, Frederick G. Anderson, Ankur Agrawal, Yves Martin, Christian W. Baks, Marwan Khater, Jessie C. Rosenberg, W. D. Sacher, Jens Hofrichter, Edward Kiewra, Andreas D. Stricker, Frank Libsch, Bert Jan Offrein, Mounir Meghelli, Natalie B. Feilchenfeld, Wilfried Haensch, William M. J. Green:
Monolithic silicon photonics at 25 Gb/s. OFC 2016: 1-3 - 2015
- [j3]Alexander V. Rylyakov, Jonathan E. Proesel, Sergey V. Rylov
A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks. IEEE J. Solid State Circuits 50(12): 3120-3132 (2015) - [c16]Alexander V. Rylyakov, Jonathan E. Proesel, Sergey V. Rylov, Benjamin G. Lee, John F. Bulzacchelli, Abhijeet Ardey, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Clint Schow, Mounir Meghelli:
22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks. ISSCC 2015: 1-3 - [c15]Benjamin G. Lee, Renato Rimolo-Donadio, Alexander V. Rylyakov, Jonathan E. Proesel, John F. Bulzacchelli, Christian W. Baks, Mounir Meghelli, Clint L. Schow, Anand Ramaswamy, Jonathan E. Roth, Jae-Hyuk Shin, Brian R. Koch, Daniel K. Sparacin, Gregory A. Fish:
A WDM-Compatible 4 × 32-Gb/s CMOS-driven electro-absorption modulator array. OFC 2015: 1-3 - [c14]Anand Ramaswamy, Jonathan E. Roth, Erik J. Norberg, Robert S. Guzzon, Jae-Hyuk Shin, J. T. Imamura, Brian R. Koch, Daniel K. Sparacin, Gregory A. Fish, Benjamin G. Lee, Renato Rimolo-Donadio, Christian W. Baks, Alexander V. Rylyakov, Jonathan E. Proesel, Mounir Meghelli, Clint L. Schow:
A WDM 4×28Gbps integrated silicon photonic transmitter driven by 32nm CMOS driver ICs. OFC 2015: 1-3 - [c13]Alexander V. Rylyakov, Jonathan E. Proesel, Sergey V. Rylov, Benjamin G. Lee, John F. Bulzacchelli, Abhijeet Ardey, Clint Schow, Mounir Meghelli:
A 25 Gb/s burst-mode receiver for low latency photonic switch networks. OFC 2015: 1-3 - 2014
- [c12]Nicolas Dupuis, Daniel M. Kuchta, Fuad E. Doany, Alexander V. Rylyakov, Jonathan E. Proesel, Christian W. Baks, Clint L. Schow, S. Luong, C. Xie, L. Wang, S. Huang, K. Jackson, N. Y. Li:
Exploring the limits of high-speed receivers for multimode VCSEL-based optical links. OFC 2014: 1-3 - [c11]Nicolas Dupuis, Benjamin G. Lee, Jonathan E. Proesel, Alexander V. Rylyakov, Renato Rimolo-Donadio
30Gbps optical link utilizing heterogeneously integrated III-V/Si photonics and CMOS circuits. OFC 2014: 1-3 - [c10]Daniel M. Kuchta, Alexander V. Rylyakov, Clint L. Schow, Jonathan E. Proesel, Christian W. Baks, Petter Westbergh, Johan S. Gustavsson, Anders Larsson:
64Gb/s transmission over 57m MMF using an NRZ modulated 850nm VCSEL. OFC 2014: 1-3 - 2013
- [c9]Jonathan E. Proesel, Alexander V. Rylyakov, Clint Schow:
Optical receivers using DFE-IIR equalization. ISSCC 2013: 130-131 - [c8]Daniel M. Kuchta, Clint L. Schow, Alexander V. Rylyakov, Jonathan E. Proesel, Fuad E. Doany, Christian W. Baks, B. H. Hamel-Bissell, Chris Kocot, L. Graham, R. Johnson, Gary Landry, E. Shaw, A. MacInnes, Jim Tatum:
A 56.1Gb/s NRZ modulated 850nm VCSEL-based optical link. OFC/NFOEC 2013: 1-3 - [c7]Jonathan E. Proesel, Benjamin G. Lee, Christian W. Baks, Clint L. Schow:
35-Gb/s VCSEL-Based optical link using 32-nm SOI CMOS circuits. OFC/NFOEC 2013: 1-3 - 2012
- [j2]Jonathan E. Proesel, Benjamin G. Lee, Alexander V. Rylyakov, Christian W. Baks, Clint L. Schow:
Ultra-Low-Power 10 to 285 Gb/s CMOS-Driven VCSEL-Based Optical Links [Invited]. JOCN 4(11): B114-B123 (2012) - [c6]Jonathan E. Proesel, Clint Schow, Alexander V. Rylyakov:
25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-based optical links in 90nm CMOS. ISSCC 2012: 418-420 - 2011
- [j1]Gokce Keskin, Jonathan E. Proesel, Jean-Olivier Plouchart, Lawrence T. Pileggi:
Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs. IEEE J. Solid State Circuits 46(8): 1904-1918 (2011) - [c5]Cheng-Yuan Wen, Jeyanandh Paramesh, Larry T. Pileggi, Jing Li
Post-silicon calibration of analog CMOS using phase-change memory cells. ESSCIRC 2011: 423-426 - 2010
- [c4]Gokce Keskin, Jonathan E. Proesel, Larry T. Pileggi:
Statistical modeling and post manufacturing configuration for scaled analog CMOS. CICC 2010: 1-4 - [c3]Jonathan E. Proesel, Gokce Keskin, Jean-Olivier Plouchart, Lawrence T. Pileggi:
An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection. CICC 2010: 1-4
2000 – 2009
- 2008
- [c2]Larry T. Pileggi, Gökçe Keskin, Xin Li, Ken Mai
Mismatch analysis and statistical design at 65 nm and below. CICC 2008: 9-12 - [c1]Jonathan E. Proesel, Lawrence T. Pileggi:
A 0.6-to-1V inverter-based 5-bit flash ADC in 90nm digital CMOS. CICC 2008: 153-156
Coauthor Index
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