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Dong-Hyuk Lim
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2020 – today
- 2023
- [j2]Timothy O. Dickson
, Zeynep Toprak Deniz
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. IEEE J. Solid State Circuits 58(4): 1074-1086 (2023) - 2022
- [c5]Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. VLSI Technology and Circuits 2022: 28-29 - [c4]Serdar S. Yonar, Pier Andrea Francese
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. VLSI Technology and Circuits 2022: 168-169 - 2020
- [c3]Byoung-Joo Yoo, Dong-Hyuk Lim, Hyonguk Pang, June-Hee Lee, Seung-Yeob Baek, Naxin Kim, Dong-Ho Choi, Young-Ho Choi, Hyeyeon Yang, Taehun Yoon, Sang-Hyeok Chu, Kangjik Kim, Woochul Jung, Bong-Kyu Kim, Jaechol Lee, Gunil Kang, Sang-Hune Park, Michael Choi, Jongshin Shin:
6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier. ISSCC 2020: 122-124
2010 – 2019
- 2014
- [j1]Jun-Eun Park
A Reconfigurable 40-to-67 dB SNR, 50-to-6400 Hz Frame-Rate, Column-Parallel Readout IC for Capacitive Touch-Screen Panels. IEEE J. Solid State Circuits 49(10): 2305-2318 (2014) - 2012
- [c2]Dong-Hyuk Lim, Jun-Eun Park
A low-noise differential front-end and its controller for capacitive touch screen panels. ESSCIRC 2012: 237-240 - 2011
- [c1]Woo-Yeol Shin, Gi-Moon Hong, Hyongmin Lee, Jaeduk Han, Sunkwon Kim, Kyu-Sang Park
A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface. ISSCC 2011: 494-496
Coauthor Index
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