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Ken Mai
Kenneth Mai – Kenneth W. Mai
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2020 – today
- 2024
- [c62]Christopher Talbot
, Deepali Garg
An IP-Agnostic Foundational Cell Array Offering Supply Chain Security. DAC 2024: 103:1-103:6 - [c61]Larry Tang, Siyuan Chen, Keshav Harisrikanth, Guanglin Xu, Franz Franchetti, Ken Mai:
A 1.19GHz 9.52Gsamples/sec Radix-8 FFT Hardware Accelerator in 28nm. HCS 2024: 1 - 2023
- [c60]Siddharth Das, McKenzie van der Hagen, Swarali Patil, Cagri Erbagci, Brandon Lucia, Ken Mai:
A 10.33 μJ/encryption Homomorphic Encryption Engine in 28nm CMOS with 4096-degree 109-bit Polynomials for Resource-Constrained IoT Clients. ESSCIRC 2023: 193-196 - [c59]Graham Gobieski, Oguz Atli, Cagri Erbagci, Ken Mai, Nathan Beckmann, Brandon Lucia:
MANIC: A $19\mu\mathrm{W}$ @ 4MHz, 256 MOPS/mW, RISC-V microcontroller with embedded MRAM main memory and vector-dataflow co-processor in 22nm bulk finFET CMOS. ISCAS 2023: 1-4 - 2022
- [c58]Larry T. Pileggi, Siyuan Chen, Keshav Harisrikanth, Guanglin Xu, Ken Mai, Franz Franchetti:
A High Throughput Hardware Accelerator for FFTW Codelets: A First Look. HPEC 2022: 1-7 - [c57]Siyuan Chen, Ken Mai:
Towards Specialized Hardware for Learning-based Visual Odometry on the Edge. IROS 2022: 10603-10610 - [i5]Elisaweta Masserova, Deepali Garg, Ken Mai, Lawrence T. Pileggi, Vipul Goyal, Bryan Parno:
Logic Locking - Connecting Theory and Practice. IACR Cryptol. ePrint Arch. 2022: 545 (2022) - 2021
- [j10]Samuel Pagliarini
Split-Chip Design to Prevent IP Reverse Engineering. IEEE Des. Test 38(4): 109-118 (2021) - [c56]Prashanth Mohan, Oguz Atli, Joseph Sweeney, Onur O. Kibar, Larry T. Pileggi, Ken Mai:
Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion. DATE 2021: 1186-1191 - [c55]Prashanth Mohan, Oguz Atli, Onur O. Kibar, V. Mohammed Zackriya, Larry T. Pileggi, Ken Mai:
Top-down Physical Design of Soft Embedded FPGA Fabrics. FPGA 2021: 1-10 - [c54]Graham Gobieski, Ahmet Oguz Atli, Kenneth Mai, Brandon Lucia, Nathan Beckmann:
Snafu: An Ultra-Low-Power, Energy-Minimal CGRA-Generation Framework and Architecture. ISCA 2021: 1027-1040 - 2020
- [c53]Prashanth Mohan, Oguz Atli, Onur O. Kibar, Ken Mai:
A Top-Down Design Methodology for Synthesizing FPGA Fabrics Using Standard ASIC Flow. FPGA 2020: 313 - [c52]Prashanth Mohan, Wen Wang, Bernhard Jungk, Ruben Niederhagen, Jakub Szefer, Ken Mai:
ASIC Accelerator in 28 nm for the Post-Quantum Digital Signature Scheme XMSS. ICCD 2020: 656-662
2010 – 2019
- 2019
- [j9]Burak Erbagci, Nail Etkin Can Akkaya, Mudit Bhargava, Rachel Dondero, Ken Mai:
Secure hardware-entangled field programmable gate arrays. J. Parallel Distributed Comput. 131: 81-96 (2019) - [c51]Burak Erbagci, Nail Etkin Can Akkaya, Cagri Erbagci, Ken Mai:
An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS. ESSCIRC 2019: 65-68 - 2018
- [c50]Prashanth Mohan, Nail Etkin Can Akkaya, Burak Erbagci, Ken Mai:
A compact energy-efficient pseudo-static camouflaged logic family. HOST 2018: 96-102 - [c49]Nail Etkin Can Akkaya, Burak Erbagci, Ken Mai:
Secure chip odometers using intentional controlled aging. HOST 2018: 111-117 - [c48]Nail Etkin Can Akkaya, Burak Erbagci, Ken Mai:
A secure camouflaged logic family using post-manufacturing programming with a 3.6GHz adder prototype in 65nm CMOS at 1V nominal VDD. ISSCC 2018: 128-130 - [i4]Yu Cai, Yixin Luo, Erich F. Haratsch, Ken Mai, Saugata Ghose, Onur Mutlu:
Experimental Characterization, Optimization, and Recovery of Data Retention Errors in MLC NAND Flash Memory. CoRR abs/1805.02819 (2018) - [i3]Yu Cai, Yixin Luo, Saugata Ghose, Erich F. Haratsch, Ken Mai, Onur Mutlu:
Read Disturb Errors in MLC NAND Flash Memory. CoRR abs/1805.03283 (2018) - [i2]Yu Cai, Saugata Ghose, Yixin Luo, Ken Mai, Onur Mutlu, Erich F. Haratsch:
Characterizing, Exploiting, and Mitigating Vulnerabilities in MLC NAND Flash Memory Programming. CoRR abs/1805.03291 (2018) - 2017
- [c47]Yu Cai, Saugata Ghose, Yixin Luo, Ken Mai, Onur Mutlu, Erich F. Haratsch:
Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques. HPCA 2017: 49-60 - 2016
- [j8]Fangfei Liu, Hao Wu, Kenneth Mai, Ruby B. Lee:
Newcache: Secure Cache Architecture Thwarting Cache Side-Channel Attacks. IEEE Micro 36(5): 8-16 (2016) - [c46]Burak Erbagci, Cagri Erbagci, Nail Etkin Can Akkaya, Ken Mai:
A secure camouflaged threshold voltage defined logic family. HOST 2016: 229-235 - [c45]Cagla Cakir, Ron Ho, Jon K. Lexau, Ken Mai:
Scalable High-Radix Modular Crossbar Switches. Hot Interconnects 2016: 37-44 - [c44]L. Richard Carley, Gurkan Colak, Louis Chomas, Larry T. Pileggi, Kenneth Mai:
Technologies for secure RFID authentication of medicinal pills and capsules. RFID-TA 2016: 10-15 - 2015
- [j7]Ramesh Karri
Guest Editorial Special Section on Hardware Security and Trust. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(6): 873-874 (2015) - [c43]Burak Erbagci, Fangfei Liu, Cagla Cakir, Nail Etkin Can Akkaya, Ruby B. Lee, Ken Mai:
A 32kB secure cache memory with dynamic replacement mapping in 65nm bulk CMOS. A-SSCC 2015: 1-4 - [c42]Burak Erbagci, Nail Etkin Can Akkaya, Craig Teegarden, Ken Mai:
A 275 Gbps AES encryption accelerator using ROM-based S-boxes in 65nm. CICC 2015: 1-4 - [c41]Mudit Bhargava, Kaship Sheikh, Ken Mai:
Robust true random number generator using hot-carrier injection balanced metastable sense amplifiers. HOST 2015: 7-13 - [c40]Nail Etkin Can Akkaya, Burak Erbagci, Raymond Carley, Ken Mai:
A DPA-resistant self-timed three-phase dual-rail pre-charge logic family. HOST 2015: 112-117 - [c39]Yu Cai, Yixin Luo, Erich F. Haratsch, Ken Mai, Onur Mutlu:
Data retention in MLC NAND flash memory: Characterization, optimization, and recovery. HPCA 2015: 551-563 - [c38]Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu
Statistical Learning in Chip (SLIC). ICCAD 2015: 664-669 - [c37]Cagla Cakir, Ron Ho, Jon K. Lexau, Ken Mai:
High-efficiency crossbar switches using capacitively coupled signaling. ISLPED 2015: 98-103 - [c36]Michael Papamichael, Cagla Cakir, Chen Sun, Chia-Hsin Owen Chen, James C. Hoe, Ken Mai, Li-Shiuan Peh, Vladimir Stojanovic:
DELPHI: a framework for RTL-based architecture design evaluation using DSENT models. ISPASS 2015: 11-20 - [c35]Yu Cai, Ken Mai, Onur Mutlu:
Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks. ISQED 2015: 475-484 - [c34]Cagla Cakir, Ron Ho, Jon K. Lexau, Ken Mai:
Modeling and Design of High-Radix On-Chip Crossbar Switches. NOCS 2015: 20:1-20:8 - [c33]Burak Erbagci, Mudit Bhargava, Rachel Dondero, Ken Mai:
Deeply hardware-entangled reconfigurable logic and interconnect. ReConFig 2015: 1-8 - [i1]Mudit Bhargava, Ken Mai:
A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement. IACR Cryptol. ePrint Arch. 2015: 427 (2015) - 2014
- [c32]Mudit Bhargava, Ken Mai:
An efficient reliable PUF-based cryptographic key generator in 65nm CMOS. DATE 2014: 1-6 - [c31]Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu
SLIC: Statistical learning in chip. ISIC 2014: 119-123 - [c30]Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Osman S. Unsal, Adrián Cristal, Ken Mai:
Neighbor-cell assisted error correction for MLC NAND flash memories. SIGMETRICS 2014: 491-504 - 2013
- [c29]Mudit Bhargava, Ken Mai:
A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement. CHES 2013: 90-106 - [c28]Yu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai:
Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling. DATE 2013: 1285-1290 - [c27]Yu Cai, Onur Mutlu, Erich F. Haratsch, Ken Mai
Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation. ICCD 2013: 123-130 - [c26]Ben Niewenhuis, Ronald D. Blanton, Mudit Bhargava, Ken Mai
SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states. ITC 2013: 1-8 - [c25]Jangwoo Kim, Hyunggyun Yang, Mark P. McCartney, Mudit Bhargava, Ken Mai
Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC. PRDC 2013: 98-107 - 2012
- [c24]Mudit Bhargava, Cagla Cakir, Ken Mai
Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS. CICC 2012: 1-4 - [c23]Cagla Cakir, Mudit Bhargava, Ken Mai
6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS. CICC 2012: 1-4 - [c22]Yu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai:
Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis. DATE 2012: 521-526 - [c21]Eric S. Chung, Michael Papamichael, Gabriel Weisz, James C. Hoe, Ken Mai
Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing. FPGA 2012: 139-142 - [c20]Mudit Bhargava, Cagla Cakir, Ken Mai
Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS. HOST 2012: 25-30 - [c19]Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Adrián Cristal
Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime. ICCD 2012: 94-101 - 2011
- [c18]Yu Cai, Erich F. Haratsch, Mark P. McCartney, Ken Mai
FPGA-Based Solid-State Drive Prototyping Platform. FCCM 2011: 101-104 - [c17]Eric S. Chung, James C. Hoe, Ken Mai
CoRAM: an in-fabric memory architecture for FPGA-based computing. FPGA 2011: 97-106 - [c16]Yu Cai, Erich F. Haratsch, Mark P. McCartney, Mudit Bhargava, Ken Mai:
FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only). FPGA 2011: 284 - 2010
- [j6]David S. Ricketts, James A. Bain
Enhancing CMOS Using Nanoelectronic Devices: A Perspective on Hybrid Integrated Systems. Proc. IEEE 98(12): 2061-2075 (2010) - [c15]Satyanand Nalam, Mudit Bhargava, Ken Mai
Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers. DAC 2010: 138-143 - [c14]Eric Menendez, Ken Mai
A Comparison of Power-analysis-resistant Digital Circuits. HOST 2010: 64-69 - [c13]Mudit Bhargava, Cagla Cakir, Ken Mai:
Attack Resistant Sense Amplifier based PUFs (SA-PUF) with Deterministic and Controllable Reliability of PUF Responses. HOST 2010: 106-111 - [c12]Craig Teegarden, Mudit Bhargava, Ken Mai
Side-channel Attack Resistant ROM-based AES S-Box. HOST 2010: 124-129 - [c11]Eric S. Chung, Peter A. Milder
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs? MICRO 2010: 225-236 - [e1]Jim Plusquellic, Ken Mai:
HOST 2010, Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 13-14 June 2010, Anaheim Convention Center, California, USA. IEEE Computer Society 2010, ISBN 978-1-4244-7810-1 [contents]
2000 – 2009
- 2009
- [j5]Eric S. Chung, Michael Papamichael, Eriko Nurvitadhi, James C. Hoe, Ken Mai
ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(2): 15:1-15:32 (2009) - [c10]Mudit Bhargava, Mark P. McCartney, Alexander Hoefler, Ken Mai
Low-overhead, digital offset compensated, SRAM sense amplifiers. CICC 2009: 705-708 - [c9]Satyanand Nalam, Mudit Bhargava, Kyle Ringgenberg, Ken Mai
A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes. ICCD 2009: 523-528 - 2008
- [j4]Benton H. Calhoun, Yu Cao, Xin Li, Ken Mai
Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS. Proc. IEEE 96(2): 343-365 (2008) - [c8]Larry T. Pileggi, Gökçe Keskin, Xin Li, Ken Mai
Mismatch analysis and statistical design at 65 nm and below. CICC 2008: 9-12 - [c7]Umut Arslan, Mark P. McCartney, Mudit Bhargava, Xin Li, Ken Mai
Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines. CICC 2008: 415-418 - [c6]Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. FPGA 2008: 77-86 - [c5]Eric Menendez, Ken Mai
A High-Performance, Low-Overhead, Power-Analysis-Resistant, Single-Rail Logic Style. HOST 2008: 33-36 - 2007
- [c4]Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
PROToFLEX: FPGA-accelerated Hybrid Functional Simulator. IPDPS 2007: 1-6 - [c3]Jangwoo Kim, Nikos Hardavellas
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding. MICRO 2007: 197-209 - 2005
- [j3]Ken Mai
Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS. IEEE J. Solid State Circuits 40(1): 261-275 (2005) - 2001
- [j2]Ron Ho, Kenneth Mai
The future of wires. Proc. IEEE 89(4): 490-504 (2001) - 2000
- [c2]Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, Mark Horowitz:
Smart Memories: a modular reconfigurable architecture. ISCA 2000: 161-171
1990 – 1999
- 1999
- [c1]Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz:
Interconnect scaling implications for CAD. ICCAD 1999: 425-429 - 1998
- [j1]Kenneth W. Mai
Low-power SRAM design using half-swing pulse-mode techniques. IEEE J. Solid State Circuits 33(11): 1659-1671 (1998)
Coauthor Index
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last updated on 2024-12-02 22:34 CET by the dblp team
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