Microprocessors and Microsystems, Volume 39

Volume 39, Number 1, February 2015

• 
  Lichen Weng, Chen Liu:
  A resource utilization based instruction fetch policy for SMT processors. 1-10
• 
  Masoud Oveis Gharan, Gul N. Khan:
  Statically adaptive multi FIFO buffer architecture for network on chip. 11-26
• 
  Reza Sabbaghi-Nadooshan, Ahmad Patooghy:
  Analytical performance modeling of de Bruijn inspired mesh-based network-on-chips. 27-36
• 
  Alejandro Valero, Salvador Petit, Julio Sahuquillo, David R. Kaeli, José Duato:
  A reuse-based refresh policy for energy-aware eDRAM caches. 37-48

Volume 39, Number 2, March 2015

• 
  Mohammad Khavari Tavana, Saba Ahmadian Khameneh, Maziar Goudarzi:
  Dynamically adaptive register file architecture for energy reduction in embedded processors. 49-63
• 
  Javier Olivito, Ruben Gran, Javier Resano, Carlos González, Enrique F. Torres:
  Performance and energy efficiency analysis of a Reversi player for FPGAs and General Purpose Processors. 64-73
• 
  Luis Pizano-Escalante, Ramón Parra-Michel, J. Vazquez Castillo, Omar Humberto Longoria-Gandara:
  Fast bit-accurate reciprocal square root. 74-82
• 
  Farimah Farahmandi, Bijan Alizadeh:
  Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction. 83-96
• 
  Hamad Marzouqi, Mahmoud Al-Qutayri, Khaled Salah:
  Review of Elliptic Curve Cryptography processor designs. 97-112
• 
  KyuHee Lee, SangKyun Yun:
  Hybrid memory-efficient multimatch packet classification for NIDS. 113-121
• 
  Chien-Chi Chen, Sheng-De Wang:
  A hybrid multiple-character transition finite-automaton for string matching engine. 122-134
• 
  W. Kurdthongmee:
  A low latency minimum distance searching unit of the SOM based hardware quantizer. 135-143

Volume 39, Number 3, May 2015

• 
  Seyed Mohammad Hossein Shekarian, Morteza Saheb Zamani:
  Improving hardware Trojan detection by retiming. 145-156
• 
  Mehdi Dehbashi, Görschwin Fey:
  Transaction-based online debug for NoC-based multiprocessor SoCs. 157-166
• 
  Chengjun Wang, Sanjeev Baskiyar:
  Extending flash lifetime in secondary storage. 167-180
• 
  Nitin Chaturvedi, S. Gurunarayanan:
  An efficient adaptive block pinning for multicore architectures. 181-188
• 
  Ke Pang, Virginie Fresse, Suying Yao, Otávio Alcântara de Lima Júnior:
  Task mapping and mesh topology exploration for an FPGA-based network on chip. 189-199
• 
  Baishik Biswas, Rohan Mukherjee, Indrajit Chakrabarti:
  Efficient architecture of adaptive rood pattern search technique for fast motion estimation. 200-209
• 
  Eesa Nikahd, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi:
  One-way quantum computer simulation. 210-222

Volume 39, Numbers 4-5, June-July 2015

• 
  Uche Afam Nnolim:
  Design and implementation of novel, fast, pipelined HSI2RGB and log-hybrid RGB2HSI colour converter architectures for image enhancement. 223-236
• 
  Seyed A. Rooholamin, Sotirios G. Ziavras:
  Modular vector processor architecture targeting at data-level parallelism. 237-249
• 
  Tomasz Szydlo, Robert Brzoza-Woch:
  Predictive power consumption adaptation for future generation embedded devices powered by energy harvesting sources. 250-258
• 
  Mehdi Jemai, Bouraoui Ouni:
  Hardware software partitioning of control data flow graph on system on programmable chip. 259-270
• 
  Ying Zhang, Lide Duan, Bin Li, Lu Peng, Sadagopan Srinivasan:
  Cross-architecture prediction based scheduling for energy efficient execution on single-ISA heterogeneous chip-multiprocessors. 271-285
• 
  Cong Thuan Do, Hong Jun Choi, Jong-Myon Kim, Cheol Hong Kim:
  A new cache replacement algorithm for last-level caches by exploiting tag-distance correlation of cache lines. 286-295
• 
  Mahmood Fazlali, Hadi Valikhani, Somayeh Timarchi, Hadi Tabatabaee Malazi:
  Fast architecture for decimal digit multiplication. 296-301
• 
  Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid:
  FPGA-based many-core System-on-Chip design. 302-312
• 
  Naijun Zheng, Huaxi Gu, Xin Huang, Xiaokang Chen:
  CSquare: A new kilo-core-oriented topology. 313-320
• 
  Dionisios N. Pnevmatikatos, Kyprianos Papadimitriou, Tobias Becker, Peter Böhm, Andreas Brokalakis, Karel Bruneel, Catalin Bogdan Ciobanu, Tom Davidson, Georgi Gaydadjiev, Karel Heyse, Wayne Luk, Xinyu Niu, Ioannis Papaefstathiou, Danilo Pau, Oliver Pell, Christian Pilato, Marco D. Santambrogio, Donatella Sciuto, Dirk Stroobandt, Tim Todman, Elias Vansteenkiste:
  FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration. 321-338

Volume 39, Number 6, August 2015

• 
  Weina Zhou, Huafeng Wu, Xiaoyang Zeng:
  A low cost architecture for high performance face detection. 339-347
• 
  Muruganantham Arunraja, Veluchamy Malathi, Erulappan Sakthivel:
  Energy conservation in WSN through multilevel data reduction scheme. 348-357
• 
  Junxiu Liu, Jim Harkin, Yuhua Li, Liam P. Maguire:
  Low cost fault-tolerant routing algorithm for Networks-on-Chip. 358-372
• 
  Vipin Tiwari, Nilay Khare:
  Hardware implementation of neural network with Sigmoidal activation functions using CORDIC. 373-381
• 
  Lilian Bossuet, Viktor Fischer, Lubos Gaspar, Lionel Torres, Guy Gogniat:
  Disposable configuration of remotely reconfigurable systems. 382-392
• 
  Marwa Chouchene, Fatma Ezahra Sayadi, Haythem Bahri, Julien Dubois, Johel Mitéran, Mohamed Atri:
  Optimized parallel implementation of face detection based on GPU component. 393-404
• 
  Atef Benhaoues, Salah Toumi, Camel Tanougast, El-Bay Bourennane, Kamel Messaoudi, Hichem Mayache:
  Versatile digital architecture for mobile terminal. 405-417
• 
  Carlos Avelino de Barros, Luiz Felipe Q. Silveira, Carlos Valderrama, Samuel Xavier de Souza:
  Optimal processor dynamic-energy reduction for parallel workloads on heterogeneous multi-core architectures. 418-425
• 
  Razieh Farazkish, Fatemeh Khodaparast:
  Design and characterization of a new fault-tolerant full-adder for quantum-dot cellular automata. 426-433

Volume 39, Number 7, October 2015

• 
  Jaspal S. Sagoo:
  Formal approach for the safety assessment of embedded controller based on programmable electronic hardware. 435-443
• 
  Bin Zhang, Kuizhi Mei, Jizhong Zhao:
  Matrix computing coprocessor for an embedded system. 444-456
• 
  Naeem Abbas, Steven Derrien, Sanjay V. Rajopadhye, Patrice Quinton, Alexandre Cornu, Dominique Lavenier:
  Combining execution pipelines to improve parallel implementation of HMMER on FPGA. 457-470
• 
  Alper Sen, Etem Deniz:
  Thread-level synthetic benchmarks for multicore systems. 471-479
• 
  Abolfazl Soltani, Saeed Sharifian:
  An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA. 480-493
• 
  C.-A. Tavera-Vaca, Dora Luz Almanza-Ojeda, Mario Alberto Ibarra-Manzano:
  Analysis of the efficiency of the census transform algorithm implemented on FPGA. 494-503
• 
  Sandeep Raj, G. S. S. Praveen Chand, Kailash Chandra Ray:
  ARM-based arrhythmia beat monitoring system. 504-511
• 
  Shaahin Angizi, Mohammad Hossein Moaiyeri, Shohreh Farrokhi, Keivan Navi, Nader Bagherzadeh:
  Designing quantum-dot cellular automata counters with energy consumption analysis. 512-520
• 
  S. Padmapriya, V. Lakshmi Prabha:
  Design of an efficient dual mode reconfigurable FIR filter architecture in speech signal processing. 521-528
• 
  Paulo Da Cunha Possa, Naim Harb, Eva Dokládalová, Carlos Valderrama:
  P²IP: A novel low-latency Programmable Pipeline Image Processor. 529-540

Special Section on Reconfigurable Computing and FPGAs

• 
  René Cumplido, Eduardo de la Torre, Claudia Feregrino Uribe, Michael J. Wirthlin:
  Introduction to Special issue on Reconfigurable computing and FPGAs. 541-542
• 
  Markus Weinhardt, Bernhard Lang, Frank M. Thiesing, Alexander Krieger, Thomas Kinder:
  SAccO: An implementation platform for scalable FPGA accelerators. 543-552
• 
  Mingjie Lin, Shaoyi Cheng, Ronald F. DeMara, John Wawrzynek:
  ASTRO: Synthesizing application-specific reconfigurable hardware traces to exploit memory-level parallelism. 553-564
• 
  Yann Thoma, Alberto Dassatti, Daniel Molla, Enrico Petraglio:
  FPGA-GPU communicating through PCIe. 565-575
• 
  Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido:
  Processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs. 576-588
• 
  Aydin Aysu, Patrick Schaumont:
  Hardware/software co-design of physical unclonable function based authentications on FPGAs. 589-597

Volume 39, Number 8, November 2015

Research papers

• 
  Christoforos Kachris, Georgios Ch. Sirakoulis, Dimitrios Soudris:
  A MapReduce scratchpad memory for multi-core cloud computing applications. 599-608
• 
  Kamel Messaoudi, Hichem Mayache, Atef Benhaoues, El-Bay Bourennane, Salah Toumi:
  Connection of H.264/AVC hardware IPs using a specific Networks-on-Chip. 609-620
• 
  Sarayut Amornwongpeeti, Mongkol Ekpanyapong, Nattapon Chayopitak, João L. Monteiro, Júlio S. Martins, João Luiz Afonso:
  A single chip FPGA-based solution for controlling of multi-unit PMSM motor with time-division multiplexing scheme. 621-633
• 
  Awet Yemane Weldezion, Matt Grange, Axel Jantsch, Hannu Tenhunen, Dinesh Pamunuwa:
  Zero-load predictive model for performance analysis in deflection routing NoCs. 634-647
• 
  Ralf Joost, Matthias Hinkfoth:
  Combining BOUNCE and X-ORCA: Improving their real-world utility. 648-655
• 
  Gorker Alp Malazgirt, Arda Yurdakul, Smaïl Niar:
  Customizing VLIW processors from dynamically profiled execution traces. 656-673
• 
  Azam Beg, Falah Awwad, Walid Ibrahim, Faheem Ahmed:
  On the reliability estimation of nano-circuits using neural networks. 674-685
• 
  Shuai Wang, Guangshan Duan:
  On the characterization and optimization of system-level vulnerability for instruction caches in embedded processors. 686-692
• 
  Juan Carlos Moctezuma, Joseph P. McGeehan, José Luis Núñez-Yáñez:
  Biologically compatible neural networks with reconfigurable hardware. 693-703
• 
  Hamed Tabkhi, Robert Bushey, Gunar Schirner:
  Conceptual Abstraction Levels (CALs) for managing design complexity of market-oriented MPSoCs. 704-719
• 
  Madhu Monga, Daniel Roggow, Manoj Karkee, Song Sun, Lakshmi Kiran Tondehal, Brian L. Steward, Atul G. Kelkar, Joseph Zambreno:
  Real-time simulation of dynamic vehicle models using a high-performance reconfigurable platform. 720-740
• 
  N. Prasad, Santanu Chattopadhyay, Indrajit Chakrabarti:
  Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip. 741-751
• 
  Tassadaq Hussain:
  HMMC: A memory controller for heterogeneous Multi-core System. 752-766
• 
  Joon Goo Lee, Seon Wook Kim, Dong-Hyun Kim, Younga Cho, Jae-Sung Rieh, Gyusung Kang, Jongsun Park, Hokyu Lee, Sejin Park, Chulwoo Kim:
  D²ART: Direct Data Accessing from Passive RFID Tag for infra-less, contact-less, and battery-less pervasive computing. 767-781
• 
  Vuk S. Vranjkovic, Rastislav J. R. Struharik, Ladislav A. Novak:
  Hardware acceleration of homogeneous and heterogeneous ensemble classifiers. 782-795
• 
  Hossein Mehri, Bijan Alizadeh:
  Analytical performance model for FPGA-based reconfigurable computing. 796-806
• 
  Andreas Thor Winther, Wei Liu, Alberto Nannarelli, Sarma B. K. Vrudhula:
  Thermal aware floorplanning incorporating temperature dependent wire delay estimation. 807-815

Special section on Cyber-Physical Systems: Extending the Networks to the Real-World

• 
  Davide Quaglia, Marc Geilen:
  Introduction to special issue on cyber-physical systems. 817
• 
  Andrej Skraba, Radovan Stojanovic, Anton Zupan, Andrej Kolozvari, Davorin Kofjac:
  Speech-controlled cloud-based wheelchair platform for disabled persons. 819-828
• 
  Ashray A. Doshi, Adam J. Postula, Andrew Fletcher, Surya P. N. Singh:
  Development of micro-UAV with integrated motion planning for open-cut mining surveillance. 829-835
• 
  Davide Bresolin, Luca Geretti, Riccardo Muradore, Paolo Fiorini, Tiziano Villa:
  Formal verification of robotic surgery tasks by reachability analysis. 836-842
• 
  Michele Lora, Riccardo Muradore, Davide Quaglia, Franco Fummi:
  Simulation alternatives for the verification of networked cyber-physical systems. 843-853
• 
  Víctor Fernández, Andrés Mena, Cédric Ben Aoun, François Pêcheux, Luis J. Fernández:
  Virtual prototyping of pressure driven microfluidic systems with SystemC-AMS extensions. 854-865

Special section on selected papers from NORCHIP 2013

• 
  Dalius Navakauskas, Arturas Serackis:
  Special issue on selected papers from NORCHIP 2013. 867-868
• 
  Yanxiang Huang, Ajay Kapoor, Robert Rutten, José Pineda de Gyvez:
  A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain with Carry-Save format numbers. 869-878
• 
  Felice Francesco Tafuri, Daniel Sira, Troels Studsgaard Nielsen, Ole Kiel Jensen, Jan Hvolgaard Mikkelsen, Torben Larsen:
  Memory models for behavioral modeling and digital predistortion of envelope tracking power amplifiers. 879-888
• 
  Isael Diaz, Chenxin Zhang, Lieven Hollevoet, Jim Svensson, Joachim Neves Rodrigues, Leif R. Wilhelmsson, Thomas Olsson, Liesbet Van der Perre, Viktor Öwall:
  A new digital front-end for flexible reception in software defined radio. 889-900
• 
  Stefan Granlund, Liang Liu, Chenxin Zhang, Viktor Öwall:
  A low-latency high-throughput soft-output signal detector for spatial multiplexing MIMO systems. 901-908
• 
  Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min:
  Functional self-test of high-performance pipe-lined signal processing architectures. 909-918

Special section on Design of Circuits and Integrated Systems in the Nanoelectronics and Nanotechnology Era (DCIS)

• 
  Eduardo de la Torre, Jorge Portilla, Teresa Riesgo:
  Letter from the guest editors of the special issue on DCIS 2014. 919
• 
  Gabriel Mujica, Jorge Portilla, Teresa Riesgo:
  Performance evaluation of an AODV-based routing protocol implementation by using a novel in-field WSN diagnosis tool. 920-938
• 
  José-Ignacio Rejas, Alberto Sánchez, Guillermo Glez. de Rivera, Manuel Prieto, Javier Garrido Salas:
  Environment mapping using a 3D laser scanner for unmanned ground vehicles. 939-949
• 
  Chang-Chih Chen, Taizhi Liu, Soonyoung Cha, Linda S. Milor:
  Processor-level reliability simulator for time-dependent gate dielectric breakdown. 950-960

Special section on Euromicro Conference on Digital Systems Design 2014

• 
  Francesco Leporati, José Silva Matos:
  MICPRO DSD 2014 special issue. 961
• 
  Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
  Ultra-low power circuits using graphene p-n junctions and adiabatic computing. 962-972
• 
  Syed M. A. H. Jafri, Masoud Daneshtalab, Ahmed Hemani, Naeem Abbas, Muhammad Ali Awan, Juha Plosila:
  TEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAs. 973-986
• 
  Luis Araneda, Miguel E. Figueroa:
  A compact hardware architecture for digital image stabilization using integral projections. 987-997
• 
  Ang Li, Akash Kumar, Yajun Ha, Henk Corporaal:
  Correlation ratio based volume image registration on GPUs. 998-1011
• 
  Joachim Falk, Tobias Schwarzer, Liyuan Zhang, Michael Glaß, Jürgen Teich:
  Automatic communication-driven virtual prototyping and design for networked embedded systems. 1012-1028
• 
  Fardin Derogarian, João Canas Ferreira, Vítor M. Grade Tavares:
  A time synchronization circuit with sub-microsecond skew for multi-hop wired wearable networks. 1029-1038
• 
  Halil Kükner, Pieter Weckx, Sébastien Morrison, Jacopo Franco, Maria Toledano-Luque, Moonju Cho, Praveen Raghavan, Ben Kaczer, Doyoung Jang, Kenichi Miyaguchi, Marie Garcia Bardon, Francky Catthoor, Liesbet Van der Perre, Rudy Lauwereins, Guido Groeseneken:
  Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes. 1039-1051
• 
  Antonios Prodromakis, Stelios Korkotsides, Theodore Antonakopoulos:
  MLC NAND Flash memory: Aging effect and chip/channel emulation. 1052-1062
• 
  Simon Reder, Christoph Roth, Harald Bucher, Oliver Sander, Jürgen Becker:
  Adaptive algorithm and tool flow for accelerating SystemC on many-core architectures. 1063-1075
• 
  Massimiliano Zilli, Wolfgang Raschke, Reinhold Weiss, Johannes Loinig, Christian Steger:
  Hardware/software co-design for a high-performance Java Card interpreter in low-end embedded systems. 1076-1086
• 
  Shubhendu Sinha, Martijn Koedam, Gabriela Breaban, Andrew Nelson, Ashkan Beyranvand Nejad, Marc Geilen, Kees Goossens:
  Composable and predictable dynamic loading for time-critical partitioned systems on multiprocessor architectures. 1087-1107
• 
  Bouthaina Dammak, Mouna Baklouti, Rachid Benmansour, Smaïl Niar, Mohamed Abid:
  Hardware resource utilization optimization in FPGA-based Heterogeneous MPSoC architectures. 1108-1118
• 
  Ralph Nyberg, Johann Heyszl, Dirk Rabe, Georg Sigl:
  Closing the gap between speed and configurability of multi-bit fault emulation environments for security and safety-critical designs. 1119-1129
• 
  Jaak Kousaar, Raimund Ubar, Sergei Devadze, Jaan Raik:
  Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra. 1130-1138
• 
  Apostolos P. Fournaris, Ioannis Zafeirakis, Paris Kitsos, Odysseas G. Koufopavlou:
  Comparing design approaches for elliptic curve point multiplication over GF(2^k) with polynomial basis representation. 1139-1155

Special section on European Projects in Embedded Digital Systems Design

• 
  Francesco Leporati, Lech Józwiak:
  MICPRO special issue on European projects in embedded system design 2014. 1157
• 
  Nicola Bombieri, Dimitrios Drogoudis, Giuliana Gangemi, Renaud Gillon, Michelangelo Grosso, Enrico Macii, Massimo Poncino, Salvatore Rinaudo:
  Addressing the Smart Systems design challenge: The SMAC platform. 1158-1173
• 
  Santhosh Kumar Rethinagiri, Oscar Palomar, Anita Sobe, Gulay Yalcin, Thomas Knauth, J. Rubén Titos Gil, Pablo Prieto, Malte Schneegaß, Adrián Cristal, Osman S. Unsal, Pascal Felber, Christof Fetzer, Dragomir Milojevic:
  ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers. 1174-1189
• 
  Luís Miguel Pinho, Vincent Nélis, Patrick Meumeu Yomsi, Eduardo Quiñones, Marko Bertogna, Paolo Burgio, Andrea Marongiu, Claudio Scordino, Paolo Gai, Michele Ramponi, Michal Mardiak:
  P-SOCRATES: A parallel software framework for time-critical many-core systems. 1190-1203
• 
  Alessandro Vallero, Sotiris Tselonis, Nikos Foutris, Manolis Kaliorakis, Maha Kooli, Alessandro Savino, Gianfranco Politano, Alberto Bosio, Giorgio Di Natale, Dimitris Gizopoulos, Stefano Di Carlo:
  Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview. 1204-1214
• 
  Jakub Podivinsky, Ondrej Cekan, Marcela Simková, Zdenek Kotásek:
  The evaluation platform for testing fault-tolerance methodologies in electro-mechanical applications. 1215-1230

Special section on Innovative Circuit and System Design Methodologies for Green Cyber-Physical Systems

• 
  Jiafu Wan, Chin-Feng Lai, Shiwen Mao, Eugenio Villar, Subhas Mukhopadhyay:
  Innovative circuit and system design methodologies for green cyber-physical systems. 1231-1233
• 
  Song Li, Di Li, Fang Li, Nan Zhou:
  CPSiCGF: A code generation framework for CPS integration modeling. 1234-1244
• 
  Fulong Chen, Heping Ye, Jie Yang, Yong Huang, Ji Zhang, Xuemei Qi, Chuanxin Zhao, Junru Zhu, Wen Zhou:
  A standardized design methodology for complex digital logic components of cyber-physical systems. 1245-1254
• 
  Shiyong Wang, Chunhua Zhang, Dongyao Jia:
  Improvement of type declaration of the IEC 61499 basic function block for developing applications of cyber-physical system. 1255-1261
• 
  Xuejun Yue, Hu Cai, Hehua Yan, Caifeng Zou, Keliang Zhou:
  Cloud-assisted industrial cyber-physical systems: An insight. 1262-1270
• 
  Guangjie Han, Aihua Qian, Li Liu, Jinfang Jiang, Chuan Zhu:
  Impacts of traveling paths on energy provisioning for industrial wireless rechargeable sensor networks. 1271-1278
• 
  Yujun Ma, Chi Harold Liu, Musaed A. Alhussein, Yin Zhang, Min Chen:
  LTE-based humanoid robotics system. 1279-1284
• 
  Tie Qiu, Lin Chi, Weidong Guo, Yushuang Zhang:
  STETS: A novel energy-efficient time synchronization scheme based on embedded networking devices. 1285-1295
• 
  Pan Deng, Gang Ren, Wei Yuan, Feng Chen, Qingsong Hua:
  An integrated framework of formal methods for interaction behaviors among industrial equipments. 1296-1304
• 
  Chun-Wei Tsai, Pei-wei Tsai, Jeng-Shyang Pan, Han-Chieh Chao:
  Metaheuristics for the deployment problem of WSN: A review. 1305-1317