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Claudia Feregrino Uribe
Claudia Feregrino
Person information
- affiliation: National Institute of Astrophysics, Optics and Electronics, Puebla, Mexico
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2020 – today
- 2024
- [j58]Alejandro Peñuelas-Angulo
, Claudia Feregrino Uribe
A revocable multi-authority attribute-based encryption scheme for fog-enabled IoT. J. Syst. Archit. 155: 103265 (2024) - [j57]Martín Letras
A novel partition strategy for efficient implementation of 3D Cellular Genetic Algorithms. Microprocess. Microsystems 104: 104986 (2024) - [j56]Jesus Fonseca-Bustos
A robust self-supervised image hashing method for content identification with forensic detection of content-preserving manipulations. Neural Networks 177: 106357 (2024) - [c57]Kevin Saúl Gómez-Molina, Jesus Fonseca-Bustos, Claudia Feregrino Uribe:
A Robust Content Identification System for Picture-In-Picture Attack Detection Using Trainable Background Removal and Perceptual Hashing Functions. MCPR 2024: 210-219 - 2023
- [j55]Alejandro Peñuelas-Angulo
An adaptive method for prevention of overflow in reversible data hiding schemes. Expert Syst. Appl. 230: 120610 (2023) - [j54]Alejandro Peñuelas-Angulo
Revocation in attribute-based encryption for fog-enabled internet of things: A systematic survey. Internet Things 23: 100827 (2023) - [j53]Mireya Lucia Hernandez-Jaimes, Alfonso Martínez-Cruz
Artificial intelligence for IoMT security: A review of intrusion detection systems, attacks, datasets and Cloud-Fog-Edge architectures. Internet Things 23: 100887 (2023) - [j52]Freddy Alejandro Chaurra-Gutierrez
QIST: One-dimensional quantum integer wavelet S-transform. Inf. Sci. 622: 999-1013 (2023) - [j51]Jose Juan Garcia-Hernandez
On a self-recovery digital watermarking scheme robust against spatial and temporal attacks on compressed video. J. Frankl. Inst. 360(17): 13482-13508 (2023) - [c56]Alejandro Peñuelas-Angulo
Large Universe Attribute-based Encryption with Multiple Authorities and Outsourced Decryption for Fog-enabled Internet of Things. ENC 2023: 1-8 - [c55]Raul Sánchez-Reillo, Luz Hernández-Martínez, Claudia Feregrino Uribe:
IoT Architecture and Security Mecanisms for an Energy Management System in a Smart Microgrid. CCE 2023: 1-6 - 2022
- [j50]Lázaro Bustio-Martínez
FPGA/GPU-based Acceleration for Frequent Itemsets Mining: A Comprehensive Review. ACM Comput. Surv. 54(9): 179:1-179:35 (2022) - [j49]Lázaro Bustio-Martínez
A lightweight data representation for phishing URLs detection in IoT environments. Inf. Sci. 603: 42-59 (2022) - [j48]Jesus Fonseca-Bustos
Robust image hashing for content identification through contrastive self-supervised learning. Neural Networks 156: 81-94 (2022) - [c54]Genaro Isidro Alamillo-Montes, Alfonso Martínez-Cruz
Security Scheme for an RFID Access Control based on Internet of Things. ENC 2022: 1-6 - [c53]Jesus Fonseca-Bustos
A compact and robust perceptual hashing function through self-supervised learning. MECO 2022: 1-4 - [c52]Freddy Alejandro Chaurra-Gutierrez
QBRBS: Quantum Block Representation by Basis States. QCE 2022: 125-132 - 2021
- [j47]Alfonso Martínez-Cruz
Security on in-vehicle communication protocols: Issues, challenges, and future research directions. Comput. Commun. 180: 1-20 (2021) - [j46]Jorge Echavarria, Alicia Morales-Reyes, René Cumplido, Miguel A. Salido, Claudia Feregrino Uribe:
IP-cores watermarking scheme at behavioral level using genetic algorithms. Eng. Appl. Artif. Intell. 104: 104386 (2021) - [j45]Maikel Lázaro Pérez Gort
Semantic-driven watermarking of relational textual databases. Expert Syst. Appl. 167: 114013 (2021) - [j44]Miguel Morales-Sandoval
A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks. J. Sensors 2021: 8860413:1-8860413:13 (2021) - [j43]Ignacio Algredo-Badillo
Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES. Sensors 21(16): 5655 (2021) - 2020
- [j42]Maikel Lázaro Pérez Gort
A Double Fragmentation Approach for Improving Virtual Primary Key-Based Watermark Synchronization. IEEE Access 8: 61504-61516 (2020) - [j41]Martín Letras
On the design of hardware architectures for parallel frequent itemsets mining. Expert Syst. Appl. 157: 113440 (2020)
2010 – 2019
- 2019
- [j40]Alejandra Menendez-Ortiz, Claudia Feregrino Uribe, Rogelio Hasimoto-Beltrán
A Survey on Reversible Watermarking for Multimedia Content: A Robustness Overview. IEEE Access 7: 132662-132681 (2019) - [j39]Maikel Lázaro Pérez Gort
HQR-Scheme: A High Quality and resilient virtual primary key generation approach for watermarking relational data. Expert Syst. Appl. 138 (2019) - [j38]Alejandra Menendez-Ortiz, Claudia Feregrino Uribe, Jose Juan Garcia-Hernandez:
Framework for audio reversible watermarking robust against content replacement with signal restoration capabilities. J. Frankl. Inst. 356(12): 6793-6816 (2019) - [j37]Ernesto Aparicio-Díaz, René Cumplido, Maikel L. Pérez Gort
Temporal Copy-Move Forgery Detection and Localization Using Block Correlation Matrix. J. Intell. Fuzzy Syst. 36(5): 5023-5035 (2019) - [j36]Lázaro Bustio-Martínez
Using hashing and lexicographic order for Frequent Itemsets Mining on data streams. J. Parallel Distributed Comput. 125: 58-71 (2019) - [j35]René Cumplido, Maya B. Gokhale, Claudia Feregrino, Michael Hübner:
Guest Editorial: Special Issue on Reconfigurable Computing and FPGA Technology. J. Parallel Distributed Comput. 133: 359-361 (2019) - [j34]Zobeida Jezabel Guzman-Zavaleta
Partial-copy detection of non-simulated videos using learning at decision level. Multim. Tools Appl. 78(2): 2427-2446 (2019) - [j33]Lázaro Bustio-Martínez
A novel multi-core algorithm for frequent itemsets mining in data streams. Pattern Recognit. Lett. 125: 241-248 (2019) - [c51]Maikel Lázaro Pérez Gort
Preventing Additive Attacks to Relational Database Watermarking. CONFENIS 2019: 131-140 - [c50]Ernesto Aparicio-Díaz, René Cumplido, Lázaro Bustio-Martínez
Detection And Localization Of Splicing Attacks On Videos Using Block Correlation. PACRIM 2019: 1-6 - [e4]David Andrews, René Cumplido, Claudia Feregrino, Marco Platzner:
2019 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2019, Cancun, Mexico, December 9-11, 2019. IEEE 2019, ISBN 978-1-7281-1957-1 [contents] - 2018
- [j32]Ignacio Algredo-Badillo
Lightweight Security Hardware Architecture Using DWT and AES Algorithms. IEICE Trans. Inf. Syst. 101-D(11): 2754-2761 (2018) - [j31]Lázaro Bustio-Martínez
On the design of hardware-software architectures for frequent itemsets mining on data streams. J. Intell. Inf. Syst. 50(3): 415-440 (2018) - [e3]David Andrews, René Cumplido, Claudia Feregrino, Dirk Stroobandt:
2018 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December 3-5, 2018. IEEE 2018, ISBN 978-1-7281-1968-7 [contents] - 2017
- [j30]Alejandra Menendez-Ortiz
Self-recovery scheme for audio restoration after a content replacement attack. Multim. Tools Appl. 76(12): 14197-14224 (2017) - [j29]Zobeida Jezabel Guzman-Zavaleta
A robust and low-cost video fingerprint extraction method for copy detection. Multim. Tools Appl. 76(22): 24143-24163 (2017) - [c49]Alejandra Menendez-Ortiz
Audio Reversible Watermarking Scheme in the intDCT Domain with Modified Prediction Error Expansion. IH&MMSec 2017: 105-110 - [c48]Maikel L. Pérez Gort
A Minimum Distortion: High Capacity Watermarking Technique for Relational Data. IH&MMSec 2017: 111-121 - [c47]Lázaro Bustio-Martínez
Approximate frequent itemsets mining on data streams using hashing and lexicographie order in hardware. LASCAS 2017: 1-4 - [c46]Luis Armando Rodriguez Flores, Miguel Morales-Sandoval
A compact FPGA-based microcoded coprocessor for exponentiation in asymmetric encryption. LASCAS 2017: 1-4 - 2016
- [j28]José Kadir Febrer-Hernández, Raudel Hernández-León, Claudia Feregrino Uribe, José Hernández Palancar:
SPaC-NF: A classifier based on sequential patterns with high netconf. Intell. Data Anal. 20(5): 1101-1113 (2016) - [c45]Juan Andrés Pérez-Celis, José Martínez-Carranza
An FPGA Architecture to Accelerate the Burrows Wheeler Transform by Using a Linear Sorter. IPDPS Workshops 2016: 156-161 - [c44]Zobeida Jezabel Guzman-Zavaleta
A simple approach towards efficient partial-copy video detection. MMSP 2016: 1-6 - [e2]Peter M. Athanas, René Cumplido, Claudia Feregrino, Ron Sass:
International Conference on ReConFigurable Computing and FPGAs, ReConFig 2016, Cancun, Mexico, November 30 - Dec. 2, 2016. IEEE 2016, ISBN 978-1-5090-3707-0 [contents] - 2015
- [j27]Marisol Rodriguez-Perez, Alicia Morales-Reyes
An analysis of computational models for accelerating the subtractive pixel adjacency model computation. Comput. Electr. Eng. 43: 9-16 (2015) - [j26]Vladimir Rodríguez-Diez
A fast hardware software platform for computing irreducible testors. Expert Syst. Appl. 42(24): 9612-9619 (2015) - [j25]René Cumplido, Eduardo de la Torre, Claudia Feregrino Uribe, Michael J. Wirthlin:
Introduction to Special issue on Reconfigurable computing and FPGAs. Microprocess. Microsystems 39(7): 541-542 (2015) - [c43]José Kadir Febrer-Hernández, Raudel Hernández-León, José Hernández Palancar, Claudia Feregrino Uribe:
SPaR-FTR: An Efficient Algorithm for Mining Sequential Patterns-Based Rules. CIARP 2015: 643-650 - [c42]José Kadir Febrer-Hernández, Raudel Hernández-León, José Hernández Palancar, Claudia Feregrino Uribe:
Improving the Accuracy of the Sequential Patterns-Based Classifiers. CIARP 2015: 708-715 - [c41]Lázaro Bustio
Frequent Itemsets Mining in Data Streams Using Reconfigurable Hardware. NFMCP 2015: 32-45 - 2014
- [j24]Rommel García, Ignacio Algredo-Badillo
A compact FPGA-based processor for the Secure Hash Algorithm SHA-256. Comput. Electr. Eng. 40(1): 194-202 (2014) - [j23]Claudia Feregrino Uribe, Ernesto Aparicio-Díaz, José Juan García-Hernández, Alejandra Menendez-Ortiz, René Cumplido, Alicia Morales-Reyes
Hardware architecture for security improved Fallahpour audio watermarking scheme. IEICE Electron. Express 11(9): 20140223 (2014) - [j22]Peter M. Athanas, René Cumplido, Claudia Feregrino Uribe, Eduardo de la Torre:
Introduction to Special issue on FPGA Devices and Applications. Microprocess. Microsystems 38(8): 843-844 (2014) - [j21]Lázaro Bustio-Martínez, René Cumplido-Parra, Raudel Hernández-León, Claudia Feregrino Uribe:
Hardware Acceleration of Frequent Itemsets Mining on Data Streams. Res. Comput. Sci. 71: 13-22 (2014) - [c40]José Kadir Febrer-Hernández, José Hernández Palancar, Raudel Hernández-León, Claudia Feregrino Uribe:
SPaMi-FTS: An Efficient Algorithm for Mining Frequent Sequential Patterns. CIARP 2014: 470-477 - [c39]Zobeida Jezabel Guzman-Zavaleta
A robust audio fingerprinting method using spectrograms saliency maps. ICITST 2014: 47-52 - [c38]Vladimir Rodriguez
A hardware architecture for filtering irreducible testors. ReConFig 2014: 1-4 - 2013
- [j20]Miguel Morales-Sandoval
Area/performance trade-off analysis of an FPGA digit-serial GF(2m)GF(2m) Montgomery multiplier based on LFSR. Comput. Electr. Eng. 39(2): 542-549 (2013) - [j19]Jose Juan Garcia-Hernandez, Ramón Parra-Michel, Claudia Feregrino Uribe, René Cumplido:
High payload data-hiding in audio signals based on a modified OFDM approach. Expert Syst. Appl. 40(8): 3055-3064 (2013) - [j18]Ignacio Algredo-Badillo
FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256. Microprocess. Microsystems 37(6-7): 750-757 (2013) - [c37]Francisco Aguirre-Ramos
Video Error Concealment Based on Data Hiding for the Emerging Video Technologies. PSIVT 2013: 454-467 - [c36]Juan M. Campos, René Cumplido, Claudia Feregrino Uribe, Roberto Perez-Andrade:
A parallelization methodology for reconfigurable systems applied to edge detection. ReCoSoC 2013: 1-7 - [c35]Eduardo Cuevas-Farfan, Miguel Morales-Sandoval
A programmable FPGA-based cryptoprocessor for bilinear pairings over F2m. ReCoSoC 2013: 1-8 - 2012
- [j17]Pedro Aaron Hernandez-Avalos, Claudia Feregrino Uribe, René Cumplido:
Watermarking using similarities based on fractal codification. Digit. Signal Process. 22(2): 324-336 (2012) - [j16]Alejandro Rojas, René Cumplido, Jesús Ariel Carrasco-Ochoa
Hardware-software platform for computing irreducible testors. Expert Syst. Appl. 39(2): 2203-2210 (2012) - [j15]Fernando Martin del Campo, Alicia Morales-Reyes
A multi-cycle fixed point square root module for FPGAs. IEICE Electron. Express 9(11): 971-977 (2012) - [j14]Claudia Feregrino, Miguel Arias, Kris Gaj, Viktor K. Prasanna, Marco D. Santambrogio
Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10). Int. J. Reconfigurable Comput. 2012: 319827:1-319827:2 (2012) - [c34]Ignacio Algredo-Badillo
Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm. ISVLSI 2012: 63-68 - 2011
- [j13]Miguel Morales-Sandoval
Bit-serial and digit-serial GF(2m)Montgomery multipliers using linear feedback shift registers. IET Comput. Digit. Tech. 5(2): 86-94 (2011) - [j12]Jose Juan Garcia-Hernandez, Claudia Feregrino Uribe, René Cumplido, Carolina Reta
On the Implementation of a Hardware Architecture for an Audio Data Hiding System. J. Signal Process. Syst. 64(3): 457-468 (2011) - [c33]Ignacio Algredo-Badillo
Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms. DSD 2011: 543-549 - [c32]René Cumplido, Claudia Feregrino Uribe, Jose Juan Garcia-Hernandez:
Invited paper: Implementing digital data hiding algorithms in reconfigurable hardware - Experiences on teaching and research. ReCoSoC 2011: 1-6 - 2010
- [j11]Ignacio Algredo-Badillo
Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard. Comput. Electr. Eng. 36(3): 565-577 (2010) - [j10]Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo:
A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter. Digit. Signal Process. 20(6): 1733-1747 (2010) - [j9]Jose Juan Garcia-Hernandez, Claudia Feregrino Uribe, René Cumplido, Ramón Parra-Michel:
Improving the security of Fallahpour's audio watermarking scheme. IEICE Electron. Express 7(14): 995-1001 (2010) - [j8]Miguel Morales-Sandoval
A Single Formula and its Implementation in FPGA for Elliptic Curve Point Addition Using Affine Representation. J. Circuits Syst. Comput. 19(2): 425-433 (2010) - [c31]Lázaro Bustio-Martínez
On the Design of a Hardware-Software Architecture for Acceleration of SVM's Training Phase. MCPR 2010: 281-290 - [c30]Alejandro Mesa, Claudia Feregrino Uribe, René Cumplido, José Hernández Palancar:
A Highly Parallel Algorithm for Frequent Itemset Mining. MCPR 2010: 291-300 - [i1]René Cumplido, Juan M. Campos, Claudia Feregrino Uribe, Jose Roberto Perez-Andrade:
Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for software radio systems. Dynamically Reconfigurable Architectures 2010
2000 – 2009
- 2009
- [j7]Miguel Morales-Sandoval
An area/performance trade-off analysis of a GF(2m) multiplier architecture for elliptic curve cryptography. Comput. Electr. Eng. 35(1): 54-58 (2009) - [j6]Jose Juan Garcia-Hernandez, Carolina Reta
Efficient implementation of the RDM-QIM algorithm in an FPGA. IEICE Electron. Express 6(14): 1064-1070 (2009) - [j5]Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo:
A versatile linear insertion sorter based on an FIFO scheme. Microelectron. J. 40(12): 1705-1713 (2009) - [c29]Pedro Aaron Hernandez-Avalos, Claudia Feregrino Uribe, Roger Luis Velázquez, René Cumplido-Parra:
Watermarking Based on Iterated Function Systems. ENC 2009: 339-344 - [c28]Miguel Morales-Sandoval
A Run Time Reconfigurable Co-processor for Elliptic Curve Scalar Multiplication. ENC 2009: 345-350 - [c27]Hector Borrayo-Sandoval, Ramón Parra-Michel, Luis F. Gonzalez-Perez, Fernando Landeros Printzen, Claudia Feregrino Uribe:
Design and Implementation of a Configurable Interleaver/Deinterleaver for Turbo Codes in 3GPP Standard. ReConFig 2009: 320-325 - 2008
- [j4]Tomás Balderas-Contreras, René Cumplido, Claudia Feregrino Uribe:
On the design and implementation of a RISC processor extension for the KASUMI encryption algorithm. Comput. Electr. Eng. 34(6): 531-546 (2008) - [j3]Raúl Rodríguez-Colín, Claudia Feregrino Uribe, Jose-Alberto Martinez Villanueva:
Robust Watermarking Scheme Applied to Radiological Medical Images. IEICE Trans. Inf. Syst. 91-D(3): 862-864 (2008) - [j2]Ignacio Algredo-Badillo
Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description. IEICE Trans. Inf. Syst. 91-D(10): 2519-2523 (2008) - [c26]Edgar Gomez-Hernández, Claudia Feregrino Uribe, René Cumplido:
FPGA Hardware Architecture of the Steganographic ConText Technique. CONIELECOMP 2008: 123-128 - [c25]Ariel Molina-Rueda, Fernando Uceda-Ponga, Claudia Feregrino Uribe:
Extended Period LFSR Using Variable TAP Function. CONIELECOMP 2008: 129-132 - [c24]Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo:
A versatile hardware architecture for a CFAR detector based on a linear insertion sorter. FPL 2008: 467-470 - [c23]Roberto Perez-Andrade, René Cumplido, Fernando Martin del Campo, Claudia Feregrino Uribe:
A Versatile Linear Insertion Sorter Based on a FIFO Scheme. ISVLSI 2008: 357-362 - [c22]Jose Juan Garcia-Hernandez, Claudia Feregrino Uribe, René Cumplido:
FPGA Implementation of a Modulated Complex Lapped Transform for Watermarking Systems. ReConFig 2008: 367-372 - [c21]Ignacio Algredo-Badillo
FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks. ReConFig 2008: 421-426 - [c20]Zobeida Jezabel Guzman-Zavaleta
A Reversible Data Hiding Algorithm for Radiological Medical Images and Its Hardware Implementation. ReConFig 2008: 444-449 - 2007
- [c19]Raúl Rodríguez-Colín, Claudia Feregrino Uribe, Gershom de J. Trinidad-Blas:
Data Hiding Scheme for Medical Images. CONIELECOMP 2007: 32 - [c18]José Alberto Méndez-Polanco, Ana Cristina Palacios-García, Raúl Rodríguez-Colín, Claudia Feregrino Uribe:
Digital Watermarking Based on Image Centroid Resistant to Rotation and Scaling. CONIELECOMP 2007: 33 - [c17]Dulce R. Herrera-Moro, Raúl Rodríguez-Colín, Claudia Feregrino Uribe:
Adaptive Steganography based on textures. CONIELECOMP 2007: 34 - [c16]Alejandro Rojas, René Cumplido, Jesús Ariel Carrasco-Ochoa, Claudia Feregrino Uribe, José Francisco Martínez Trinidad
FPGA-Based Architecture for Computing Testors. IDEAL 2007: 188-197 - 2006
- [j1]Virgilio Zúñiga Grajeda, Claudia Feregrino Uribe, René Cumplido-Parra:
Parallel Hardware/Software Architecture for the BWT and LZ77 Lossless Data Compression Algorithms. Computación y Sistemas 10(2) (2006) - [c15]René Cumplido, Jesús Ariel Carrasco-Ochoa, Claudia Feregrino:
On the Design and Implementation of a High Performance Configurable Architecture for Testor Identification. CIARP 2006: 665-673 - [c14]Ignacio Algredo-Badillo
Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture. ICCSA (3) 2006: 456-465 - [c13]Miguel Morales-Sandoval
GF(2m) Arithmetic Modules for Elliptic Curve Cryptography. ReConFig 2006: 176-183 - [c12]Roshan Mathew Duraisamy, Zoran A. Salcic, Miguel Morales-Sandoval, Claudia Feregrino Uribe:
A Fast Elliptic Curve Based Key Agreement Protocol-on-Chip (PoC) for Securing Networked Embedded Systems. RTCSA 2006: 154-161 - [e1]Claudia Feregrino Uribe, Janeth Cruz Enríquez, J. Alejandro Díaz Méndez:
JIISIC'06 - V Jornadas Iberoamericanas de Ingeniería de Software e Ingeniería del Conocimiento, Memoria Técnica, Proceedings, Puebla, Pue. México, 1 al 3 de Febrero de 2006. 2006, ISBN 970-94770-0-5 [contents] - 2005
- [c11]Miguel Morales-Sandoval
A Hardware Architecture for Elliptic Curve Cryptography and Lossless Data Compression. CONIELECOMP 2005: 113-118 - [c10]Carlos Avendaño Pérez, Claudia Feregrino Uribe, Gonzalo Navarro:
Approximate Searching on Compressed Text. CONIELECOMP 2005: 258-261 - [c9]José Francisco Martínez Trinidad, René Cumplido-Parra, Claudia Feregrino Uribe:
An FPGA-based parallel sorting architecture for the Burrows Wheeler transform. ReConFig 2005 - 2004
- [c8]Miguel Morales-Sandoval
On the Hardware Design of an Elliptic Curve Cryptosystem. ENC 2004: 64-70 - 2003
- [c7]Claudia Feregrino Uribe:
High Performance PPMC Compression Algorithm. ENC 2003: 135- - [c6]Marco Aurelio Nuño-Maganda
Three video applications using an FPGA based pyramid implementation: Tracking, Mosaics and Stabilization. FPT 2003: 336-339 - 2001
- [b1]Claudia Feregrino Uribe:
A novel approach for the hardware implementation of a PPMC statistical data compressor. Loughborough University, UK, 2001 - [c5]Claudia Feregrino Uribe, S. R. Jones:
Optimisation of PPMC Model for Hardware Implementation. DSD 2001: 120-126 - [c4]José Luis Núñez, Claudia Feregrino, Simon R. Jones, Stephen Bateman:
X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor. FPL 2001: 613-617 - [c3]Riad Stefo, José Luis Núñez, Claudia Feregrino, Sudipta Mahapatra, Simon R. Jones:
FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding. FPL 2001: 643-647
1990 – 1999
- 1999
- [c2]José Luis Núñez, Claudia Feregrino, Simon R. Jones, Stephen Bateman:
The X-MatchLITE FPGA-Based Data Compressor. EUROMICRO 1999: 1126-1132 - [c1]José Luis Núñez, Claudia Feregrino, Stephen Bateman, Simon R. Jones:
The X-MatchLITE FPGA-Based Data Compressor. FPGA 1999: 255
Coauthor Index
Lázaro Bustio-Martínez
aka: Lázaro Bustio
aka: Lázaro Bustio
René Cumplido
aka: René Cumplido-Parra
aka: René Cumplido-Parra
[j57] [j55] [j50] [j49] [j46] [j44] [j41] [j37] [j36] [j35] [j33] [c50] [e4] [j31] [e3] [c47] [c46] [c45] [e2] [j27] [j26] [j25] [c41] [j24] [j23] [j22] [j21] [c38] [j20] [j19] [j18] [c37] [c36] [c35] [j17] [j16] [j15] [c34] [j12] [c33] [c32] [j11] [j10] [j9] [j8] [c31] [c30] [i1] [j7] [j6] [j5] [c29] [c28] [j4] [j2] [c26] [c24] [c23] [c22] [c21] [c20] [c16] [j1] [c15] [c14] [c9]
José Juan García-Hernández
aka: Jose Juan Garcia-Hernandez
aka: Jose Juan Garcia-Hernandez
Kelsey A. Ramírez-Gutiérrez
aka: Kelsey Aleiandra Ramírez-Gutiérrez
aka: Kelsey Aleiandra Ramírez-Gutiérrez
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the dblp computer science bibliography is funded and supported by: