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40th VTS 2022: San Diego, CA, USA
- 40th IEEE VLSI Test Symposium, VTS 2022, San Diego, CA, USA, April 25-27, 2022. IEEE 2021, ISBN 978-1-6654-1060-1
- Sahil Shah, Jennifer Blain Christen:
Special Session: Calibrating mismatch in an ISFET with a Floating-Gate. 1-4 - Bora Bilgic, Sule Ozev:
Performance Degradation Monitoring for Analog Circuits Using Lightweight Built-in Components. 1-7 - Daniel W. Gulick
, Yuna Jung, Seunghyun Lee, Sule Ozev, Jennifer Blain Christen
Exploring Model-based Failure Prediction of Passive Bio-electro-mechanical Implants. 1-7 - Vineet Pancholi:
Special Session: Test Impact of Multi-Die Packages. 1-2 - Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento, Smbat Tonoyan, Ashwin Chintaluri, Animesh Khare, Milind Sonawane, Ashish Kumar, Anitha Kalva, Alex Hsu, Jayesh Pandey:
NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links. 1-7 - Sreejit Chakravarty:
Special Session: A Call to Standardize Chip-let Interconnect Testing. 1-3 - Rasheed Kibria, Nusrat Farzana, Farimah Farahmandi, Mark M. Tehranipoor:
FSMx: Finite State Machine Extraction from Flattened Netlist With Application to Security. 1-7 - Muslum Emir Avci, Sule Ozev, Y. B. Chethan Kumar:
Fast RF Mismatch Calibration Using Built-in Detectors. 1-7 - Marcel Merten, Sebastian Huhn, Rolf Drechsler
A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection. 1-7 - Debarshi Chatterjee, Parth Lathigara, Siddhanth Dhodhi, Chad Parsons:
FIFO Topology Aware Stalling for Accelerating Coverage Convergence of Stalling Regressions. 1-7 - Bala Tarun Nelapatla, Rahul Singhal, Michael Daub, Zoran Stanojevics:
Innovative Practices Track: High Speed Test Fabric. 1 - Deepika Neethirajan, V. A. Niranjan
Machine Learning-Based Overkill Reduction through Inter-Test Correlation. 1-7 - Sankaran M. Menon, Rolf Kühnis:
Special Session: Closed Chassis Platform Debug of Compute Systems using the Functional Ubiquitous USB Type-C Receptacle. 1-4 - Arani Sinha:
Innovative Practices Track: Silent Data Errors. 1 - Christopher Münch, Jongsin Yun, Martin Keim, Mehdi B. Tahoori:
MBIST-based Trim-Search Test Time Reduction for STT-MRAM. 1-7 - Ho-Chieh Hsu, Cheng-Che Lu, Shih-Wei Wang, Kelly Jones, Kai-Chiang Wu, Mango C.-T. Chao:
Rule Generation for Classifying SLT Failed Parts. 1-7 - Soyed Tuhin Ahmed
Fault-tolerant Neuromorphic Computing with Functional ATPG for Post-manufacturing Re-calibration. 1-7 - Minqiang Peng, Youfa Wu, Jialiang Li, Alex Yu, Grigor Tshagharyan, Costas Argyrides, Vilas Sridharan, Gurgen Harutyunyan, Yervant Zorian, Nilanjan Mukherjee:
Innovative Practices Track: What's Next for Automotive: Where and How to Improve Field Test and Enhance SoC Safety. 1 - Chris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa:
Innovative Practices Track: Innovative Analog Circuit Testing Technologies. 1 - Renjian Pan, Xin Li, Krishnendu Chakrabarty:
Semi-Supervised Root-Cause Analysis with Co-Training for Integrated Systems. 1-7 - Mehdi Sadi
Special Session: On the Reliability of Conventional and Quantum Neural Network Hardware. 1-12 - Aibin Yan, Kuikui Qian, Jie Cui, Ningning Cui, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard:
A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications. 1-6 - Jennifer Hasler:
Special Session: Testing and Characterization for Large-Scale Programmable Analog Systems. 1-5 - Fei Su, Stephen Crosher, Andrea Matteucci, Yuwen Zou:
Innovation Practices Track: Silicon Telemetry for Dependability. 1 - Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy:
Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. 1-7 - Antonios Pavlidis, Eric Faehn, Marie-Minerve Louërat, Haralampos-G. Stratigopoulos:
Run-Time Hardware Trojan Detection in Analog and Mixed-Signal ICs. 1-8 - Arjun Chaudhuri, Jonti Talukdar
Special Session: Fault Criticality Assessment in AI Accelerators. 1-4 - Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti
The Least-Squares Approach to Systematic Error Identification and Calibration in Semiconductor Multisite Testing. 1-7 - Riccardo Cantoro, Francesco Garau, Riccardo Masante, Sandro Sartoni
Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries. 1-7 - Juan-David Guerrero-Balaguera
A New Method to Generate Software Test Libraries for In-Field GPU Testing Resorting to High-Level Languages. 1-7 - Shamik Kundu, Suvadeep Banerjee
Special Session: Effective In-field Testing of Deep Neural Network Hardware Accelerators. 1-4 - Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski:
Fast Test Generation for Structurally Similar Circuits. 1-7 - Mahta Mayahinia, Atousa Jafari, Mehdi B. Tahoori:
Voltage Tuning for Reliable Computation in Emerging Resistive Memories. 1-7 - Amit Pandey, Brendan Tully, Abhijeet Samudra, Ajay Nagarandal, Karthikeyan Natarajan, Rahul Singhal:
Novel Technique for Manufacturing & In-system Testing of Large Scale SoC using Functional Protocol Based High-Speed I/O. 1-7 - Cheng Liu, Zhen Gao, Siting Liu
Special Session: Fault-Tolerant Deep Learning: A Hierarchical Perspective. 1-12 - Sandeep Kumar Goel, Sandeep Pendharkar, Chunsheng Liu:
Innovative Practices Track: Test of 3D ICs & Chiplets. 1 - Arani Sinha:
Innovative Practices Track: Next Generation Test Standards. 1 - Mingye Li, Fangzhou Wang, Sandeep Gupta:
Methods for testing path delay and static faults in RSFQ circuits. 1-7 - Nitin Chaudhary:
Innovative Practices Track: Novel Methods for Validation and Test. 1 - Seyed Nima Mozaffari, Bonita Bhaskaran, Shantanu Sarangi, Suhas M. Satheesh, Kuo Lin Fu, Nithin Valentine, P. Manikandan, Mahmut Yilmaz:
On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST). 1-6 - Shail Dave
Special Session: Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML Systems. 1-14 - Ziqi Zhou, Ujjwal Guin, Peng Li, Vishwani D. Agrawal:
Fault Modeling and Test Generation for Technology-Specific Defects of Skyrmion Logic Circuits. 1-7 - Rubin A. Parekhji:
Innovative Practices Track: New Methods for System Level Test of Image Projection and Radar VLSI Systems. 1 - Gang Qu, Benjamin Tan, Kuheli Pratihar, Debdeep Mukhopadhyay, Ramesh Karri
Innovation Practices Track: Security in Test and Test for Security. 1 - Mona Ganji, Marampally Saikiran
All Digital Low-Overhead SAR ADC Built-In Self-Test for Fault Detection and Diagnosis. 1-7 - Baishakhi Rani Biswas, Sandeep Gupta:
Memristor-Specific Failures: New Verification Methods and Emerging Test Problems. 1-7 - Abram Detofsky:
Special Session: A Testability Practitioner's Guide to Chiplets. 1-2 - Anteneh Gebregiorgis, Lizhou Wu, Christopher Münch, Siddharth Rao
Special Session: STT-MRAMs: Technology, Design and Test. 1-10
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