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Kaushik Narayanun
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2020 – today
- 2024
- [c7]Kunal Jain Mangilal, Mahmut Yilmaz, Vishal Agarwal, Shantanu Sarangi, Kaushik Narayanun:
A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS. ITC 2024: 400-406 - 2023
- [j1]Mahmut Yilmaz
, Pavan Kumar Datla Jagannadha
NVIDIA MATHS: Mechanism to Access Test-Data Over High-Speed Links. IEEE Des. Test 40(4): 25-33 (2023) - 2022
- [c6]Bonita Bhaskaran, Sanmitra Banerjee, Kaushik Narayanun, Shao-Chun Hung, Seyed Nima Mozaffari Mojaveri, Mengyun Liu, Gang Chen, Tung-Che Liang:
Observation Point Insertion Using Deep Learning. ICCAD 2022: 161:1-161:8 - [c5]Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento, Smbat Tonoyan, Ashwin Chintaluri, Animesh Khare, Milind Sonawane, Ashish Kumar, Anitha Kalva, Alex Hsu, Jayesh Pandey:
NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links. VTS 2022: 1-7
2010 – 2019
- 2019
- [c4]Seyed Nima Mozaffari, Bonita Bhaskaran, Kaushik Narayanun, Ayub Abdollahian, Vinod Pagalone, Shantanu Sarangi, Jonathon E. Colburn
An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test. ITC 2019: 1-10 - 2017
- [c3]Zipeng Li, Jonathon E. Colburn
Test-cost optimization in a scan-compression architecture using support-vector regression. VTS 2017: 1-6 - 2016
- [c2]Bonita Bhaskaran, Amit Sanghani, Kaushik Narayanun, Ayub Abdollahian, Amit Laknaur:
Test method and scheme for low-power validation in modern SOC integrated circuits. VTS 2016: 1-6 - [c1]Ran Wang, Bonita Bhaskaran, Karthikeyan Natarajan, Ayub Abdollahian, Kaushik Narayanun, Krishnendu Chakrabarty
A programmable method for low-power scan shift in SoC integrated circuits. VTS 2016: 1-6
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