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ITC 2021: Anaheim, CA, USA
- IEEE International Test Conference, ITC 2021, Anaheim, CA, USA, October 10-15, 2021. IEEE 2021, ISBN 978-1-6654-1695-5
- J. Lefevre, Philippe Debaud, Patrick Girard
, Arnaud Virazel
A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors. 1-9 - Dun-An Yang, Yu-Teng Chang, Ting-Shuo Hsu, Jing-Jia Liou, Harry H. Chen:
ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph. 10-19 - Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich:
Testability-Enhancing Resynthesis of Reconfigurable Scan Networks. 20-29 - Xin Huang, Min Qin, Ruosheng Xu, Cheng Chen, Shangling Jui, Zhihao Ding, Pengyun Li, Yu Huang:
Adaptive NN-based Root Cause Analysis in Volume Diagnosis for Yield Improvement. 30-36 - Florian Klemme
Machine Learning for Circuit Aging Estimation under Workload Dependency. 37-46 - Yen-Ting Kuo, Wei-Chen Lin, Chun Chen, Chao-Ho Hsieh, James Chien-Mo Li, Eric Jia-Wei Fang, Sung S.-Y. Hsueh:
Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning. 47-52 - Chenwei Liu, Jie Ou:
Smart Sampling for Efficient System Level Test: A Robust Machine Learning Approach. 53-62 - Yongliang Chen, Xiaole Cui, Wenqiang Ye, Xiaoxin Cui:
The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack. 63-72 - Arjun Chaudhuri, Ching-Yuan Chen, Jonti Talukdar
Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin∗. 73-82 - Ching-Yuan Chen, Krishnendu Chakrabarty:
On-line Functional Testing of Memristor-mapped Deep Neural Networks using Backdoored Checksums. 83-92 - Yi He
Efficient Functional In-Field Self-Test for Deep Learning Accelerators. 93-102 - Michihiro Shintani
Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process. 103-112 - Hanbin Hu
Semi-supervised Wafer Map Pattern Recognition using Domain-Specific Data Augmentation and Contrastive Learning. 113-122 - Paul R. Genssler, Hussam Amrouch:
Brain-Inspired Computing for Wafer Map Defect Pattern Classification. 123-132 - Foisal Ahmed
Study on High-Accuracy and Low-Cost Recycled FPGA Detection. 133-142 - Lizhou Wu, Siddharth Rao
Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions. 143-152 - Mengyun Liu, Krishnendu Chakrabarty:
Adaptive Methods for Machine Learning-Based Testing of Integrated Circuits and Boards. 153-162 - Shahram Rasoolzadeh
Impeccable Circuits III. 163-169 - Jonti Talukdar
A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks*. 170-179 - M. Sazadur Rahman
LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment. 180-189 - Yueling Jenny Zeng, Li-C. Wang, Chuanhe Jay Shan:
MINiature Interactive Offset Networks (MINIONs) for Wafer Map Classification. 190-199 - Chenwei Liu, Qiaoyue Tang:
Triplet Convolutional Networks for Classifying Mixed-Type WBM Patterns with Noisy Labels. 200-207 - Leon Li-Yang Chen, Katherine Shu-Min Li, Xu-Hao Jiang, Sying-Jyan Wang
Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling. 208-212 - Danielle Duvalsaint, R. D. Shawn Blanton:
Characterizing Corruptibility of Logic Locks using ATPG. 213-222 - Arash Vafaei, Nick Hooten, Mark M. Tehranipoor, Farimah Farahmandi:
SymbA: Symbolic Execution at C-level for Hardware Trojan Activation. 223-232 - Yang Shang, Makoto Shinohara, Eiji Kato, Masaichi Hashimoto, Joanna Kiljan:
Open-short Normalization Method for a Quick Defect Identification in Branched Traces with High-resolution Time-domain Reflectometry. 233-242 - Tommaso Melis, Emmanuel Simeu, Luc Saury, Etienne Auvray:
Relevant Signals and Devices for Failure Analysis of Analog and Mixed-signal Circuits. 243-250 - Mu-Ting Wu, Cheng-Sian Kuo, James Chien-Mo Li, Chris Nigh
Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization. 251-259 - Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer:
On Reduction of Deterministic Test Pattern Sets. 260-267 - Mahta Mayahinia, Christopher Münch, Mehdi B. Tahoori:
Analyzing and Mitigating Sensing Failures in Spintronic-based Computing in Memory. 268-277 - Jorge Corso, Saidapet Ramesh, Kumar Abishek, Ley Teng Tan, Chik Hooi Lew:
Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on automotive designs. 278-283 - Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jianglin Wei, Takayuki Nakatani, Yujie Zhao, Shogo Katayama, Shuhei Yamamoto, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi:
Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies. 284-288 - Stephen Traynor, Chen He
Adaptive High Voltage Stress Methodology to Enable Automotive Quality on FinFET Technologies. 289-293 - Seongkwan Lee, Minho Kang, Cheolmin Park, HyungSun Ryu, Jaemoo Choi, Byunghyun Yim:
3.5Gsps MIPI C-PHY Receiver Circuit for Automatic Test Equipment. 294-298 - Tobias Kilian, Heiko Ahrens, Daniel Tille, Martin Huch, Ulf Schlichtmann:
A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators. 299-303 - Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti
Systematic Hardware Error Identification and Calibration for Massive Multisite Testing. 304-308 - Peter Yi-Yu Liao, Katherine Shu-Min Li, Leon Li-Yang Chen, Sying-Jyan Wang
WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques. 309-313 - Chris Nigh
AAA: Automated, On-ATE AI Debug of Scan Chain Failures. 314-318 - Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas
Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits. 319-323 - Min Li, Zhengyuan Shi, Zezhong Wang, Weiwei Zhang, Yu Huang, Qiang Xu
Testability-Aware Low Power Controller Design with Evolutionary Learning. 324-328 - Felipe Augusto da Silva
An automated formal-based approach for reducing undetected faults in ISO 26262 hardware compliant designs. 329-333 - Sergej Meschkov
Is your secure test infrastructure secure enough? : Attacks based on delay test patterns using transient behavior analysis. 334-338 - Bambang Suparjo, Jugantor Chetia, Ankit R. Shah:
Seamless Physical Implementation of ASIC Hierarchical Integrated Scan Architecture. 339-343 - Michele Portolan, Vincent Reynaud, Paolo Maistri, Régis Leveugle, Giorgio Di Natale:
Security EDA Extension through P1687.1 and 1687 Callbacks. 344-353 - Erik Larsson, Prathamesh Murali, Ziling Zhang:
Accessing general IEEE Std. 1687 networks via functional ports. 354-363 - Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Akemi Hatta, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jianglin Wei, Yujie Zhao, Minh Tri Tran, Kazumi Hatayama, Haruo Kobayashi:
Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer. 364-373 - Franziska Mayer, Christian Schott, Enrico Billich, Saeid Yazdani, Ulrich Heinkel, Georg Daler, Bernhard Ruf, Ricardo Pannuzzo, Wolfgang Dickenscheid:
Automatic Verification of Mixed-Signal ATE Test Programs using Device Variation. 374-379 - Muslum Emir Avci, Sule Ozev:
Background Receiver IQ Imbalance Correction for in-Field and Post-Production Testing and Calibration. 380-388 - Chandramouli N. Amarnath, Md Imran Momtaz, Abhijit Chatterjee:
Hierarchical Failure Modeling and Machine Learning Assisted Correction of Electro-Mechanical Subsystem Failures in Autonomous Vehicles. 389-398 - V. Prasanth, Rubin A. Parekhji, Bharadwaj Amrutur:
Exploiting Application Tolerance for Functional Safety. 399-408 - Christian Bartsch, Stephan Wilhelm, Daniel Kästner, Dominik Stoffel, Wolfgang Kunz:
Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation. 409-418
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