default search action
Xiaole Cui
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
- [j27]Yongliang Chen
, Xiaole Cui
The area-efficient gate level information flow tracking schemes of digital circuit with multi-level security lattice. Microelectron. J. 144: 106088 (2024) - [j26]Mingqi Yin
A reconfigurable FPGA-based spiking neural network accelerator. Microelectron. J. 152: 106377 (2024) - [j25]Feng Wei
An 11T SRAM Cell for the Dual-Direction In-Array Logic/CAM Operations. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2329-2333 (2024) - [j24]Feng Wei
An in-Array Build-In Self-Test Scheme for Embedded SRAM Array. IEEE Trans. Circuits Syst. II Express Briefs 71(8): 3935-3939 (2024) - [j23]Xiaole Cui
The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells. ACM Trans. Design Autom. Electr. Syst. 29(1): 10:1-10:21 (2024) - [j22]Chen Wei
Dy-MFNS-CAC: An Encoding Mechanism to Suppress the Crosstalk and Repair the Hard Faults in Rectangular TSV Arrays. IEEE Trans. Reliab. 73(1): 622-636 (2024) - [c44]Hanqing Liu, Xiaole Cui, Sunrui Zhang, Mingqi Yin, Yuanyuan Jiang, Xiaoxin Cui:
A Convolutional Spiking Neural Network Accelerator with the Sparsity-Aware Memory and Compressed Weights. ASAP 2024: 163-171 - [c43]Shengjie Zhou, Yongliang Chen, Xiaole Cui, Yun Liu:
Modeling Attack Tests and Security Enhancement of the Sub-Threshold Voltage Divider Array PUF. DATE 2024: 1-6 - [c42]Yuanyuan Jiang, Li Lun, Jiawei Wang, Mingqi Yin, Hanqing Liu, Zhenhui Dai, Xiaole Cui, Xiaoxin Cui:
SPAT: FPGA-based Sparsity-Optimized Spiking Neural Network Training Accelerator with Temporal Parallel Dataflow. ISCAS 2024: 1-5 - [c41]Yang Zeng, Xiaole Cui:
A High Performance PODEM Algorithm with the Improved Backtrace Process. ITC-Asia 2024: 1-6 - 2023
- [j21]Sunrui Zhang
An Area-Efficient In-Memory Implementation Method of Arbitrary Boolean Function Based on SRAM Array. IEEE Trans. Computers 72(12): 3416-3430 (2023) - [j20]Xiaole Cui
Mosaic-3C1S: A Low Overhead Crosstalk Suppression Scheme for Rectangular TSV Array. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(5): 1380-1392 (2023) - [j19]Yongliang Chen
An Evaluation Method of the Anti-Modeling-Attack Capability of PUFs. IEEE Trans. Inf. Forensics Secur. 18: 1773-1788 (2023) - [c40]Yongliang Chen, Xiaole Cui, Pengyuan Yang, Gang Qu:
An Anti-Removal-Attack Hardware Watermarking Method Based on Polymorphic Gates. ICCAD 2023: 1-9 - 2022
- [j18]Chen Wei
A Global Self-Repair Method for TSV Arrays With Adaptive FNS-CAC Codec. IEEE Des. Test 39(5): 26-33 (2022) - [c39]Huixian Huang, Xiaole Cui, Shuming Zhang, Ge Li, Xiaoxin Cui:
An obfuscation scheme of scan chain to protect the cryptographic chips. ATS 2022: 19-24 - [c38]Fan Liu, Sunrui Zhang
The Design Method of Logic Circuits based on the Voltage-Input Enhanced Scouting Logic Gates. FPL 2022: 136-142 - [c37]Yun Liu, Yongliang Chen, Xiaole Cui:
A Modeling Attack on the Sub-threshold Current Array PUF. HOST 2022: 169-172 - [c36]Xiaole Cui, Fan Liu, Sunrui Zhang
An Area-Efficient and Robust Memristive LUT Based on the Enhanced Scouting Logic Cells. ISCAS 2022: 2571-2575 - 2021
- [j17]Xiaole Cui
The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates. IEEE Access 9: 54466-54477 (2021) - [j16]Qingyun Zou, Xiaoxin Cui, Zhenhui Dai, Yisong Kuang, Yi Zhong, Chenglong Zou
28nm asynchronous area-saving AES processor with high Common and Machine learning side-channel attack resistance. IEICE Electron. Express 18(20): 20210309 (2021) - [j15]Yi Zhong, Jianhua Feng, Xiaoxin Cui, Xiaole Cui:
Machine Learning Aided Key-Guessing Attack Paradigm Against Logic Block Encryption. J. Comput. Sci. Technol. 36(5): 1102-1117 (2021) - [c35]Yuqian Sun, Xiaole Cui, Yongliang Chen, Xiaoxin Cui:
The logic obfuscation of LFSR with the crosstalk based polymorphic gate. AsianHOST 2021: 1-6 - [c34]Xiangyu Zhang, Feng Wei
Design and Implementation of Full Adder in One-Transistor-One-Resistor RRAM Array. ASICON 2021: 1-4 - [c33]Yongliang Chen, Xiaole Cui, Wenqiang Ye, Xiaoxin Cui:
The Modeling Attack and Security Enhancement of the XbarPUF with Both Column Swapping and XORing. ACM Great Lakes Symposium on VLSI 2021: 83-88 - [c32]Kanglin Xiao, Xiaoxin Cui, Kefei Liu, Xiaole Cui, Xin'an Wang:
An SNN-Based and Neuromorphic-Hardware-Implementable Noise Filter with Self-adaptive Time Window for Event-Based Vision Sensor. IJCNN 2021: 1-8 - [c31]Yongliang Chen, Xiaole Cui, Wenqiang Ye, Xiaoxin Cui:
The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack. ITC 2021: 63-72 - [c30]Xiaole Cui, Yongliang Chen, Wenqiang Ye, Xiaoxin Cui:
The ANN Based Modeling Attack and Security Enhancement of the Double-layer PUF. ITC-Asia 2021: 1-6 - 2020
- [j14]Xiaole Cui, Xiao Ma, Feng Wei
A synthesis method for logic circuits in RRAM arrays. Sci. China Inf. Sci. 63(10): 1-3 (2020) - [j13]Xiaole Cui, Xiao Ma, Qiujun Lin, Xiang Li, Hang Zhou, Xiaoxin Cui
Design of High-Speed Logic Circuits with Four-Step RRAM-Based Logic Gates. Circuits Syst. Signal Process. 39(6): 2822-2840 (2020) - [j12]Xiaole Cui, Qiujun Lin, Xiaoxin Cui, Feng Wei
The synthesis method of logic circuits based on the iMemComp gates. Integr. 74: 115-126 (2020) - [c29]Li Qu, Xiaole Cui, Xiaoxin Cui:
A Testability Enhancement Method for the Memristor Ratioed Logic Circuits. ATS 2020: 1-6 - [c28]Xianfeng Li, Gengchao Li, Xiaole Cui:
ReTriple: Reduction of Redundant Rendering on Android Devices for Performance and Energy Optimizations. DAC 2020: 1-6
2010 – 2019
- 2019
- [j11]Runze Han, Peng Huang, Yudi Zhao, Xiaole Cui, Xiaoyan Liu, Jinfeng Kang:
Efficient evaluation model including interconnect resistance effect for large scale RRAM crossbar array matrix computing. Sci. China Inf. Sci. 62(2): 22401:1-22401:11 (2019) - [c27]Jinfeng Kang, Peng Huang, Runze Han, Yachen Xiang, Xiaole Cui, Xiaoyan Liu:
Flash-based Computing in-Memory Scheme for IOT. ASICON 2019: 1-4 - 2018
- [j10]Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Dunshan Yu, Xiaole Cui:
Design of Low-Power High-Performance FinFET Standard Cells. Circuits Syst. Signal Process. 37(5): 1789-1806 (2018) - [j9]Tian Wang
Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1922-1929 (2018) - [c26]Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui:
Polymorphic gate based IC watermarking techniques. ASP-DAC 2018: 90-96 - [c25]Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui:
A Novel Polymorphic Gate Based Circuit Fingerprinting Technique. ACM Great Lakes Symposium on VLSI 2018: 141-146 - 2017
- [j8]Xiaole Cui, Qiang Zhang, Xiaoxin Cui, Xin'an Wang, Jinfeng Kang, Xiaoyan Liu:
Testing of 1TnR RRAM array with sneak path technique. Sci. China Inf. Sci. 60(2): 29402 (2017) - [j7]Nan Liao, Xiaoxin Cui, Kai Liao, Tian Wang, Dunshan Yu, Xiaole Cui:
Improving DFA attacks on AES with unknown and random faults. Sci. China Inf. Sci. 60(4): 42401 (2017) - [j6]Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Dunshan Yu, Xiaole Cui:
High-Performance Noninvasive Side-Channel Attack Resistant ECC Coprocessor for GF(2m ). IEEE Trans. Ind. Electron. 64(1): 727-738 (2017) - [j5]Xiaole Cui, Xiaoxin Cui
An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias. IEEE Trans. Very Large Scale Integr. Syst. 25(5): 1601-1610 (2017) - [c24]Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui, Gang Qu:
A practical cold boot attack on RSA private keys. AsianHOST 2017: 55-60 - [c23]Yewen Ni, Xiaoxin Cui, Tian Wang, Yuanning Fan, Qiankun Han, Kefei Liu, Xiaole Cui:
Improving DFA on AES using all-fault ciphertexts. ASICON 2017: 283-286 - [c22]Liwen Zhu, Xiaole Cui, Xiang Li, Xiaoxin Cui:
A signal noise separation method for the instant mixing linear and nonlinear circuits with MISEP algorithm. ASICON 2017: 742-745 - [c21]Kuimin Zhang, Xiaole Cui, Xiaoxin Cui:
A design of high performance full adder with memristors. ASICON 2017: 746-479 - [c20]Yewen Ni, Xiaoxin Cui, Yuanning Fan, Qiankun Han, Kefei Liu, Xiaole Cui:
Design of router for spiking neural networks. ASICON 2017: 965-968 - [c19]Xiaole Cui, Yichi Luo, Qiujun Lin, Xiaoxin Cui:
A Heuristic Algorithm for Automatic Generation of March Tests. ATS 2017: 266-271 - [c18]Xiaole Cui, Chunliang Liu, Guangyi Shi, Yufeng Jin:
A new calibration method for MEMS accelerometers with genetic algorithm. RCAR 2017: 240-245 - 2016
- [j4]Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Dunshan Yu, Xiaole Cui:
Ultralow-power high-speed flip-flop based on multimode FinFETs. Sci. China Inf. Sci. 59(4): 042404:1-042404:11 (2016) - [j3]Xiaole Cui, Zuolin Cheng, Chung-Len Lee, Xinnan Lin, Yiqun Wei, Xiaogang Chen, Zhitang Song:
A snake addressing scheme for phase change memory testing. Sci. China Inf. Sci. 59(10): 102401 (2016) - [j2]Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Xiaole Cui, Dunshan Yu:
Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology. IEICE Trans. Electron. 99-C(8): 974-983 (2016) - 2015
- [j1]Zuolin Cheng, Xiaole Cui, Xiaoxin Cui, Chung Len Lee:
Self-heating burn-in pattern generation based on the genetic algorithm incorporated with a BACK-like procedure. IET Comput. Digit. Tech. 9(6): 300-310 (2015) - [c17]Bingqiang Jing, Xiaole Cui, Yalin Ran, Yufeng Jin:
Post-bond test for TSVs using voltage division. ASICON 2015: 1-4 - [c16]Nan Liao, Xiaoxin Cui, Tian Wang, Kai Liao, Yewen Ni, Dunshan Yu, Xiaole Cui:
A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications. ASICON 2015: 1-4 - [c15]Lifei Liu, Xiaole Cui, Yalin Ran, Xiaoxin Cui:
A countermeasure for power analysis to scalar multiplication of ECC hardware. ASICON 2015: 1-4 - [c14]Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Yewen Ni, Dunshan Yu, Xiaole Cui:
Employing the mixed FBB/RBB in the design of FinFET logic gates. ASICON 2015: 1-4 - [c13]Hupo Wei, Xiaole Cui, Qiang Zhang, Yufeng Jin:
An enhanced decoder for multiple-bit error correcting BCH codes. ASICON 2015: 1-4 - [c12]Shijie Zhang, Xiaole Cui, Qiang Zhang, Yufeng Jin:
A TSV repair method for clustered faults. ASICON 2015: 1-4 - [c11]Xufeng Li, Ronggang Wang, Xiaole Cui, Wenmin Wang:
Context-adaptive fast motion estimation of HEVC. ISCAS 2015: 2784-2787 - 2013
- [c10]Si Chen, Xiaole Cui, Chung Len Lee:
A novel test scheme for NAND flash memory based on built-in oscillator ring. ASICON 2013: 1-4 - [c9]Xiaoxin Cui, Rui Li, Wei Wei, Juan Gu, Xiaole Cui:
AHardware implementation of DES with combined countermeasure against DPA. ASICON 2013: 1-4 - [c8]Yibo He, Xiaole Cui, Chung Len Lee, Xiaoxin Cui, Yufeng Jin:
New DfT architectures for 3D-SICs with a wireless test port. ASICON 2013: 1-4 - [c7]Weijia Ma, Xiaole Cui, Chung Len Lee:
Enhanced error correction against multiple-bit-upset based on BCH code for SRAM. ASICON 2013: 1-4 - [c6]Zhengyu Qian, Xiaole Cui, Bo Wang, Xiangrong Zhang, Chung Len Lee:
A folded current-reused CMOS power amplifier for low-voltage 3.0-5.0 GHz UWB applications. ASICON 2013: 1-4 - [c5]Xuan Yang, Xiaole Cui, Chao Wang, Chung Len Lee:
A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique. ASICON 2013: 1-4 - [c4]Xiangrong Zhang, Xiaole Cui, Bo Wang, Chung Len Lee:
A UWB mixer with a balanced wide band active balun using crossing centertaped inductor. ISCAS 2013: 1588-1591 - 2012
- [c3]Jin Zha, Xiaole Cui, Chung Len Lee:
Modeling and testing of interference faults in the nano NAND Flash memory. DATE 2012: 527-531
2000 – 2009
- 2008
- [c2]Guangyi Shi, Yuexian Zou, Yufeng Jin, Xiaole Cui, Wen Jung Li
Towards HMM based human motion recognition using MEMS inertial sensors. ROBIO 2008: 1762-1766 - 2006
- [c1]Xiaoxin Cui, Dunshan Yu, Shimin Sheng, Xiaole Cui:
Design and Implementation of a 2-level FSK Digital Modems Using CORDIC Algorithm. APCCAS 2006: 1753-1756
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-30 21:34 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: