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ISVLSI 2014: Tampa, FL, USA
- IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014, Tampa, FL, USA, July 9-11, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-3763-9
Session 01: Variation-Aware and Low-Power Design
- Vikram B. Suresh, Wayne P. Burleson:
Variation Aware Design of Post-Silicon Tunable Clock Buffer. 1-6 - Liang Men, Brent Hollosi, Jia Di:
Framework of an Adaptive Delay-Insensitive Asynchronous Platform for Energy Efficiency. 7-12 - Orhun Aras Uzun, Selçuk Köse
:
Regulator-Gating Methodology with Distributed Switched Capacitor Voltage Converters. 13-18
Session 02: Hardware Security and Testing (SS)
- Yier Jin
Design-for-Security vs. Design-for-Testability: A Case Study on DFT Chain in Cryptographic Circuits. 19-24 - Marten van Dijk
PUF Interfaces and their Security. 25-28 - Xiaolin Xu, Vikram B. Suresh, Raghavan Kumar, Wayne P. Burleson:
Post-Silicon Validation and Calibration of Hardware Security Primitives. 29-34
Session 03: Advanced Circuit for Computing
- Fabio Campi, Roberto Airoldi, Jari Nurmi
Design of a Flexible, Energy Efficient (Auto)Correlator Block for Timing Synchronization. 35-40 - Dominik Auras, Rainer Leupers, Gerd Ascheid:
A Novel Class of Linear MIMO Detectors with Boosted Communications Performance: Algorithm and VLSI Architecture. 41-47 - Son Bui, James E. Stine
Experiments with High Speed Parallel Cubing Units. 48-53
Session 04: New Directions in Hardware Trust (SS)
- Garrett Steven Rose
A Chaos-Based Arithmetic Logic Unit and Implications for Obfuscation. 54-58 - Nektarios Georgios Tsoutsos, Michail Maniatakos
Trust No One: Thwarting "heartbleed" Attacks Using Privacy-Preserving Computation. 59-64
Session 05: Memristive and 3-Dimensional Designs
- Chenchen Liu, Hai Li
A Weighted Sensing Scheme for ReRAM-Based Cross-Point Memory Array. 65-70 - Debashri Roy, Prasun Ghosal, Saraju P. Mohanty:
FuzzRoute: A Method for Thermally Efficient Congestion Free Global Routing in 3D ICs. 71-76 - Cory E. Merkel, Dhireesha Kudithipudi:
Neuromemristive Extreme Learning Machines for Pattern Classification. 77-82
Session 06: Poster Session
- Swagata Bhattacharya, Somsubhra Talapatra:
A New Walsh Hadamard Transform Architecture Using Current Mode Circuit. 83-88 - Suresh Alapati, Patri SrihariRao, K. S. R. Krishna Prasad, Saurabh Dixit:
A Transient-Enhanced Capacitorless LDO Regulator with improved Error Amplifier. 89-93 - Raqibul Hasan, Tarek M. Taha:
Memristor Crossbar Based Programmable Interconnects. 94-99 - Hélène Leroux, Karen Godary-Dejean, Guillaume Coppey, David Andreu
Automatic Handling of Conflicts in Synchronous Interpreted Time Petri Nets Implementation. 100-105 - Anirban Sengupta, Vipul Kumar Mishra
Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance Tradeoff. 106-111 - Hongxia Zhou, Chiu-Wing Sham
Slicing Floorplans with Handling Symmetry and General Placement Constraints. 112-117 - Ivan Ratkovic, Oscar Palomar
Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders. 118-123 - Somrita Ghosh, Prasun Ghosal, Nabanita Das, Saraju P. Mohanty, Oghenekarho Okobiah:
Data Correlation Aware Serial Encoding for Low Switching Power On-Chip Communication. 124-129 - Matthew J. Cotter, Yan Fang, Steven P. Levitan, Donald M. Chiarulli, Vijaykrishnan Narayanan:
Computational Architectures Based on Coupled Oscillators. 130-135 - Avik Bose
A Low Latency Scalable 3D NoC Using BFT Topology with Table Based Uniform Routing. 136-141 - Debasis Dhal, Piyali Datta, Arpan Chakrabarty, Goutam Saha
An Algorithm for Parallel Assay Operations in a Restricted Sized Chip in Digital Microfluidics. 142-147 - Atul Kumar Nishad
Analytical Model for Inverter Design Using Floating Gate Graphene Field Effect Transistors. 148-153 - Neela Gopi, Jeffrey Draper:
Modeling the Impact of TSVs on Average Wire Length in 3DICs Using a Tier-Level Hierarchical Approach. 154-159 - Lei Xu
Removing the Root of Trust: Secure Oblivious Key Establishment for FPGAs. 160-165 - Sanjeev Das
Reconfigurable Dynamic Trusted Platform Module for Control Flow Checking. 166-171 - Nikita Nikitin, Magnus Jahre
Patterned Heterogeneous CMPs: The Case for Regularity-Driven System-Level Synthesis. 172-177 - Mahanama Wickramasinghe
Energy-Aware Thread Scheduling for Embedded Multi-threaded Processors: Architectural Level Design and Implementation. 178-183 - Hemanta Kumar Mondal
An Efficient Hardware Implementation of DVFS in Multi-core System with Wireless Network-on-Chip. 184-189 - Jia Zhao, Shiting (Justin) Lu, Wayne P. Burleson, Russell Tessier:
A Broadcast-Enabled Sensing System for Embedded Multi-core Processors. 190-195 - Surajit Kumar Roy, Payel Ghosh, Hafizur Rahaman
Session Based Core Test Scheduling for 3D SOCs. 196-201 - Rupali Mitra
On Designing Robust Path-Delay Fault Testable Combinational Circuits Based on Functional Properties. 202-207 - Kele Shen, Dong Xiang, Zhou Jiang:
Cost-Effective Test Optimized Scheme of TSV-Based 3D SoCs for Pre-Bond Test. 208-213 - Lingbo Kou, William H. Robinson
Impact of Process Variations on Reliability and Performance of 32-nm 6T SRAM at Near Threshold Voltage. 214-219 - Vahid Janfaza, Payman Behnam, Bahjat Forouzandeh, Bijan Alizadeh:
A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data Compression. 220-225 - Anu Asokan, Aida Todri-Sanial
A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise. 226-231
Session 07: Ph.D. Forum
- Mike Borowczak
Enabling Side Channel Secure FSMs in the Presence of Low Power Requirements. 232-235 - Tosiron Adegbija, Ann Gordon-Ross:
Dynamic Phase-Based Optimization of Embedded Systems. 236-239 - Xiaokun Yang, Jean H. Andrian:
A Low-Cost and High-Performance Embedded System Architecture and an Evaluation Methodology. 240-243 - Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos:
Exploring Kriging for Fast and Accurate Design Optimization of Nanoscale Analog Circuits. 244-247 - Sophiane Senni, Lionel Torres, Gilles Sassatelli, Anastasiia Butko, Bruno Mussard:
Exploration of Magnetic RAM Based Memory Hierarchy for Multicore Architecture. 248-251 - Matthew Morrison:
Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits for Security Applications. 252-255
Session 08: Biomedical and Sensor Circuits
- Hourieh Attarzadeh, Trond Ytterdal:
A Low-Noise Variable-Gain Amplifier for in-Probe 3D Imaging Applications Based on CMUT Transducers. 256-260 - Hai Chi, Tom Chen:
A CMOS Temperature Sensor with -0.34°C to 0.27°C Inaccuracy from -30°C to 80°C. 261-266 - Yanmei Wang, Pak Kwong Chan, King Ho Li:
A Compact CMOS Ring Oscillator with Temperature and Supply Compensation for Sensor Applications. 267-272
Session 09: Variability and Aging of Integrated Circuits (SS)
- Masahiro Fujita:
Variation-Aware Analysis and Test Pattern Generation Based on Functional Faults. 273-277 - Ketul Sutaria, Athul Ramkumar, Rongjun Zhu, Yu Cao
Where is the Achilles Heel under Circuit Aging. 278-279 - Farshad Firouzi, Fangming Ye, Krishnendu Chakrabarty
Chip Health Monitoring Using Machine Learning. 280-283 - Andrew B. Kahng:
Toward Holistic Modeling, Margining and Tolerance of IC Variability. 284-289
Session 10: Memory and Oscillator Circuits
- Alireza Shafaei, Yanzhi Wang, Xue Lin, Massoud Pedram:
FinCACTI: Architectural Analysis and Modeling of Caches with Deeply-Scaled FinFET Devices. 290-295 - Kaisheng Ma
Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed. 296-301 - Xueqing Li, Wei-Yu Tsai, Huichu Liu, Suman Datta, Vijaykrishnan Narayanan:
A Low-Voltage Low-Power LC Oscillator Using the Diode-Connected SymFET. 302-307
Session 11: Test Generation and Fault Diagnosis
- Irith Pomeranz:
FDPIC: Generation of Functional Test Sequences Based on Fault-Dependent Primary Input Cubes. 308-313 - Irith Pomeranz:
OBO: An Output-by-Output Scoring Algorithm for Fault Diagnosis. 314-319 - Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults. 320-325
Session 12: CAD for Verification and Debug
- Prateek Thakyal, Prabhat Mishra
Layout-Aware Selection of Trace Signals for Post-Silicon Debug. 326-331 - Manish Kumar Jaiswal, Ray C. C. Cheung
Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division. 332-337 - Farimah Farahmandi, Bijan Alizadeh, Zainalabedin Navabi:
Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits. 338-343
Session 13: CAD for Digital Systems
- Vinitha Arakkonam Palaniveloo, Jude Angelo Ambrose, Arcot Sowmya:
Improving GA-Based NoC Mapping Algorithms Using a Formal Model. 344-349 - Adriel Mota Ziesemer, Ricardo Augusto da Luz Reis
Simultaneous Two-Dimensional Cell Layout Compaction Using MILP with ASTRAN. 350-355 - Maciej J. Ciesielski, Walter Brown, Duo Liu, André Rossi
Function Extraction from Arithmetic Bit-Level Circuits. 356-361
Session 14: Reaching Beyond Device Scaling: Post-CMOS Perspectives
- Lin Liu, Yuchen Zhou, Shiyan Hu:
Buffering Single-Walled Carbon Nanotubes Bundle Interconnects for Timing Optimization. 362-367 - K. M. Mohsin, Ashok Srivastava, Ashwani K. Sharma, Clay Mayberry:
Characterization of MWCNT VLSI Interconnect with Self-Heating Induced Scatterings. 368-373 - Darryl Shima, Ganesh Balakrishnan:
High Mobility n and p Channels on Gallium Arsenide and Silicon Substrates Using Interfacial Misfit Dislocation Arrays. 374-379
Session 15: Sub-Power Circuit and 3D Architecture
- Jiaoyan Chen, Christian Spagnol, Satish Grandhi, Emanuel M. Popovici, Sorin Cotofana
Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits. 380-385 - Yassine Fkih, Pascal Vivet
2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures. 386-391 - Jun Zhou, Huawei Li, Yuntan Fang, Tiancheng Wang, Yuanqing Cheng, Xiaowei Li:
HARS: A High-Performance Reliable Routing Scheme for 3D NoCs. 392-397
Session 16: CAD for Emerging Memory Technologies (SS)
- Kaushik Roy, Mrigank Sharad, Deliang Fan, Karthik Yogendra:
Computing with Spin-Transfer-Torque Devices: Prospects and Perspectives. 398-402 - Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Giovanni De Micheli
Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis. 403-405 - Hai Li
Memristor Modeling - Static, Statistical, and Stochastic Methodologies. 406-411
Session 17: FinFET and Optical Technology Based Design
- Pratik Dutta
Mach-Zehnder Interferometer Based All Optical Reversible Carry-Lookahead Adder. 412-417 - Gracieli Posser, Jozeanne Belomo, Cristina Meinhardt
Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices. 418-423 - Qing Xie, Xue Lin, Yanzhi Wang, Mohammad Javad Dousti, Alireza Shafaei, Majid Ghasemi-Gol, Massoud Pedram:
5nm FinFET Standard Cell Library Optimization and Circuit Synthesis in Near-and Super-Threshold Voltage Regimes. 424-429
Session 18: Dynamic Power Management
- Yue Wang, Nagarajan Ranganathan:
A Feedback, Runtime Technique for Scaling the Frequency in GPU Architectures. 430-435 - Arunachalam Annamalai, Rance Rodrigues, Israel Koren, Sandip Kundu:
Reducing Energy per Instruction via Dynamic Resource Allocation and Voltage and Frequency Adaptation in Asymmetric Multicores. 436-441 - Santhosh Kumar Rethinagiri, Oscar Palomar
System-Level Power and Energy Estimation Methodology for Open Multimedia Applications Platforms. 442-449
Session 19: Security and Error Tolerance in System Architecture
- Ke Jiang, Lejla Batina, Petru Eles, Zebo Peng:
Robustness Analysis of Real-Time Scheduling Against Differential Power Analysis Attacks. 450-455 - André Luiz Pereira de França, Ricardo Pereira Jasinski, Volnei Antonio Pedroni, Altair Olivo Santin
Moving Network Protection from Software to Hardware: An Energy Efficiency Analysis. 456-461
Session 20: VLSI for Big Data (SS)
- Kevin M. Irick, Nandhini Chandramoorthy:
Achieving High-Performance Video Analytics with Lightweight Cores and a Sea of Hardware Accelerators. 462-467 - Karim Kanoun, Martino Ruggiero, David Atienza, Mihaela van der Schaar
Low Power and Scalable Many-Core Architecture for Big-Data Stream Computing. 468-473 - Apostolos Dollas:
Big Data Processing with FPGA Supercomputers: Opportunities and Challenges. 474-479
Session 21: Network-on-a-Chip (NoC) Based Systems
- Zhe Wang, Weichen Liu
A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCs. 480-485 - Bharath Phanibhushana, Sandip Kundu:
Network-on-Chip Design for Heterogeneous Multiprocessor System-on-Chip. 486-491 - Changlin Chen, Sorin Dan Cotofana
Towards an Effective Utilization of Partially Defected Interconnections in 2D Mesh NoCs. 492-497
Session 22: CAD for Power Integrity
- Can Sitik, Leo Filippini
High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design. 498-503 - Arunkumar Vijayakumar, Sandip Kundu:
Glitch Power Reduction via Clock Skew Scheduling. 504-509 - Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu:
On Maximizing Decoupling Capacitance of Clock-Gated Logic for Robust Power Delivery. 510-515
Session 23: Secure and Trustworthy Embedded Systems (SS)
- David H. K. Hoe, Jeyavijayan Rajendran, Ramesh Karri
Towards Secure Analog Designs: A Secure Sense Amplifier Using Memristors. 516-521 - Mahadevan Gomathisankaran, Akhilesh Tyagi:
Glitch Resistant Private Circuits Design Using HORNS. 522-527 - Jungmin Park, Akhilesh Tyagi:
Towards Making Private Circuits Practical: DPA Resistant Private Circuits. 528-533
Session 24: Advanced Methods for Futuristic Systems
- Sparsh Mittal
LastingNVCache: A Technique for Improving the Lifetime of Non-volatile Caches. 534-540 - Xinying Wang, Phillip H. Jones, Joseph Zambreno:
A Reconfigurable Architecture for QR Decomposition Using a Hybrid Approach. 541-546 - Juan Yi, Weichen Liu
An Improved Thermal Model for Static Optimization of Application Mapping and Scheduling in Multiprocessor System-on-Chip. 547-552
Session 25: High-Reliability Design
- Saif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, Lirida A. B. Naviner
Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. 553-558 - Raul Chipana, Fernanda Gusmão de Lima Kastensmidt
SET Susceptibility Analysis of Clock Tree and Clock Mesh Topologies. 559-564 - Zheng Wang, Goutam Paul, Anupam Chattopadhyay:
Processor Design with Asymmetric Reliability. 565-570
Session 26: Reaching Beyond Device Scaling: CMOS Perspectives
- Umamaheswara Rao Tida, Varun Mittapalli, Cheng Zhuo, Yiyu Shi:
"Green" On-chip Inductors in Three-Dimensional Integrated Circuits. 571-576 - Ying Zhang, Sui Chen, Lu Peng, Shaoming Chen:
Mitigating NBTI Degradation on FinFET GPUs through Exploiting Device Heterogeneity. 577-582 - Indira Priyadarshini Dugganapally, Steve E. Watkins, Benjamin Cooper:
Multi-level, Memory-Based Logic Using CMOS Technology. 583-588
Session 27: Soft Error Analysis and Mitigation
- Bradley T. Kiddie, William H. Robinson
Alternative Standard Cell Placement Strategies for Single-Event Multiple-Transient Mitigation. 589-594 - Lawrence T. Clark, Sandeep Shambhulingaiah:
Methodical Design Approaches to Radiation Effects Analysis and Mitigation in Flip-Flop Circuits. 595-600 - Faiq Khalid Lodhi
Low Power Soft Error Tolerant Macro Synchronous Micro Asynchronous (MSMA) Pipeline. 601-606
Session 28: CAD Recent Developments on Partitioning
- Wenzan Cai, Evangeline F. Y. Young:
A Fast Hypergraph Bipartitioning Algorithm. 607-612 - Sabyasachee Banerjee
A Graph-Based 3D IC Partitioning Technique. 613-618 - Tariq B. Ahmad, Maciej J. Ciesielski:
Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning. 619-624
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