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ED&TC 1996: Paris, France
- 1996 European Design and Test Conference, ED&TC 1996, Paris, France, March 11-14, 1996. IEEE Computer Society 1996, ISBN 0-8186-7423-7
Session 1A: Formal Verification
- Rolf Drechsler
, Bernd Becker
K*BMDs: A New Data Structure for Verification. 2-8 - C. A. J. van Eijk, Jochen A. G. Jess:
Exploiting Functional Dependencies in Finite State Machine Verification. 9-14 - Jürgen Frößl, Thomas Kropf, Joachim Gerlach:
An Efficient Algorithm for Real-Time Symbolic Model Checking. 15-21
Session 1B: System Design for Digital Broadband Telecom: Trends and System Design Challenges
- Jacques Wenin, Geert van Wauwe, Mark Genoe, Danny Sallaerts:
The Use of Microelectronics for Future Telecom and Multimedia Systems. 22 - Bill Lin:
System design tools for broadband telecom network applications. 23-26 - J. L. Conesa:
Design challenges of high speed ATM communication ASICs. 27-29
Session 1C: BIST Pattern Generation
- Birgit Reeb, Hans-Joachim Wunderlich:
Deterministic Pattern Generation for Weighted Random Pattern Testing. 30-36 - Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar:
Deterministic Test Pattern Reproduction by a Counter. 37-41 - Janusz Rajski, Jerzy Tyszer:
Multiplicative Window Generators of Pseudo-random Test Vectors. 42-49
Session 2A: New Domains in High-Level Synthesis
- Wah Chan, Alex Orailoglu:
High-level synthesis of gracefully degradable ASICs. 50-54 - Seong Yong Ohm, Douglas M. Blough, Fadi J. Kurdahi
High-Level Synthesis of Recoverable Microarchitectures. 55-62 - Preeti Ranjan Panda, Nikil D. Dutt
Reducing Address Bus Transitions for Low Power Memory Mapping. 63-71
Session 2C: Fault Analysis and Test Quality
- Francesco Corsi, Cristoforo Marzocca, S. Martino:
Assessing the Quality Level of Digital CMOS IC's under the Hypothesis of Non-Uniform Distribution of Fault Probabilities. 72-78 - P. Cavallera, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits. 79-87 - Mahesh A. Iyer
Surprises in Sequential Redundancy Identification. 88-95
Session 3A: Code Generation
- Hiroyuki Tomiyama, Hiroto Yasuura
Optimal Code Placement of Embedded Software for Instruction Caches. 96-101 - Johan Van Praet, Dirk Lanneer, Gert Goossens, Werner Geurts, Hugo De Man:
A Graph Based Processor Model for Retargetable Code Generation. 102-107 - Rajesh K. Gupta:
Operation Serializability for Embedded Systems. 108-115
Session 3B: IDDQ: You Heard the Hype, But What's Really Coming?
- Keith Baker:
IDDQ: you heard the hype, but what's really coming? 116-119
Session 3C: Test and BIST Beyond Chips
- Chauchin Su, Shyh-Jye Jou, Yuan-Tzu Ting:
Decentralized BIST for 1149.1 and 1149.5 Based Interconnects. 120-125 - Joan Oliver
Test Structures on MCM Active Substrate: Is it worthwhile? 126-130 - Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian:
Relay Propagation Scheme for Testing of MCMs on Large Area Substrates. 131-137
Session 4A: Transformations and Estimations
- Martin Janssen, Francky Catthoor, Hugo De Man:
A Specification Invariant Technique for Regularity Improvement between Flow-Graph Clusters. 138-143 - Wei Zhao, Christos A. Papachristou
An evolution programming approach on multiple behaviors for the design of application specific programmable processors. 144-150 - Min Xu, Fadi J. Kurdahi
Area and Timing Estimation for Lookup Table Based FPGAs. 151-159
Session 4B: FPGA Placement and Routing
- Yasuhiro Takashima, Atsushi Takahashi
Detailed-Routability of FPGAs with Extremal Switch-Block Structures. 160-164 - Anmol Mathur
Timing Driven Placement Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs. 165-169 - Srilata Raman, C. L. Liu, Larry G. Jones:
A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs. 170-175
Session 4C: Self-Test Methodologies
- Ernst G. Bernard, Sven Simon, Josef A. Nossek:
Built-in self test architectures for multistage interconnection networks. 176-180 - Yervant Zorian, Hakim Bederr:
Designing Self-Testable Multi-Chip Modules. 181-185 - Michael Nicolaidis, Salvador Manich
Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and Implementations. 186-194
Session 4D: Emerging Design Techniques
- Hicham Boutamine, Alain Guyot, Bachar El-Hassan, Marc Renaudin:
Asynchronous SRT Dividers: The Real Cost. 195-199 - Eckart Voskamp, Wolfgang Rosenstiel:
Error Detection in Fault Secure Controllers using State Encoding. 200-204 - S. Caufape, Joan Figueras:
Power Optimization of Delay Constrained CMOS Bus Drivers. 205-213
Session 5A: Low Power Design
- Olivier Coudert:
Gate Sizing: A General Purpose Optimization Approach. 214-218 - Enric Musoll, Jordi Cortadella:
Optimizing CMOS Circuits for Low Power Using Transistor Reordering. 219-223 - S. Turgis, Nadine Azémard, Daniel Auvergne:
Design and selection of buffers for minimum power-delay product. 224-229
Session 5B: Performance-Driven Routing
- Y. P. Chen, D. F. Wong
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion. 230-236 - Hidenori Sato, Akira Onozawa, Hiroaki Matsuda:
A Balanced-Mesh Clock Routing Technique Using Circuit Partitioning. 237-243 - Iksoo Pyo, Jaewon Oh, Massoud Pedram:
Constructing Minimal Spanning/Steiner Trees with Bounded Path Length. 244-253
Session 5D: Test Generation for Mixed-Signal Circuits
- Salvador Mir, Bernard Courtois, Marcelo Lubaszewski, Vladimir Kolarik
Automatic Test Generation for Maximal Diagnosis of Linear Analogue Circuits. 254-258 - Firas Mohamed, Meryem Marzouki, Mohamed Hedi Touati:
FLAMES: A Fuzzy Logic ATMS and Model-based Expert System for Analog Diagnosis. 259-263 - José Machado da Silva
Evaluation of iDD/vOUT Cross-Correlation for Mixed Current/Voltage Testing of Analogue and Mixed-Signal Circuits. 264-269
Session 6A: Heterogeneous System Modelling and Design
- Jie Gong, Daniel D. Gajski, Smita Bakshi:
Model Refinement for Hardware-Software Codesign. 270-274 - Armin Bender:
Design of an Optimal Loosely Coupled Heterogeneous Multiprocessor System. 275-281 - Youngsoo Shin, Kiyoung Choi:
Thread-based software synthesis for embedded system design. 282-287
Session 6B: Analysis in Digital Circuit Design
- Ahmed Riadh Baba-Ali, A. Farah:
An Efficient Algorithm for Signal Flow Determination in Digital CMOS VLSI. 288-293 - Jindrich Zejda, Eduard Cerny, S. Shenoy, Nicholas C. Rumin:
Bounding Switching Activity in CMOS Circuits Using Constraint Resolution. 294-301 - Ulrich Heinkel, Wolfram Glauert:
An Approach for a Dynamic Generation/Validation System for the Functional Simulation Considering Timing Constraints. 302-309
Session 6D: High Speed Signal Processing
- César Sanz
VLSI Architecture for Motion Estimation using the Block-Matching Algorithm. 310-314 - Eric Lüthi, Emmanuel Casseau:
High Rate Soft Output Viterbi Decoder. 315-319 - Mitsuo Ikeda, Tsuneo Okubo, Tetsuya Abe, Yoshinori Ito, Yutaka Tashiro, Ryota Kasai:
A Hardware/Software Concurrent Design for a Real-Time SP@ML MPEG2 Video-Encoder Chip Set. 320-327
Session 7A: Sequential Logic Synthesis
- Thomas R. Shiple, Gérard Berry, Hervé J. Touati:
Constructive Analysis of Cyclic Circuits. 328-333 - Chih-Chang Lin, Malgorzata Marek-Sadowska, Kuang-Chien Chen, Mike Tien-Chien Lee:
Sequential Permissible Functions and their Application to Circuit Optimization. 334-339 - Enric Pastor, Oriol Roig, Jordi Cortadella, Alex Kondratyev:
Structural Methods for the Synthesis of Speed-Independent Circuits. 340-349
Session 7B: From High Level Verification to (Low Level) Extraction
- Reinaldo A. Bergamaschi, Salil Raje:
Observable Time Windows: Verifying the Results of High-Level Synthesis. 350-356 - Frank Scherber, Erich Barke, Wolfgang Meier:
PALACE: A Parallel and Hierarchical Layout Analyzer and Circuit Extractor. 357-361 - P. J. H. Elias, N. P. van der Meijs:
Including Higher-Order Moments of RC Interconnections in Layout-to-Circuit Extraction. 362-367
Session 7C: Sequential Test Generation
- Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Alternating Strategies for Sequential Circuit ATPG. 368-374 - Fulvio Corno
Advanced Techniques for GA-based sequential ATPGs. 375-379 - Irith Pomeranz, Sudhakar M. Reddy:
On Test Generation for Interconnected Finite-State Machines - The Output Sequence Justification Problem. 380-387
Session 7D: Module Generators
- Markus Wolf, Ulrich Kleine, Bedrich J. Hosticka:
A Novel Analog Module Generator Environment. 388-392 - Avaneendra Gupta, Siang-Chun The, John P. Hayes:
XPRESS: A Cell Layout Generator with Integrated Transistor Folding. 393-401
Session 8A: Logic Synthesis
- Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Perturb and Simplify: Optimizing Combinational Circuits with External Don't Cares. 402-406 - Anne-Marie Trullemans, Q. Zhang:
Rapid Gate Matching with Don't Cares. 407-411 - Christian Legl, Bernd Wurth, Klaus Eckl:
An Implicit Algorithm for Support Minimization during Functional Decomposition. 412-419
Session 8B: Memory Testing
- Ad J. van de Goor, Aad Offerman, Ivo Schanstra:
Towards a Uniform Notation for Memory Tests. 420-427 - Manoj Sachdev:
Test and Testability Techniques for Open Defects in RAM Address Decoders. 428-434 - V. G. Mikitjuk, V. N. Yarmolik, Ad J. van de Goor:
RAM Testing Algorithm for Detection Linked Coupling Faults. 435-441
Session 8C: Design Environments and CAD Tools for Microsystems Design
- Jean-Michel Karam, Bernard Courtois, M. Bauge:
High level CAD melds microsystems with foundries. 442-447 - Takashi Kiriyama, Naomasa Nakajima, Shinobu Yoshimura, Stuart C. Burgess
A conceptual design environment for micromechanisms. 448-453 - Stephanus Büttgenbach, O. Than:
SUZANA: A 3D CAD Tool for Anisotropically Etched Silicon Microstructures. 454-459
Session 9A: Partitioning in System Design
- Emile H. L. Aarts, Gerben Essink, Erwin A. de Kock:
Recursive Bipartitioning of Signal Flow Graphs for Programmable Video Signal Processors. 460-466 - Ireneusz Karkowski, Ralph H. J. M. Otten:
An Automatic Hardware-Software Partitioner Based on the Possibilistic Programming. 467-472 - Ralf Niemann, Peter Marwedel:
Hardware/Software Partitioning using Integer Programming. 473-480
Session 9B: Synthesis and Testability
- Víctor Fernández
Partial Scan High-Level Synthesis. 481-485 - Angela Krstic, Kwang-Ting Cheng
Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault Testability. 486-490 - Bernd Becker
A Fast Optimal Robust Path Delay Fault Testable Adder. 491-499
Session 9C: Novelties in Integrated System Design
- Minoru Inamori, Jiro Naganuma, Haruo Wakabayashi, Makoto Endo:
A Memory-based Architecture for MPEG2 System Protocol LSIs. 500-507 - Vivek Garg, Steve Lacy, David E. Schimmel, Darrell Stogner, Craig D. Ulmer, D. Scott Wills, Sudhakar Yalamanchili:
Incorporating Multi-Chip Module Packaging Constraints into System Design. 508-513 - Kazuhiro Shirakawa, Kazushige Higuchi, Toshiaki Miyazaki, Kazuhiro Hayashi, Kazuhisa Yamada:
FORM: A Frame-Oriented Representation Method for Digital Telecommunication System Design. 514-521
Session 10A: Modelling and Design Strategies for Microsystems Design
- Wolfgang Vermeiren, Bernd Straube, Andreas Holubek:
Defect-Oriented Experiments in Fault Modelling and Fault Simulation of Microsystem Components. 522-527 - Jean-Michel Karam, Bernard Courtois, András Poppe
Applied design and analysis of microsystems. 528-532 - Wolfgang Süß, K. Lindemann, Horst Eggert, Martina Gorges-Schleuter, Wilfried Jakob, W. Hoffmann, Reinhard Rapp:
Step by Step from Specification to Realization of an Electrochemical Microsystem. 533-541
Session 10C: New Technologies for Mixed-Signal Test
- Bert Atzema, Taco Zwemstra:
Exploit Analog IFA to Improve Specification Based Tests. 542-546 - Mark Zwolinski
Analogue Fault Modelling and Simulation for Supply Current Monitoring. 547-552 - R. A. Cobley:
Approaches to On-chip Testing of Mixed Signal Macros in ASICs. 553-559
Session 11A: Recent Advances in Simulation
- Arjan J. van Genderen, N. P. van der Meijs, T. Smedes:
Fast Computation of Substrate Resistances in Large Circuits. 560-565 - Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang:
ETS-A: A New Electrothermal Simulator for CMOS VLSI Circuits. 566-570 - H. Z. Yang, C. Z. Fan, H. Wang, R. S. Liu:
Simulated Annealing Algorithm with Multi-Molecule: An Approach to Analog Synthesis. 571-577
Session 11C: DFT Solutions and IDDQ
- Thomas W. Williams, Rohit Kapur, M. Ray Mercer, Robert H. Dennard, Wojciech Maly:
Iddq Testing for High Performance CMOS - The Next Ten Years. 578-583 - M. Rullán, Carles Ferrer, Joan Oliver
Analysis of ISSQ/IDDQ Testing Implementation and Circuit Partitioning in CMOS Cell-Based Design. 584-588 - Michele Favalli, Luca Benini, Giovanni De Micheli:
Design for Testability of Gated-Clock FSMs. 589-597
Poster Session
- Tom Conway, John Nelson:
VLSI Design of a High Speed Soft Decision Viterbi Detector. 598 - Mohamed Abid, Adel Changuel, Ahmed Amine Jerraya:
A Hardware/Software Codesign Case Study: Design of a Robot Arm Controller. 599 - Peter Marwedel, Steven Bashford, Rainer Dömer, Birger Landwehr, Ingolf Markhof:
A Technique for Avoiding Isomorphic Netlists in Architectural Synthesis. 600 - José M. Mendías, Román Hermida
Algebraic Support for Transformational Hardware Allocation. 601 - D. Michael Miller:
A spectral method for Boolean function matching. 602 - Kuo-Rueih Ricky Pan, Massoud Pedram:
FPGA synthesis for minimum area, delay and power. 603 - Vladimír Székely, András Poppe
An Efficient Method for the Self-Consistent Electro-Thermal Simulation and its Integration into a CAD Framework. 604 - Michel Allemand, Solange Coupet-Grimal, Line Jakubiec, Jean-Luc Paillet:
A System for Modelling and Proving Circuits. 605 - Ales Casar, Zmago Brezocnik, Tatjana Kapus:
Exploiting Partitioned Transition Relations for Efficient Symbolic Model Checking in CTL. 606 - Laurence Pierre:
Formal Specification of a Reactive System: An Exercise in VHDL, LOTOS and UNITY. 607 - Jean Bruce Guignet:
Generalized Recognition of Gates: A VLSI Abstraction Tool. 608 - A. Josep Velasco, Xavier Marin, Jordi Carrabina
A Combined Pairing and Chaining Algorithm for CMOS Layout Generation. 609 - Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
Self-Checking and Fault Tolerant Approaches Can Help BIST Fault Coverage: A Case Study. 610 - Alexander V. Drozd, Wael Hassonah, Michel Lobachov:
Hardware Check of Arithmetic Devices with Abridged Execution of Operations. 611 - José T. de Sousa, T. Shen, Peter Y. K. Cheung:
Realistic Fault Extraction for Boards. 612 - Matthias Gulbins, Bernd Straube:
Applying Behavioural Level Test Generation to High-Level Design Validation. 613 - Claudio Truzzi, Eric Beyne
Design of Test Modules for the Analysis of MCM Interconnects. 614 - Chryssa Dislis, Ian P. Jalowiecki:
Economics Modelling and Optimisation of MCM Test Strategies. 615 - Mohamed Hedi Touati, Firas Mohamed, Meryem Marzouki:
System Fault Diagnosis based on a Fuzzy Qualitative Approach. 616 - A. Murthi, F. Rocaries:
An Automated Design Environment for Micromechanical Sensors. 617 - Tor-Björn Johansson, Kay Hameyer, Ronnie Belmans:
Methods and Tools for the Design of Electrostatic Micromotors. 618 - Jordi Carrabina, L. Hébrard, Angel Merlos
Design Kit for Microsystems Design for an Enhanced CMOS Process. 619
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