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Mahesh A. Iyer
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2020 – today
- 2024
- [c27]Yuan Meng
, Michael Kinsner
PEARL: Enabling Portable, Productive, and High-Performance Deep Reinforcement Learning using Heterogeneous Platforms. CF 2024 - [c26]Rachel Selina Rajarathnam, Kate Thurmer, Vaughn Betz, Mahesh A. Iyer, David Z. Pan:
Better Together: Combining Analytical and Annealing Methods for FPGA Placement. FPL 2024: 43-52 - [c25]Samuel Wiggins, Yuan Meng, Mahesh A. Iyer, Viktor K. Prasanna:
A Heterogeneous Acceleration System for Attention-Based Multi-Agent Reinforcement Learning. FPL 2024: 236-242 - 2023
- [c24]Rachel Selina Rajarathnam
DREAMPlaceFPGA-PL: An Open-Source GPU-Accelerated Packer-Legalizer for Heterogeneous FPGAs. ISPD 2023: 175-184 - [i1]Yuan Meng, Michael Kinsner, Deshanand P. Singh, Mahesh A. Iyer, Viktor K. Prasanna:
A Software-Hardware Co-Optimized Toolkit for Deep Reinforcement Learning on Heterogeneous Platforms. CoRR abs/2311.09445 (2023) - 2022
- [c23]Rachel Selina Rajarathnam, Mohamed Baker Alawieh, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan:
DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit. ASP-DAC 2022: 300-306 - 2020
- [c22]Mohamed Baker Alawieh, Wuxi Li, Yibo Lin, Love Singhal, Mahesh A. Iyer
High-Definition Routing Congestion Prediction for Large-Scale FPGAs. ASP-DAC 2020: 26-31 - [c21]Mahesh A. Iyer:
Symbiosis in Action: Reconfigurable Architectures and EDA. FPGA 2020: 27-28 - [c20]Ilya K. Ganusov, Mahesh A. Iyer
Agilex™ Generation of Intel® FPGAs. Hot Chips Symposium 2020: 1-26
2010 – 2019
- 2019
- [c19]Shounak Dhar, Love Singhal, Mahesh A. Iyer
A shape-driven spreading algorithm using linear programming for global placement. ASP-DAC 2019: 563-568 - [c18]Shounak Dhar, Love Singhal, Mahesh A. Iyer
FPGA Accelerated FPGA Placement. FPL 2019: 404-410 - [c17]Shounak Dhar, Love Singhal, Mahesh A. Iyer
FPGA-Accelerated Spreading for Global Placement. HPEC 2019: 1-7 - 2017
- [c16]Love Singhal, Mahesh A. Iyer
LSC: A Large-Scale Consensus-Based Clustering Algorithm for High-Performance FPGAs. DAC 2017: 30:1-30:6 - [c15]Mahesh A. Iyer:
CAD Opportunities with Hyper-Pipelining. ISPD 2017: 149 - [c14]Shounak Dhar, Mahesh A. Iyer
An Effective Timing-Driven Detailed Placement Algorithm for FPGAs. ISPD 2017: 151-157 - 2016
- [c13]Shounak Dhar, Saurabh N. Adya, Love Singhal, Mahesh A. Iyer
Detailed placement for modern FPGAs using 2D dynamic programming. ICCAD 2016: 9
2000 – 2009
- 2009
- [c12]Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer
On improving optimization effectiveness in interconnect-driven physical synthesis. ISPD 2009: 51-58 - 2003
- [c11]Mahesh A. Iyer:
Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation. ITC 2003: 299-308 - [c10]Mahesh A. Iyer
A Robust and Scalable Technique for the Constraints Solving Problem in High-Level Verification. MTV 2003: 95- - 2000
- [j3]David E. Long, Mahesh A. Iyer
FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults. ACM Trans. Design Autom. Electr. Syst. 5(3): 631-657 (2000)
1990 – 1999
- 1999
- [c9]Leon Stok, Andrew J. Sullivan, Mahesh A. Iyer
Wavefront Technology Mapping. DATE 1999: 531- - [c8]Narendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking:
A Robust Solution to the Timing Convergence Problem in High-Performance Design. ICCD 1999: 250-257 - [c7]Mahesh A. Iyer:
High Time For High Level ATPG. ITC 1999: 1112 - 1996
- [j2]Mahesh A. Iyer
FIRE: a fault-independent combinational redundancy identification algorithm. IEEE Trans. Very Large Scale Integr. Syst. 4(2): 295-301 (1996) - [c6]Mahesh A. Iyer
Identifying Sequential Redundancies Without Search. DAC 1996: 457-462 - [c5]Mahesh A. Iyer
Surprises in Sequential Redundancy Identification. ED&TC 1996: 88-95 - 1995
- [j1]Srimat T. Chakradhar, Mahesh A. Iyer, Vishwani D. Agrawal:
Energy models for delay testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(6): 728-739 (1995) - [c4]David E. Long, Mahesh A. Iyer, Miron Abramovici:
Identifying sequentially untestable faults using illegal states. VTS 1995: 4-11 - 1994
- [c3]Mahesh A. Iyer, Miron Abramovici:
Sequentially Untestable Faults Identified Without Search ("Simple Implications Beat Exhaustive Search!"). ITC 1994: 259-266 - [c2]Mahesh A. Iyer, Miron Abramovici:
Low-Cost Redundancy Identification for Combinatorial Circuits. VLSI Design 1994: 315-318 - 1992
- [c1]Miron Abramovici, Mahesh A. Iyer
One-Pass Redundancy Identification and Removal. ITC 1992: 807-815
Coauthor Index
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