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G. Edward Suh
Gookwon Edward Suh
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- affiliation: Cornell University, Ithaca, NY, USA
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2020 – today
- 2024
- [j12]Pengzhi Huang, Thang Hoang, Yueying Li, Elaine Shi, G. Edward Suh:
Efficient Privacy-Preserving Machine Learning with Lightweight Trusted Hardware. Proc. Priv. Enhancing Technol. 2024(4): 327-348 (2024) - [j11]Benjamin Wu
, Aaron B. Wagner
Strong Asymptotic Composition Theorems for Mutual Information Measures. IEEE Trans. Inf. Theory 70(5): 3049-3058 (2024) - [c96]Maximilian Lam
GPU-based Private Information Retrieval for On-Device Machine Learning Inference. ASPLOS (1) 2024: 197-214 - [c95]Juntaek Lim
LazyDP: Co-Designing Algorithm-Software for Scalable Training of Differentially Private Recommendation Models. ASPLOS (2) 2024: 616-630 - [c94]Hanshen Xiao, G. Edward Suh, Srinivas Devadas:
Formal Privacy Proof of Data Encoding: The Possibility and Impossibility of Learnable Encryption. CCS 2024: 1834-1848 - [c93]Yueying Li, Nikita Lazarev, David Koufaty, Tenny Yin, Andy Anderson, Zhiru Zhang, G. Edward Suh, Kostis Kaffes, Christina Delimitrou:
LibPreemptible: Enabling Fast, Adaptive, and Hardware-Assisted User-Space Scheduling. HPCA 2024: 922-936 - [c92]Kiwan Maeng, G. Edward Suh:
Accelerating ReLU for MPC-Based Private Inference with a Communication-Efficient Sign Estimation. MLSys 2024 - [c91]Trishita Tiwari, Suchin Gururangan, Chuan Guo, Weizhe Hua, Sanjay Kariyappa, Udit Gupta, Wenjie Xiong, Kiwan Maeng, Hsien-Hsin S. Lee, G. Edward Suh:
Information Flow Control in Machine Learning through Modular Model Architecture. USENIX Security Symposium 2024 - [i27]Juntaek Lim, Youngeun Kwon, Ranggi Hwang, Kiwan Maeng, G. Edward Suh, Minsoo Rhu:
LazyDP: Co-Designing Algorithm-Software for Scalable Training of Differentially Private Recommendation Models. CoRR abs/2404.08847 (2024) - 2023
- [c90]Drew Zagieboylo
SpecVerilog: Adapting Information Flow Control for Secure Speculation. CCS 2023: 2068-2082 - [c89]Mulong Luo, Wenjie Xiong
AutoCAT: Reinforcement Learning for Automated Exploration of Cache-Timing Attacks. HPCA 2023: 317-332 - [c88]Jiaxun Cui, Xiaomeng Yang, Mulong Luo, Geunbae Lee, Peter Stone, Hsien-Hsin S. Lee, Benjamin Lee, G. Edward Suh, Wenjie Xiong
MACTA: A Multi-agent Reinforcement Learning Approach for Cache Timing Attacks and Detection. ICLR 2023 - [c87]Yueying Li, Daochen Zha, Tianjun Zhang, G. Edward Suh, Christina Delimitrou, Francis Y. Yan:
Mitigating Metastable Failures in Distributed Systems with Offline Reinforcement Learning. Tiny Papers @ ICLR 2023 - [c86]Sanjay Kariyappa, Chuan Guo, Kiwan Maeng, Wenjie Xiong
Cocktail Party Attack: Breaking Aggregation-Based Privacy in Federated Learning Using Independent Component Analysis. ICML 2023: 15884-15899 - [c85]Kiwan Maeng, Chuan Guo, Sanjay Kariyappa, G. Edward Suh:
Bounding the Invertibility of Privacy-preserving Instance Encoding using Fisher Information. NeurIPS 2023 - [i26]Maximilian Lam, Jeff Johnson, Wenjie Xiong, Kiwan Maeng, Udit Gupta, Yang Li, Liangzhen Lai, Ilias Leontiadis, Minsoo Rhu, Hsien-Hsin S. Lee, Vijay Janapa Reddi, Gu-Yeon Wei, David Brooks, G. Edward Suh:
GPU-based Private Information Retrieval for On-Device Machine Learning Inference. CoRR abs/2301.10904 (2023) - [i25]Kiwan Maeng, Chuan Guo, Sanjay Kariyappa, G. Edward Suh:
Bounding the Invertibility of Privacy-preserving Instance Encoding using Fisher Information. CoRR abs/2305.04146 (2023) - [i24]Trishita Tiwari, Suchin Gururangan, Chuan Guo, Weizhe Hua, Sanjay Kariyappa, Udit Gupta, Wenjie Xiong, Kiwan Maeng, Hsien-Hsin S. Lee, G. Edward Suh:
Information Flow Control in Machine Learning through Modular Model Architecture. CoRR abs/2306.03235 (2023) - [i23]Yueying Li, Nikita Lazarev, David Koufaty, Yijun Yin, Andy Anderson, Zhiru Zhang, G. Edward Suh, Kostis Kaffes, Christina Delimitrou:
Towards Fast, Adaptive, and Hardware-Assisted User-Space Scheduling. CoRR abs/2308.02896 (2023) - [i22]Kiwan Maeng, G. Edward Suh:
Approximating ReLU on a Reduced Ring for Efficient MPC-based Private Inference. CoRR abs/2309.04875 (2023) - 2022
- [j10]Weizhe Hua
Reverse-Engineering CNN Models Using Side-Channel Attacks. IEEE Des. Test 39(4): 15-22 (2022) - [c84]Mulong Luo, G. Edward Suh:
Accelerating Path Planning for Autonomous Driving with Hardware-Assisted Memorization. ASAP 2022: 126-130 - [c83]Weizhe Hua, Muhammad Umar
GuardNN: secure accelerator architecture for privacy-preserving deep learning. DAC 2022: 349-354 - [c82]Wenjie Xiong
SecNDP: Secure Near-Data Processing with Untrusted Memory. HPCA 2022: 244-258 - [c81]Muhammad Umar
SoftVN: efficient memory protection via software-provided version numbers. ISCA 2022: 160-172 - [c80]Weizhe Hua, Muhammad Umar
MGX: near-zero overhead memory protection for data-intensive accelerators. ISCA 2022: 726-741 - [c79]Yongqin Wang
Characterization of MPC-based Private Inference for Transformer-based Models. ISPASS 2022: 187-197 - [c78]Drew Zagieboylo, Charles Sherk, Gookwon Edward Suh, Andrew C. Myers:
PDL: a high-level hardware design language for pipelined processors. PLDI 2022: 719-732 - [i21]Yaohui Cai, Weizhe Hua, Hongzheng Chen
Structured Pruning is All You Need for Pruning CNNs at Initialization. CoRR abs/2203.02549 (2022) - [i20]Shaowei Zhu, Hyo Jin Kim, Maurizio Monge, G. Edward Suh, Armin Alaghi, Brandon Reagen, Vincent T. Lee:
Verifiable Access Control for Augmented Reality Localization and Mapping. CoRR abs/2203.13308 (2022) - [i19]Mulong Luo, G. Edward Suh:
Accelerating Path Planning for Autonomous Driving with Hardware-Assisted Memoization. CoRR abs/2205.02754 (2022) - [i18]Mulong Luo, Wenjie Xiong
AutoCAT: Reinforcement Learning for Automated Exploration of Cache Timing-Channel Attacks. CoRR abs/2208.08025 (2022) - [i17]Sanjay Kariyappa, Chuan Guo, Kiwan Maeng, Wenjie Xiong
Cocktail Party Attack: Breaking Aggregation-Based Privacy in Federated Learning using Independent Component Analysis. CoRR abs/2209.05578 (2022) - [i16]Kiwan Maeng, Chuan Guo, Sanjay Kariyappa, G. Edward Suh:
Measuring and Controlling Split Layer Privacy Leakage Using Fisher Information. CoRR abs/2209.10119 (2022) - [i15]Pengzhi Huang, Thang Hoang, Yueying Li, Elaine Shi, G. Edward Suh:
STAMP: Lightweight TEE-Assisted MPC for Efficient Privacy-Preserving Machine Learning. CoRR abs/2210.10133 (2022) - [i14]Liu Ke, Xuan Zhang, Benjamin Lee, G. Edward Suh, Hsien-Hsin S. Lee:
DisaggRec: Architecting Disaggregated Systems for Large-Scale Personalized Recommendation. CoRR abs/2212.00939 (2022) - [i13]Hanieh Hashemi, Wenjie Xiong
Data Leakage via Access Patterns of Sparse Features in Deep Learning-based Recommendation Systems. CoRR abs/2212.06264 (2022) - 2021
- [j9]Benjamin Wu
Guessing Outputs of Dynamically Pruned CNNs Using Memory Access Patterns. IEEE Comput. Archit. Lett. 20(2): 98-101 (2021) - [c77]Sungbo Park
BCD deduplication: effective memory compression using partial cache-line deduplication. ASPLOS 2021: 52-64 - [c76]Yanqi Zhang
Sinan: ML-based and QoS-aware resource management for cloud microservices. ASPLOS 2021: 167-181 - [c75]Alexander S. La Cour
Wireless Charging Power Side-Channel Attacks. CCS 2021: 651-665 - [c74]Weizhe Hua, Yichi Zhang, Chuan Guo, Zhiru Zhang, G. Edward Suh:
BulletTrain: Accelerating Robust Neural Network Training via Boundary Example Mining. NeurIPS 2021: 18527-18538 - [i12]Alexander S. La Cour, Khurram K. Afridi, G. Edward Suh:
Wireless Charging Power Side-Channel Attacks. CoRR abs/2105.12266 (2021) - [i11]Yanqi Zhang, Weizhe Hua, Zhuangzhuang Zhou, G. Edward Suh, Christina Delimitrou:
Sinan: Data-Driven, QoS-Aware Cluster Management for Microservices. CoRR abs/2105.13424 (2021) - [i10]Weizhe Hua, Yichi Zhang, Chuan Guo, Zhiru Zhang, G. Edward Suh:
BulletTrain: Accelerating Robust Neural Network Training via Boundary Example Mining. CoRR abs/2109.14707 (2021) - [i9]Yanqi Zhang, Weizhe Hua, Zhuangzhuang Zhou, G. Edward Suh, Christina Delimitrou:
Sinan: Data Driven Resource Management for Cloud Microservices. CoRR abs/2112.06254 (2021) - [i8]Wenjie Xiong, Liu Ke, Dimitrije Jankov, Michael Kounavis, Xiaochen Wang, Eric Northup, Jie Amy Yang, Bilge Acun, Carole-Jean Wu, Ping Tak Peter Tang, G. Edward Suh, Xuan Zhang, Hsien-Hsin S. Lee:
SecNDP: Secure Near-Data Processing with Untrusted Memory. IACR Cryptol. ePrint Arch. 2021: 1642 (2021) - 2020
- [j8]Jacopo Banfi
Path Planning Under Malicious Injections and Removals of Perceived Obstacles: A Probabilistic Programming Approach. IEEE Robotics Autom. Lett. 5(4): 6884-6891 (2020) - [c73]Mohamed Ismail, G. Edward Suh
Efficient nursery sizing for managed languages on multi-core processors with shared caches. CGO 2020: 1-15 - [c72]Benjamin Wu, Aaron B. Wagner, G. Edward Suh:
Optimal Mechanisms Under Maximal Leakage. CNS 2020: 1-6 - [c71]Yichi Zhang
Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations. ICLR 2020 - [c70]Benjamin Wu, Aaron B. Wagner, G. Edward Suh, Ibrahim Issa:
Strong Asymptotic Composition Theorems for Sibson Mutual Information. ISIT 2020: 2222-2227 - [c69]Mulong Luo, Andrew C. Myers, G. Edward Suh:
Stealthy Tracking of Autonomous Vehicles with Cache Side Channels. USENIX Security Symposium 2020: 859-876 - [i7]Yichi Zhang, Ritchie Zhao, Weizhe Hua, Nayun Xu, G. Edward Suh, Zhiru Zhang:
Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations. CoRR abs/2002.07136 (2020) - [i6]Benjamin Wu, Aaron B. Wagner, G. Edward Suh:
A Case for Maximal Leakage as a Side Channel Leakage Metric. CoRR abs/2004.08035 (2020) - [i5]Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh:
MgX: Near-Zero Overhead Memory Protection with an Application to Secure DNN Acceleration. CoRR abs/2004.09679 (2020) - [i4]Benjamin Wu, Aaron B. Wagner, G. Edward Suh, Ibrahim Issa:
Strong Asymptotic Composition Theorems for Sibson Mutual Information. CoRR abs/2005.06033 (2020) - [i3]Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh:
GuardNN: Secure DNN Accelerator for Privacy-Preserving Deep Learning. CoRR abs/2008.11632 (2020) - [i2]Drew Zagieboylo, G. Edward Suh, Andrew C. Myers:
The Cost of Software-Based Memory Management Without Virtual Memory. CoRR abs/2009.06789 (2020)
2010 – 2019
- 2019
- [c68]Drew Zagieboylo, G. Edward Suh, Andrew C. Myers:
Using Information Flow to Design an ISA that Controls Timing Channels. CSF 2019: 272-287 - [c67]Zhenghong Jiang, Hanchen Jin, G. Edward Suh
Designing Secure Cryptographic Accelerators with Information Flow Enforcement: A Case Study on AES. DAC 2019: 59 - [c66]Eojin Lee, Ingab Kang, Sukhan Lee, G. Edward Suh
TWiCe: preventing row-hammering by exploiting time window counters. ISCA 2019: 385-396 - [c65]Weizhe Hua, Yuan Zhou, Christopher De Sa, Zhiru Zhang
Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating. MICRO 2019: 139-150 - [c64]Weizhe Hua, Yuan Zhou, Christopher De Sa, Zhiru Zhang, G. Edward Suh:
Channel Gating Neural Networks. NeurIPS 2019: 1884-1894 - 2018
- [j7]Eojin Lee
TWiCe: Time Window Counter Based Row Refresh to Prevent Row-Hammering. IEEE Comput. Archit. Lett. 17(1): 96-99 (2018) - [c63]Jed Liu, Joe Corbett-Davies, Andrew Ferraiuolo, Alexander Ivanov, Mulong Luo, G. Edward Suh
Secure Autonomous Cyber-Physical Systems Through Verifiable Information Flow Control. CPS-SPC@CCS 2018: 48-59 - [c62]Andrew Ferraiuolo, Mark Zhao
HyperFlow: A Processor Architecture for Nonmalleable, Timing-Safe Information Flow Security. CCS 2018: 1583-1600 - [c61]Weizhe Hua, Zhiru Zhang
Reverse engineering convolutional neural networks through side-channel information leaks. DAC 2018: 4:1-4:6 - [c60]Zhenghong Jiang, Steve Dai, G. Edward Suh
High-level synthesis with timing-sensitive information flow enforcement. ICCAD 2018: 88 - [c59]Mohamed Ismail, G. Edward Suh:
Quantitative Overhead Analysis for Python. IISWC 2018: 36-47 - [c58]Mohamed Ismail, G. Edward Suh
Hardware-software co-optimization of memory management in dynamic languages. ISMM 2018: 45-58 - [c57]Tao Chen, Shreesha Srinath, Christopher Batten, G. Edward Suh
An Architectural Framework for Accelerating Dynamic Parallel Algorithms on Reconfigurable Hardware. MICRO 2018: 55-67 - [c56]Mark Zhao
FPGA-Based Remote Power Side-Channel Attacks. IEEE Symposium on Security and Privacy 2018: 229-244 - [i1]Weizhe Hua, Christopher De Sa, Zhiru Zhang, G. Edward Suh:
Channel Gating Neural Networks. CoRR abs/1805.12549 (2018) - 2017
- [c55]Andrew Ferraiuolo, Rui Xu, Danfeng Zhang
Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis. ASPLOS 2017: 555-568 - [c54]Andrew Ferraiuolo, Weizhe Hua, Andrew C. Myers, G. Edward Suh
Secure Information Flow Verification with Mutable Dependent Types. DAC 2017: 6:1-6:6 - [c53]Yao Wang, Benjamin Wu, G. Edward Suh:
Secure Dynamic Memory Scheduling Against Timing Channel Attacks. HPCA 2017: 301-312 - 2016
- [c52]Yao Wang, Andrew Ferraiuolo, Danfeng Zhang
SecDCP: secure dynamic cache partitioning for efficient timing channel protection. DAC 2016: 74:1-74:6 - [c51]Andrew Ferraiuolo, Yao Wang, Danfeng Zhang
Lattice priority scheduling: Low-overhead timing-channel protection for a shared memory controller. HPCA 2016: 382-393 - [c50]Taejoon Song, Daniel Lo, G. Edward Suh
Prediction-Guided Performance-Energy Trade-off with Continuous Run-Time Adaptation. ISLPED 2016: 224-229 - [c49]Tao Chen, G. Edward Suh:
Efficient data supply for hardware accelerators with prefetching and access/execute decoupling. MICRO 2016: 46:1-46:12 - 2015
- [c48]Danfeng Zhang
A Hardware Design Language for Timing-Sensitive Information-Flow Security. ASPLOS 2015: 503-516 - [c47]Mohamed Ismail, Daniel Lo, G. Edward Suh
Improving worst-case cache performance through selective bypassing and register-indexed cache. DAC 2015: 123:1-123:6 - [c46]Daniel Lo, Tao Chen, Mohamed Ismail, G. Edward Suh:
Run-time monitoring with adjustable overhead using dataflow-guided filtering. HPCA 2015: 662-674 - [c45]Tao Chen, Alexander Rucker, G. Edward Suh
Execution time prediction for energy-efficient hardware accelerators. MICRO 2015: 457-469 - [c44]Daniel Lo, Taejoon Song, G. Edward Suh
Prediction-guided performance-energy trade-off for interactive applications. MICRO 2015: 508-520 - 2014
- [c43]Ruirui C. Huang, Erik Halberg, Andrew Ferraiuolo, G. Edward Suh:
Low-overhead and high coverage run-time race detection through selective meta-data management. HPCA 2014: 96-107 - [c42]Yao Wang, Andrew Ferraiuolo, G. Edward Suh
Timing channel protection for a shared memory controller. HPCA 2014: 225-236 - [c41]G. Edward Suh
Author retrospective for analytical cache models with applications to cache partitioning. ICS 25th Anniversary 2014: 61-63 - [c40]G. Edward Suh
Author retrospective AEGIS: architecture for tamper-evident and tamper-resistant processing. ICS 25th Anniversary 2014: 68-70 - [c39]Daniel Lo, Mohamed Ismail, Tao Chen, G. Edward Suh:
Slack-aware opportunistic monitoring for real-time systems. RTAS 2014: 203-214 - 2013
- [j6]Michel A. Kinsy, Myong Hyon Cho, Keun Sup Shim, Mieszko Lis, G. Edward Suh
Optimal and Heuristic Application-Aware Oblivious Routing. IEEE Trans. Computers 62(1): 59-73 (2013) - [c38]Ruirui C. Huang, Erik Halberg, G. Edward Suh
Non-race concurrency bug detection through order-sensitive critical sections. ISCA 2013: 655-666 - [c37]Nithin Michael, Yao Wang, G. Edward Suh, Ao Tang:
Quadrisection-based task mapping on many-core processors for energy-efficient on-chip communication. NOCS 2013: 1-2 - [c36]Yinglei Wang, Wing-Kei S. Yu, Sarah Q. Xu, Edwin Kan, G. Edward Suh
Hiding Information in Flash Memory. IEEE Symposium on Security and Privacy 2013: 271-285 - 2012
- [c35]Ruby B. Lee, Simha Sethumadhavan, G. Edward Suh:
Hardware enhanced security. CCS 2012: 1052 - [c34]Nithin Michael, Ao Tang, G. Edward Suh:
On the performance of averaged optimal routing. CISS 2012: 1-6 - [c33]Daniel Lo, G. Edward Suh
Worst-case execution time analysis for parallel run-time monitoring. DAC 2012: 421-429 - [c32]Daniel Y. Deng, G. Edward Suh:
High-performance parallel accelerator for flexible and efficient run-time monitoring. DSN 2012: 1-12 - [c31]Mohamed Ismail, G. Edward Suh:
Fast development of hardware-based run-time monitors through architecture framework and high-level synthesis. ICCD 2012: 393-400 - [c30]Yao Wang, G. Edward Suh:
Efficient Timing Channel Protection for On-Chip Networks. NOCS 2012: 142-151 - [c29]Yinglei Wang, Wing-Kei S. Yu, Shuo Wu, Greg Malysa, G. Edward Suh
Flash Memory for Ubiquitous Hardware Security Functions: True Random Number Generation and Device Fingerprints. IEEE Symposium on Security and Privacy 2012: 33-47 - 2011
- [c28]Wing-Kei S. Yu, Shantanu Rajwade, Sung-En Wang, Bob Lian, G. Edward Suh
A non-volatile microcontroller with integrated floating-gate transistors. DSN Workshops 2011: 75-80 - [c27]Daniel Lo, Greg Malysa, G. Edward Suh
FlexCache: Field Extensible Cache Controller Architecture Using On-chip Reconfigurable Fabric. FPL 2011: 244-251 - [c26]Daniel Y. Deng, G. Edward Suh
Precise exception support for decoupled run-time monitoring architectures. ICCD 2011: 437-438 - [c25]Wing-Kei S. Yu, Ruirui C. Huang, Sarah Q. Xu, Sung-En Wang, Edwin Kan, G. Edward Suh
SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading. ISCA 2011: 247-258 - [c24]Nithin Michael, Milen Nikolov, Ao Tang, G. Edward Suh
Analysis of application-aware on-chip routing under traffic uncertainty. NOCS 2011: 9-16 - [c23]Ruirui C. Huang, David Grawrock, David C. Doughty, G. Edward Suh:
Systematic Security Assessment at an Early Processor Design Stage. TRUST 2011: 154-171 - [c22]Pravin Prabhu, Ameen Akel, Laura M. Grupp, Wing-Kei S. Yu, G. Edward Suh, Edwin Kan, Steven Swanson
Extracting Device Fingerprints from Flash Memory by Exploiting Physical Variations. TRUST 2011: 188-201 - 2010
- [c21]Ruirui C. Huang, Daniel Y. Deng, G. Edward Suh
Orthrus: efficient software integrity protection on multi-cores. ASPLOS 2010: 371-384 - [c20]Skyler Schneider, Daniel Y. Deng, Daniel Lo, Greg Malysa, G. Edward Suh
Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only). FPGA 2010: 285 - [c19]Ruirui C. Huang, G. Edward Suh
IVEC: off-chip memory integrity protection for both security and reliability. ISCA 2010: 395-406 - [c18]Daniel Y. Deng, Daniel Lo, Greg Malysa, Skyler Schneider, G. Edward Suh
Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric. MICRO 2010: 137-148 - [c17]Shantanu Rajwade, Wing-Kei S. Yu, Sarah Q. Xu, Tuo-Hung Hou
Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash. SoCC 2010: 461-466 - [p1]Daniel Y. Deng, Andrew H. Chan, G. Edward Suh:
Authentication of Processor Hardware Leveraging Performance Limits in Detailed Simulations and Emulations. Towards Hardware-Intrinsic Security 2010: 309-329
2000 – 2009
- 2009
- [c16]Daniel Y. Deng, Andrew H. Chan, G. Edward Suh
Hardware authentication leveraging performance limits in detailed simulations and emulations. DAC 2009: 682-687 - [c15]Michel A. Kinsy, Myong Hyon Cho, Tina Wen, G. Edward Suh, Marten van Dijk
Application-aware deadlock-free oblivious routing. ISCA 2009: 208-219 - [c14]Keun Sup Shim, Myong Hyon Cho, Michel A. Kinsy, Tina Wen, Mieszko Lis, G. Edward Suh
Static virtual channel allocation in oblivious routing. NOCS 2009: 38-43 - 2008
- [c13]Myong Hyon Cho, Chih-Chi Cheng, Michel A. Kinsy, G. Edward Suh, Srinivas Devadas:
Diastolic arrays: throughput-driven reconfigurable computing. ICCAD 2008: 457-464 - 2007
- [j5]G. Edward Suh
Aegis: A Single-Chip Secure Processor. IEEE Des. Test Comput. 24(6): 570-580 (2007) - [c12]G. Edward Suh
Physical Unclonable Functions for Device Authentication and Secret Key Generation. DAC 2007: 9-14 - 2006
- [j4]Marten van Dijk
Speeding up Exponentiation using an Untrusted Computational Resource. Des. Codes Cryptogr. 39(2): 253-273 (2006) - 2005
- [b1]G. Edward Suh:
AEGIS: a single-chip secure processor. Massachusetts Institute of Technology, Cambridge, MA, USA, 2005 - [j3]G. Edward Suh, Charles W. O'Donnell, Srinivas Devadas:
AEGIS: A single-chip secure processor. Inf. Secur. Tech. Rep. 10(2): 63-73 (2005) - [j2]Daihyun Lim, Jae W. Lee, Blaise Gassend, G. Edward Suh
Extracting secret keys from integrated circuits. IEEE Trans. Very Large Scale Integr. Syst. 13(10): 1200-1205 (2005) - [c11]G. Edward Suh
Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions. ISCA 2005: 25-36 - [c10]Dwaine E. Clarke
Towards Constant Bandwidth Overhead Integrity Checking of Untrusted Data. S&P 2005: 139-153 - 2004
- [j1]G. Edward Suh, Larry Rudolph, Srinivas Devadas:
Dynamic Partitioning of Shared Cache Memory. J. Supercomput. 28(1): 7-26 (2004) - [c9]G. Edward Suh
Secure program execution via dynamic information flow tracking. ASPLOS 2004: 85-96 - 2003
- [c8]Dwaine E. Clarke, Srinivas Devadas, Marten van Dijk
Incremental Multiset Hash Functions and Their Application to Memory Integrity Checking. ASIACRYPT 2003: 188-207 - [c7]Prabhat Jain, G. Edward Suh, Srinivas Devadas:
Embedded intelligent SRAM. DAC 2003: 869-874 - [c6]Blaise Gassend, G. Edward Suh, Dwaine E. Clarke
Caches and Hash Trees for Efficient Memory Integrity Verification. HPCA 2003: 295-306 - [c5]G. Edward Suh, Dwaine E. Clarke
AEGIS: architecture for tamper-evident and tamper-resistant processing. ICS 2003: 160-171 - [c4]G. Edward Suh
Efficient Memory Integrity Verification and Encryption for Secure Processors. MICRO 2003: 339-350 - 2002
- [c3]G. Edward Suh, Srinivas Devadas, Larry Rudolph:
A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning. HPCA 2002: 117-128 - 2001
- [c2]G. Edward Suh, Srinivas Devadas, Larry Rudolph:
Analytical cache models with applications to cache partitioning. ICS 2001: 1-12 - [c1]G. Edward Suh, Larry Rudolph, Srinivas Devadas:
Effects of Memory Performance on Parallel Job Scheduling. JSSPP 2001: 116-132
Coauthor Index
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