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Journal of Electronic Testing, Volume 19
Volume 19, Number 1, February 2003
- Vishwani D. Agrawal:
Editorial. 5 - André Ivanov:
Test Technology Technical Council Newsletter. 7-8 - Víctor H. Champac, Ingrid Jansch-Pôrto:
Guest Editorial. 11 - L. Cassol, O. Betat, Luigi Carro
, Marcelo Lubaszewski:
The SigmaDelta-BIST Method Applied to Analog Filters. 13-20 - Gladys Omayra Ducoudray, Jaime Ramírez-Angulo:
Innovative Built-In Self-Test Schemes for On-Chip Diagnosis, Compliant with the IEEE 1149.4 Mixed-Signal Test Bus Standard. 21-28 - Luis Hernández-Martínez
Topological Considerations for the Diagnosability Conditions of Analogue Circuits Using a Pair of Conjugate Trees. 29-36 - Ilia Polian, Bernd Becker
Multiple Scan Chain Design for Two-Pattern Testing. 37-48 - Marie-Lise Flottes, Christian Landrault, A. Petitqueux:
A Unified DFT Approach for BIST and External Test. 49-60 - Fabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.:
A New On-Line Robust Approach to Design Noise-Immune Speech Recognition Systems. 61-72 - Raimund Ubar:
Design Error Diagnosis with Re-Synthesis in Combinational Circuits. 73-82 - Raoul Velazco, Sana Rezgui, Haissam Ziade:
Assessing the Soft Error Rate of Digital Architectures Devoted to Operate in Radiation Environment: A Case Studied. 83-90
Volume 19, Number 2, April 2003
- Vishwani D. Agrawal:
Editorial. 95 - André Ivanov:
Test Technology Technical Council Newsletter. 99-100 - André Ivanov:
Guest Editorial. 101-102 - Nektarios Kranitis
Instruction-Based Self-Testing of Processor Cores. 103-112 - Krishna Sekar, Sujit Dey:
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects. 113-123 - Erik H. Volkerink, Ajay Khoche, Jochen Rivoir, Klaus-Dieter Hilliges:
Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits. 125-135 - Wanli Jiang, Eric Peterson:
Performance Comparison of VLV, ULV, and ECR Tests. 137-147 - Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra, Raghuram S. Tupuri:
A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages. 149-160 - Shi-Yu Huang:
A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis. 161-172 - Sule Ozev, Alex Orailoglu:
Statistical Tolerance Analysis for Assured Analog Test Coverage. 173-182 - Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha:
Timing Jitter Measurement of Intrinsic Random Jitter and Sinusoidal Jitter Using Frequency Division. 183-193 - Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Mike Rodgers:
Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests. 195-205 - Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu
Testing and Diagnosis Methodologies for Embedded Content Addressable Memories. 207-215
Volume 19, Number 3, June 2003
- Vishwani D. Agrawal:
Editorial. 219 - André Ivanov:
Test Technology Technical Council Newsletter. 221-222 - Christophe Fagot, Olivier Gascuel, Patrick Girard
A Ring Architecture Strategy for BIST Test Pattern Generation. 223-231 - Dimitri Kagaris, Spyros Tragoudas:
LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds. 233-244 - Hao-Yung Lo, Hsiu-Feng Lin, Chichyang Chen, Jenshiuh Liu, Chia-Cheng Liu:
Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers. 245-269 - Hailong Cui, Sharad C. Seth, Shashank K. Mehta:
Modeling Fault Coverage of Random Test Patterns. 271-284 - Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis
Easily Testable Cellular Carry Lookahead Adders. 285-298 - Muhammad Nummer, Manoj Sachdev:
A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers. 299-314 - Shyue-Kung Lu:
A Novel Built-In Self-Repair Approach for Embedded RAMs. 315-324 - Claude Thibeault:
Replacing IDDQ Testing: With Variance Reduction. 325-340 - Oleg Semenov, Arman Vassighi, Manoj Sachdev:
Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta IDDQ Testing. 341-352 - Josep Altet
Thermal Testing of Analogue Integrated Circuits: A Case Study. 353-357
Volume 19, Number 4, August 2003
- Vishwani D. Agrawal:
Editorial. 363 - André Ivanov:
Test Technology Technical Council Newsletter. 365-366 - Christian Landrault:
Guest Editorial. 367 - Camelia Hora, Rene Segers, Stefan Eichenberger, Maurice Lousberg:
On a Statistical Fault Diagnosis Approach Enabling Fast Yield Ramp-Up. 369-376 - Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short. 377-386 - Jonathan Bradford, Hartmut Delong, Ilia Polian, Bernd Becker
Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting. 387-395 - Frank te Beest, Ad M. G. Peeters, Kees van Berkel, Hans G. Kerkhoff:
Synchronous Full-Scan for Asynchronous Handshake Circuits. 397-406 - Sandeep Kumar Goel, Bart Vermeulen:
Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. 407-416 - Bart Vermeulen, Tom Waayers, Sjaak Bakker:
Multi-TAP Controller Architecture for Digital System Chips. 417-424 - Sandeep Kumar Goel, Erik Jan Marinissen
A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips. 425-435
- Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran:
Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors. 437-445 - Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara:
On Selecting Testable Paths in Scan Designs. 447-456 - Ozgur Sinanoglu
Reducing Average and Peak Test Power Through Scan Chain Modification. 457-467 - Serge Bernard
On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST. 469-479 - Martin John Burbidge, Frédéric Poullet, Jim Tijou, Andrew Richardson
Investigations for Minimum Invasion Digital Only Built-In "Ramp" Based Test Techniques for Charge Pump PLL's. 481-490
Volume 19, Number 5, October 2003
- Vishwani D. Agrawal:
Editorial. 495 - André Ivanov:
Test Technology Technical Council Newsletter. 497-498 - Cecilia Metra, Matteo Sonza Reorda
Guest Editorial. 499 - Matthias Pflanz, Karsten Walther, Christian Galke, Heinrich Theodor Vierhaus:
On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check. 501-510 - Daniele Rossi
Error Correcting Strategy for High Speed and High Density Reliable Flash Memories. 511-521 - Parag K. Lala, B. Kiran Kumar:
An Architecture for Self-Healing Digital Systems. 523-535 - Feng Gao, John P. Hayes:
On-Line Monitor Design of Finite-State Machines. 537-548 - Miron Abramovici, Charles E. Stroud:
BIST-Based Delay-Fault Testing in FPGAs. 549-558 - Régis Leveugle, K. Hadjiat:
Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments. 559-575 - Maurizio Rebaudengo
Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor. 577-584 - Marcelo Negreiros
A Statistical Sampler for a New On-Line Analog Test Method. 585-595 - Joan Font
A BICS for CMOS OpAmps by Monitoring the Supply Current Peak. 597-603
Volume 19, Number 6, December 2003
- Vishwani D. Agrawal:
Editorial. 607 - A. Ivanov:
Test Technology Technical Council Newsletter. 609-610 - Chintan Patel, Ernesto Staroswiecki, Smita Pawar, Dhruva Acharyya, Jim Plusquellic:
Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids. 611-623 - Claude Thibeault:
On Faster IDDQ Measurements. 625-635 - Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz:
A Low Power Pseudo-Random BIST Technique. 637-644 - Janusz Rajski, Jerzy Tyszer:
Primitive Polynomials Over GF(2) of Degree up to 660 with Uniformly Distributed Coefficients. 645-657
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