Abstract
Embedded content addressable memories (CAMs) are important components in many system chips where most CAMs are customized and have wide words. This poses challenges on testing and diagnosis. In this paper two efficient March-like test algorithms are proposed first. In addition to typical RAM faults, they also cover CAM-specific comparison faults. The first algorithm requires 9N Read/Write operations and 2(N + W) Compare operations to cover comparison and RAM faults (but does not fully cover the intra-word coupling faults), for an N × W-bit CAM. The second algorithm uses 3N log2 W Write and 2W log2 W Compare operations to cover the remaining intra-word coupling faults. Compared with the previous algorithms, the proposed algorithms have higher fault coverage and lower time complexity. Moreover, it can test the CAM even when its comparison result is observed only by the Hit output or the priority encoder output. We also present the algorithms that can locate the cells with comparison faults. Finally, a CAM BIST design is briefly described.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
T. Chadwick, T. Gordon, R. Nadkarni, and J. Rowland, “An ASIC-Embedded Content Addressable Memory with Power-Saving and Design for Test Features,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2001, pp. 183-186.
R. Dekker, F. Beenker, and L. Thijssen, “ARealistic Fault Model and Test Algorithm for Static Random Access Memories,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 6, pp. 567-572, June 1990.
Y.S. Kang, J.C. Lee, and S. Kang, “Parallel BIST Architecture for CAMs,” Electronics Letters, vol. 33, no. 1, pp. 30-31, Jan. 1997.
S. Kornachuk, L. McNaughton, R. Gibbins, and B. NadeauDostie, “A High Speed Embedded Cache Design with Non-Intrusive BIST,” in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), San Jose, 1994, pp. 40-45.
K.-J. Lin and C.-W. Wu, “Testing Content-Addressable Memories Using Functional Fault Models and March-Like Algorithms,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 5, pp. 577-588, May 2000.
P. Mazumder, J.H. Patel, and W.K. Fuchs, “Methodologies for Testing Embedded Content Addressable Memories,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 1, pp. 11-20, Jan. 1988.
A.J. McAuley and C.J. Cotton, “A Self-Testing Reconfigurable CAM,” IEEE Journal of Solid-State Circuits, vol. 26, no. 3, pp. 257-261, March 1991.
B. Nadeau-Dostie, A. Silburt, and V.K. Agarwal, “A Serial Interfacing Technique for External and Built-in Self-Testing of Embedded Memories,” IEEE Design & Test of Computers, vol. 7, no. 2, pp. 56-64, April 1990.
K.J. Schultz, “Content-Addressable Memory Core Cells: A Survey,” Integration, the VLSI J., vol. 23, pp. 171-188, 1997.
A.J. van de Goor, Testing Semiconductor Memories: Theory and Practice, Chichester, England: John Wiley & Sons, 1991.
C.-F. Wu, C.-T. Huang, and C.-W. Wu, “RAMSES:AFast Memory Fault Simulator,” in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), Albuquerque, Nov. 1999, pp. 165-173.
J. Zhao, S. Irrinki, M. Puri, and F. Lombardi, “Testing SRAM-Based Content Addressable Memories,” IEEE Trans. Computers, vol. 49, no. 10, pp. 1054-1063, Oct. 2000.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Li, JF., Tzeng, RS. & Wu, CW. Testing and Diagnosis Methodologies for Embedded Content Addressable Memories. Journal of Electronic Testing 19, 207–215 (2003). https://doi.org/10.1023/A:1022858128485
Issue Date:
DOI: https://doi.org/10.1023/A:1022858128485