Abstract
Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine General's phenomenon, in which a fault manifests itself as a non-logical voltage level at the fault site. Previously, explicit enumeration was suggested to deal with such a problem. However, it is often too time-consuming because the CPU time is exponentially proportional to fanout degree of the circuit under diagnosis. To speed up this process, we present an implicit enumeration technique using symbolic simulation. Experimental results show that the CPU time can be improved by several orders of magnitude for the ISCAS85 benchmark circuits while locating the faults accurately.
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References
M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital System Testing and Testable Design, Computer Science Press, 1990.
R.C. Aitken, “Modelling the Unmodellable: Algorithmic Fault Diagnosis,” in Proc. of Int’l Test Conference, 1996, pp. 931-940.
B. Boppana, R. Mukherjee, J. Jain, and M. Fujita, “Multiple Error Diagnosis Based on Xlists,” in Proc. of Design Automation Conf., June 1999, pp. 100-110.
R.K. Brayton et al., “SIS: A System for Sequential Circuit Synthesis,” University of California, Berkeley, Tech. Report, 1992.
R.E. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation,” IEEE Trans. on Computers, vol. 35, no. 8, pp. 677-691, Aug. 1986.
P.Y. Chung, Y.M. Wang, and I.N. Hajj, “Diagnosis and Correction of Logic Design Errors in Digital Circuits,” in Proc. of Design Automation Conf., June 1993, pp. 503-508.
S.-Y. Huang,“On Improving the Accuracy of Multiple Fault Diagnosis,” in Proc. of VLSI Test Symposium, April 2001, pp. 34-39.
S.-Y. Huang, K.-T. Cheng, K.-C. Chen, and D.-T. Cheng, “ErrorTracer: A Fault Simulation Based Approach to Design Error Diagnosis,” in Proc. of Int’l Test Conf., Nov. 1997, pp. 974-981.
J.B. Khare, W. Maly, S. Griep, and D. Schmitt-Landsiedel, “Yield-Oriented Computer-Aided Defect Diagnosis,” IEEE Transactions on Semiconductor Manufacturing, vol. 8, no. 2, pp. 195-206, May 1995.
A. Kuehlmann, D.I. Cheng, A. Srinivasan, and D.P. Lapotin, “Error Diagnosis for Transistor-Level Verification,” in Proc. of Design Automation Conf., June 1994, pp. 218-223.
D.B. Lavo, T. Larabee, and B. Chess, “Beyond the Byzantine Generals: Unexpected Behavior and Bridging Fault Diagnosis,” in Proc. of Int’l Test Conference, 1996, pp. 611-619.
I. Pomeranz and S.M. Reddy, “On Correction of Multiple Design Errors,” IEEE Trans. on Computer-Aided Design, vol. 14, pp. 255-264, Feb. 1995.
J. Richman and K.R. Bowden, “The Modern Fault Dictionary,” in Proc. of Int’l Test Conf., Nov. 1985, pp. 696-702.
A.G. Veneris and I.N. Hajj, “A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits,” in Proc. of Great Lake Symposium on VLSI Design, March 1997, pp. 45-50.
J. Wu and E.M. Rudnick, “Bridging Fault Diagnosis Using Stuck-at Fault Simulation,”IEEE Trans. on Computer-Aided Design, vol. 19, no. 4, pp. 489-495, April 2000.
S. Venkataraman and S.B. Drummonds, “A Technique for Logic Fault Diagnosis of Interconnect Open Faults,” in Proc. of VLSI Test Symposium, 2000, pp. 313-318.
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Huang, SY. A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis. Journal of Electronic Testing 19, 161–172 (2003). https://doi.org/10.1023/A:1022889623942
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DOI: https://doi.org/10.1023/A:1022889623942