default search action
EURO-DAC 1991: Hamburg, Germany
- Tony Ambler, Jochen A. G. Jess, Hugo De Man:
Proceedings of the conference on European design automation, EURO-DAC'91, Amsterdam, The Netherlands, 1991. EEE Computer Society 1991, ISBN 0-8186-2130-3
Formal verification techniques
- Don E. Ross, Kenneth M. Butler, Rohit Kapur, M. Ray Mercer:
Fast functional evaluation of candidate OBDD variable orderings. 4-10 - Paolo Camurati, Tiziana Margaria, Paolo Prinetto:
Resolution-based correctness proofs of synchronous circuits. 11-15 - Frank P. Burns, D. J. Kinniment, Albert Koelmans:
Correct interactive transformational synthesis of DSP hardware. 16-21 - Fridtjof Feldbusch, Ramayya Kumar:
Verification of synthesized circuits at register transfer level with flow graphs. 22-26
Frameworks
- Bernd Kleinjohann, Elisabeth Kupitz:
Tool communication in an integrated synthesis environment. 28-32 - Wanlin Cao, Y. Edmund Lien, Yuane Qiu, Li Shao:
A distributed engineering database management system for IC design. 33-37 - Mahesh Mehendale:
An approach to design flow management in CAD frameworks. 38-42 - Klaus Gröning, Walter Heijenga:
Why to incorporate a data definition language into a CAD frameworks extension language. 43-47
Logic synthesis
- Masahiro Fujita, Yusuke Matsunaga, Taeko Kakuda:
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. 50-54 - F. Crowet, Marc Davio, C. Dierieck, J. Durieu, G. Louis, Chantal Ykman-Couvreur:
PHIFACT a design space exploration program. 55-59 - Frank Buijs, Thomas Lengauer:
Synthesis of multi-level logic with one symbolic input. 60-64 - Tadeusz Luba, Jerzy Kalinowski, Krzysztof Jasinski:
PLATO: a CAD tool for logic synthesis based on decomposition. 65-69
Fault modeling and test generation
- Antonio Rubio, Noriyoshi Itazaki, Xiaole Xu, Kozo Kinoshita:
An approach to the analysis and test of crosstalk faults in digital VLSI circuits. 72-79 - M. Ambanelli, Michele Favalli, Piero Olivo, Bruno Riccò:
Detection of PLA multiple crosspoint faults. 80-84 - Michele Favalli, Piero Olivo, Bruno Riccò:
A probabilistic fault model for analog faults. 85-88 - Alice McKeon, Antony Wakeling:
The automatic diagnosis of faults in analogue and mixed-signal circuits. 89-93
Layout analysis
- Daniel Auvergne, Nadine Azémard, V. Bonzom, Denis Deschacht, Michel Robert:
Formal sizing rules of CMOS circuits. 96-100 - Jan Madsen:
Delay estimation for CMOS functional cells. 101-105 - K. Z. Dimopoulos, John N. Avaritsiotis, S. J. White:
Electrical modelling of lossy on-chip multilevel interconnecting lines. 106-110 - Ravi Nair, Vivek Chickermane, Ray Chamberlain:
Restructuring VLSI layout representations for efficiency. 111-116
Data path synthesis
- Douglas M. Grant, Peter B. Denyer:
Address Generation for array access based on modulus m counters. 118-122 - F. Monteiro, Bruno Rouzeyre, Georges Sagnes:
High level synthesis: a data path partitioning method dedicated to speed enhancement. 123-128 - David W. Knapp:
Datapath optimization using feedback. 129-134
Circuit simulation and macromodelling
- Joel Besnard, Jacques Benkoski, Bernard Hennion:
Eldo-XL: a software accelerator for the analysis of digital MOS circuits by an analog simulator. 136-141 - Shen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh:
SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits. 142-148 - Werner John, Werner Rissiek, Karl L. Paap:
Circuit partitioning for waveform relaxation. 149-153 - P. Hallam, T. I. Pritchard, Gloria Childress Townsend:
Performance macromodelling and optimization of regular VLSI structures. 154-159
Partitioning for layout
- Allen C.-H. Wu, Daniel D. Gajski:
Glue-logic partitioning for floorplans with a rectilinear datapath. 162-166 - Achim G. Hoffmann:
Towards optimizing global MinCut partitioning. 167-171 - S. Bapat, James P. Cohoon:
SHARP-looking geometric partitioning. 172-176 - Paul Stravers:
Partitioning a network into n pieces with a time-efficient net cost function. 177-182
Finite state machine optimisation
- Gary D. Hachtel, June-Kyung Rho, Fabio Somenzi, Reily M. Jacoby:
Exact and heuristic algorithms for the minimization of incompletely specified state machines. 184-191 - Lalgudi N. Kannan, D. Sarma:
Fast heuristic algorithms for finite state machine minimization. 192-196 - Michael Kishinevsky, Alex Kondratyev, Alexander Taubin:
Formal method for self-timed design. 197-201 - Lalgudi N. Kannan, D. Sarma:
Array folding using heuristics and simulated annealing. 202-205
Test pattern generation and diagnosis
- Jos van Sas, Francky Catthoor, Peter Vandeput, Frank Rossaert, Hugo De Man:
Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment. 208-213 - Thomas M. Niermann, Janak H. Patel:
HITEC: a test generation package for sequential circuits. 214-218 - Harald Gundlach, Bernd K. Koch, Klaus-Dieter Müller-Glaser:
On the selection of a partial scan path with respect to target faults. 219-223 - Benjamin Rogel-Favila, Antony Wakeling, Peter Y. K. Cheung:
Model-based fault diagnosis of sequential circuits and its acceleration. 224-229
Routing
- Steven T. Healey:
An algorithm for improving optimal placement for river-routing. 232-236 - Philippe Duchene, Michel J. Declercq, S. M. Kang:
An integrated layout system for sea-of-gates module generation. 237-241 - Kai-Win Lee, Carl Sechen:
A global router for sea-of-gates circuits. 237-241 - Dahe Chen, Carl Sechen:
Mickey: a macro cell global router. 248-252
Timing verification and specification
- Jacques Benkoski, Ronald B. Stewart:
TATOO: an industrial timing analyzer with false path elimination and test pattern generation. 256-260 - Amjad Hajjar, Alain Greiner, Roland Marbot, Payam Kiani:
TAS: an accurate timing analyser for CMOS VLSI. 261-265 - H. G. Yang, David M. Holburn:
A hierarchical approach to timing verification in CMOS VLSI design. 266-270 - Robert Tjärnström:
Clock independent timing verification of level-sensitive latches. 271-275
Synthesis of testable circuits
- Martin Rudolph, Michael Neher, Wolfgang Rosenstiel:
Test scheduling and controller synthesis in the CADDY-system. 278-282 - Roy Thomas, Sandip Kundu:
Synthesis of fully testable sequential machines. 283-288 - Bapiraju Vinnakota, Niraj K. Jha:
MACHETE: synthesis of sequential machines for easy testability. 289-293 - Françoise Martinolle, Jean Claude Geffroy, Bernard Soulas:
Testability analysis of hierarchical finite state machines. 294-301
Scheduling and allocation
- Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer:
Area and performance optimizations in path-based scheduling. 304-310 - Peter Gutberlet, Heinrich Krämer, Wolfgang Rosenstiel:
CASCH: a scheduling algorithm for "high level"-synthesis. 311-315 - Rumi Zahir, Wolfgang Fichtner:
Specification of timing constraints for controller synthesis. 316-322
Switch-level simulation
- Robert B. Mueller-Thuns, Daniel G. Saab, Jacob A. Abraham:
Parallel switch-level simulation for VLSI. 324-328 - David T. Blaauw, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham:
Functional abstraction of logic gates for switch-level simulation. 329-333 - Larry G. Jones:
Incremental switch-level simulation with zero/integer-delay. 334-338 - Suresh Rajgopal, Akhilesh Tyagi:
On probabilistic switch-level simulation for asynchronous circuits. 339-343
Floorplan optimization
- Luis París, G. Berbel, T. Osés:
Floorplanning strategy for mixed analog-digital VLSI integrated circuits. 346-350 - Fadi J. Kurdahi, Champaka Ramachandran:
LAST: a Layout Area and Shape function esTimator for high level applications. 351-355 - Ting-Chi Wang, D. F. Wong
:
Efficient shape curve construction in floorplan design. 356-360 - Georg Sigl, Ulf Schlichtmann:
Goal oriented slicing enumeration through shape function clipping. 361-365
Decompisition of finite state machines
- Gerard Tarroux, Bruno Rouzeyre, Georges Sagnes:
Optimization of micro-controllers by partitioning. 368-373 - D. Bochmann, F. Dresig, B. Steinbach:
A new decomposition method for multilevel circuit design. 374-377 - Wayne H. Wolf:
Decomposing data machines. 378-382
Formal verification
- Kees van Berkel, Joep L. W. Kessels, Marly Roncken, Ronald Saeijs, Frits D. Schalij:
The VLSI-programming language tangram and its translation into handshake circuits. 384-389 - Sanjiv Narayan, Frank Vahid, Daniel D. Gajski:
Translating system specifications to VHDL. 390-394 - Ton Kalker:
Formal methods for silicon compilation. 395-400 - Gjalt G. de Jong:
Data flow graphs: system specification with the most unrestricted semantics. 401-405
System design tools
- A. Compan, Alain Greiner, François Pêcheux, Frédéric Pétrot:
GENVIEW: a portable source-level debugger for macrocell generators. 408-412 - Farid Mheir-El-Saadi, Bozena Kaminska:
A framework for hierarchical performance analysis. 413-418 - Tzi-cker Chiueh:
HERESY: a hybrid approach to automatic schematic generation. 419-423 - Glenn Jennings:
GRTL: a graphical platform for pipelined system design. 424-428
Synthesis for high-speed applications
- Wim F. J. Verhaegh, Emile H. L. Aarts, Jan H. M. Korst, Paul E. R. Lippens:
Improved force-directed scheduling. 430-435 - Paul E. R. Lippens, Jef L. van Meerbergen, Albert van der Werf, Wim F. J. Verhaegh, B. T. McSweeney, Jos Huisken, O. McArdle:
PHIDEO: a silicon compiler for high speed algorithms. 436-441 - Jan Rosseel, Michaël F. X. B. van Swaaij, Francky Catthoor, Hugo De Man:
Affine transformations for multi-dimensional signal processing on ASIC regular arrays. 442-446
Object oriented approaches and modelling
- Shankar R. Mukherjee, Maqsoodul Mannan:
Switch and logic-level modeling in EDIF 200: limitations and proposed solutions. 448-452 - Mattie N. Sim, Patrick M. Dewilde:
Design of a persistent programming environment in an object oriented language using clustering and composite objects. 453-458 - A. J. van der Hoeven, Ed F. Deprettere, P. van Prooijen, Patrick M. Dewilde:
A hardware design system based on object-oriented principles. 459-463 - Anas Kabbaj, Eduard Cerny, Michel R. Dagenais, François Bouthillier:
Design by similarity using transaction modeling and statistical techniques. 464-468
Analogue design and layout
- Chin-Yuan Kuo, Liang-Gee Chen, Tai-Ming Parng:
An automatic synthesizer for CMOS operational amplifiers. 470-474 - Koen Swings, Willy Sansen:
DONALD: a workbench for interactive design space exploration and sizing of analog circuits. 475-479 - Louis-Oliver Donzelle, Pierre-François Dubois:
A new approach to layout of custom analog cells. 480-483 - Piet Wambacq, Georges G. E. Gielen, Willy Sansen:
Interactive symbolic distortion analysis of analogue integrated circuits. 484-488
Test pattern generation for combination circuits
- Sandip Kundu, Indira Nair, Leendert M. Huisman, Vijay S. Iyengar:
Symbolic implication in test generation. 492-496 - Bernd Becker, Ralf Hahn
Structure based methods for parallel pattern fault simulation in combinational circuits. 497-502 - Einar J. Aas, Gunnar Nystu:
Experiments with autonomous test of PLAs. 503-509 - Kholdoun Torki, Michael Nicolaidis, Antônio Otávio Fernandes:
A self-checking PLA automatic generator tool based on unordered codes encoding. 510-515
Partitioning techniques for CAD
- Spyros Tragoudas, R. Farrell, Fillia Makedon:
Circuit partitioning into small sets: a tool to support testing with further applications. 518-522 - James Haralambides, Fillia Makedon:
Iterative compaction: an improved approach to graph and circuit bisection. 523-527 - Hongzhong Wu:
On L × n boolean matrices with all L × k submatrices having 2k distinct row vectors. 528-532
Technology mapping
- David Filo, Jerry Chih-Yuan Yang, Frédéric Mailhot, Giovanni De Micheli:
Technology mapping for a two-output RAM-based field programmable gate array. 534-538 - Shen Lin, Malgorzata Marek-Sadowska:
A fast and efficient algorithm for determining fanout trees in large networks. 539-544 - Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli:
Optimization techniques for multiple output function synthesis. 545-551
High performance simulation techniques for digital systems
- Ernst G. Ulrich, Karen Panetta Lentz, Stephen R. Demba, Rahul Razdan:
Concurrent MIN-MAX simulation. 554-557 - Larry McMurchie, Craig Anderson, Gaetano Borriello:
Hybrid compiled/interpreted simulation of MOS circuits. 558-564 - Tara Weber, Fabio Somenzi:
Periodic signal suppression in a concurrent fault simulator. 565-569 - Daniel Cock, Andy Carpenter:
A proposed hardware fault simulation engine. 570-574
Layout tools
- Rafael Peset Llopis, R. J. H. Koopman, Hans G. Kerkhoff, J. A. Braat:
A performance analysis tool for performance-driven micro-cell generation. 576-580 - A. Kuehlmann, Yiannos Manoli:
Module synthesis for finite state machines. 581-585
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-15 01:15 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: