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EURO-DAC 1991: Hamburg, Germany

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Formal verification techniques

Frameworks

Logic synthesis

Fault modeling and test generation

Layout analysis

Data path synthesis

Circuit simulation and macromodelling

Partitioning for layout

Finite state machine optimisation

Test pattern generation and diagnosis

Routing

Timing verification and specification

Synthesis of testable circuits

Scheduling and allocation

Switch-level simulation

Floorplan optimization

Decompisition of finite state machines

Formal verification

System design tools

Synthesis for high-speed applications

Object oriented approaches and modelling

Analogue design and layout

Test pattern generation for combination circuits

Partitioning techniques for CAD

Technology mapping

High performance simulation techniques for digital systems

Layout tools