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Alain Greiner
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2020 – today
- 2021
- [j7]Pascal Vivet
, Eric Guthmuller
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. IEEE J. Solid State Circuits 56(1): 79-97 (2021) - 2020
- [c51]Pascal Vivet
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. ISSCC 2020: 46-48
2010 – 2019
- 2018
- [c50]Eric Guthmuller
A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches. ESSCIRC 2018: 318-321 - 2017
- [c49]Hao Liu, Quentin L. Meunier, Alain Greiner:
Decoupling Translation Lookaside Buffer Coherence from Cache Coherence. ISVLSI 2017: 92-97 - 2016
- [c48]Mohamed Lamine Karaoui, Pierre-Yves Peneau
Exploiting Large Memory Using 32-Bit Energy-Efficient Manycore Architectures. MCSoC 2016: 61-68 - 2015
- [j6]Mohamed Lamine Karaoui, Quentin L. Meunier, Franck Wajsbürt, Alain Greiner:
GECOS : Mécanisme de synchronisation passant à l'échelle à plusieurs lecteurs et un écrivain pour structures chaînées. Tech. Sci. Informatiques 34(1-2): 53-78 (2015) - [c47]Hao Liu, Clement Devigne, Lucas Garcia, Quentin L. Meunier, Franck Wajsbürt, Alain Greiner:
RWT: Suppressing Write-Through Cost When Coherence is Not Needed. ISVLSI 2015: 434-439 - 2014
- [j5]Zhen Zhang, Dimitri Refauvelet, Alain Greiner, Mounir Benabdenbi, François Pêcheux:
On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1364-1376 (2014) - 2013
- [c46]Eric Guthmuller
Architectural exploration of a fine-grained 3D cache for high performance in a manycore context. VLSI-SoC 2013: 302-307 - 2012
- [c45]Eric Guthmuller
Adaptive Stackable 3D Cache Architecture for Manycores. ISVLSI 2012: 39-44 - 2011
- [c44]Joël Porquet, Alain Greiner, Christian Schwarz:
NoC-MPU: A secure architecture for flexible co-hosting on shared memory MPSoCs. DATE 2011: 591-594 - [c43]Zhen Zhang, Dimitri Refauvelet, Alain Greiner, Mounir Benabdenbi, François Pêcheux:
Localization of damaged resources in NoC based shared-memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure. VTS 2011: 229-234 - 2010
- [c42]Aline Mello, Isaac Maia, Alain Greiner, François Pêcheux:
Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations. DATE 2010: 606-609 - [c41]Zhen Zhang, Alain Greiner, Mounir Benabdenbi:
Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components. IOLTS 2010: 194-196 - [c40]François Pêcheux, Khouloud Zine el Abidine, Alain Greiner:
Early Power Estimation in Heterogeneous Designs Using SoCLib and SystemC-AMS. PATMOS 2010: 252
2000 – 2009
- 2009
- [c39]Alain Greiner, Etienne Faure, Nicolas Pouillon, Daniela Genius:
A generic hardware / software communication middleware for streaming applications on shared memory multi processor systems-on-chip. FDL 2009: 1-4 - [c38]Joël Porquet, Christian Schwarz, Alain Greiner:
Multi-compartment: A new architecture for secure co-hosting on SoC. SoC 2009: 124-127 - [c37]Nicolas Pouillon, Alexandre Bécoulet
A Generic Instruction Set Simulator API for Timed and Untimed Simulation and Debug of MP2-SoCs. IEEE International Workshop on Rapid System Prototyping 2009: 116-122 - 2008
- [j4]Abbas Sheibanyrad, Alain Greiner, Ivan Miro Panades:
Multisynchronous and Fully Asynchronous NoCs for GALS Architectures. IEEE Des. Test Comput. 25(6): 572-580 (2008) - [j3]Abbas Sheibanyrad, Alain Greiner:
Two efficient synchronous <--> asynchronous converters well-suited for networks-on-chip in GALS architectures. Integr. 41(1): 17-26 (2008) - [c36]Zhen Zhang, Alain Greiner, Sami Taktak:
A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip. DAC 2008: 441-446 - [c35]Ivan Miro Panades, Fabien Clermidy, Pascal Vivet, Alain Greiner:
Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture. NOCS 2008: 139-148 - 2007
- [j2]Hervé Charlery, Adrijean Andriahantenaina, Alain Greiner:
Physical design of the VCI wrappers for the on-chip packet-switched network named SPIN. Comput. Electr. Eng. 33(4): 299-309 (2007) - [c34]Abbas Sheibanyrad, Alain Greiner:
Hybrid-Timing FIFOs to Use on Networks-on-Chip in GALS Architectures. ESA 2007: 27-33 - [c33]Abbas Sheibanyrad, Ivan Miro Panades, Alain Greiner:
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture. DATE 2007: 1090-1095 - [c32]Ivan Miro Panades, Alain Greiner:
Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures. NOCS 2007: 83-94 - [c31]Matthieu Tuna, Mounir Benabdenbi, Alain Greiner:
At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester. VTS 2007: 447-454 - 2006
- [c30]Rabie Ben Atitallah, Smaïl Niar, Alain Greiner, Samy Meftali, Jean-Luc Dekeyser:
Estimating Energy Consumption for an MPSoC Architectural Exploration. ARCS 2006: 298-310 - [c29]Emmanuel Viaud, François Pêcheux, Alain Greiner:
An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles. DATE 2006: 94-99 - [c28]Frédéric Pétrot, Alain Greiner, Pascal Gomez:
On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures. DSD 2006: 53-60 - [c27]Ivan Miro Panades, Alain Greiner, Abbas Sheibanyrad:
A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach. Nano-Net 2006: 1-5 - [c26]Abbas Sheibanyrad, Alain Greiner:
Two Efficient Synchronous Û Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures. PATMOS 2006: 191-202 - [c25]Alain Greiner, Frédéric Pétrot, M. Carrier, Mounir Benabdenbi, Roselyne Chotin-Avot, Raphaël Labayrade:
MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation. ReCoSoC 2006: 24-30 - [c24]Etienne Faure, Alain Greiner, Daniela Genius:
A generic hardware/software communication mechanism for Multi-Processor System on Chip, Targeting Telecommunication Applications. ReCoSoC 2006: 237-242 - 2004
- [c23]Mounir Benabdenbi, Alain Greiner, François Pêcheux, Emmanuel Viaud, Matthieu Tuna:
STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores. DATE 2004: 712-713 - [c22]Marie-Minerve Louërat, Tuong P. Nguyen, Vincent Bourguet, Laurent de Lamarre, Alain Greiner:
A language to desing generators of analog functions (poster). FDL 2004: 30-32 - 2003
- [c21]Adrijean Andriahantenaina, Alain Greiner:
Micro-Network for SoC: Implementation of a 32-Port SPIN network. DATE 2003: 11128-11129 - [c20]Adrijean Andriahantenaina, Hervé Charlery, Alain Greiner, Laurent Mortiez, César Albenes Zeferino:
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network. DATE 2003: 20070-20073 - 2001
- [c19]Mohamed Dessouky, Andreas Kaiser
Analog design for reuse - case study: very low-voltage sigma-delta modulator. DATE 2001: 353-360 - [c18]Jean Lou Desbarbieux, Olivier Glück, Amal Zerrouki, Alexandre Fenyo, Alain Greiner, Franck Wajsbürt, Cyril Spasevski, Fabrício Silva
Protocol and Performance Analysis of the MPC Parallel Computer. IPDPS 2001: 52 - 2000
- [c17]Pierre Guerrier, Alain Greiner:
A Generic Architecture for On-Chip Packet-Switched Interconnections. DATE 2000: 250-256
1990 – 1999
- 1997
- [c16]Frédéric Pétrot, Denis Hommais, Alain Greiner:
A Simulation Environment for Core Based Embedded Systems. Annual Simulation Symposium 1997: 86-91 - [c15]Frédéric Pétrot, Denis Hommais, Alain Greiner:
Cycle precise core based hardware/software system simulation with predictable event propagation. EUROMICRO 1997: 182-187 - 1996
- [j1]Michel Combes, Karim Dioury, Alain Greiner:
A portable clock multiplier generator using digital CMOS standard cells. IEEE J. Solid State Circuits 31(7): 958-965 (1996) - 1995
- [c14]Marcello Duhalde, Alain Greiner, Frédéric Pétrot:
A High Performance Modular Embedded ROM Architecture. ISCAS 1995: 1057-1060 - 1994
- [c13]Mokhtar Hirech, Olivier Florent, Alain Greiner, El Housseine Rejouan:
Application of a redefinable symbolic simulation technique in VLSI testability design rules checking. Annual Simulation Symposium 1994: 255-261 - [c12]Alain Greiner, Luis Lucas, Franck Wajsbürt, Laurent Winckel:
Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC Library. EDAC-ETC-EUROASIC 1994: 9-13 - [c11]Luc Burgun, N. Dictus, Alain Greiner, E. Prado Lopes, C. Sarwary:
Multilevel logic optimization of very high complexity circuits. EURO-DAC 1994: 14-19 - [c10]Mokhtar Hirech, Olivier Florent, Alain Greiner, El Housseine Rejouan:
A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking. EDAC-ETC-EUROASIC 1994: 668 - [c9]Luc Burgun, N. Dictus, Alain Greiner, E. Pradho, C. Sarwary:
Multilevel Logic Synthesis of Very High Complexity Circuits. EDAC-ETC-EUROASIC 1994: 669 - [c8]Alain Greiner, Frédéric Pétrot:
Using C to write portable CMOS VLSI module generators. EURO-DAC 1994: 676-681 - [c7]Denis Archambaud, Pascal Faudemay, Alain Greiner:
RAPID-2, An Object-Oriented Associative Memory Applicable to Genome Data Processing. HICSS (5) 1994: 150-159 - [c6]Mokhtar Hirech, Olivier Florent, Alain Greiner, El Housseine Rejouan:
A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking. ISCAS 1994: 89-92 - 1992
- [c5]Marc Laurentin, Alain Greiner, Roland Marbot:
DESB, a functional abstractor for CMOS VLSI circuits. EURO-DAC 1992: 22-27 - [c4]Lotfi Ben Ammar, Alain Greiner:
FITPATH: A Process-Independent Datapath Compiler Providing High Density Layout. Synthesis for Control Dominated Circuits 1992: 133-151 - 1991
- [c3]Amjad Hajjar, Alain Greiner, Roland Marbot, Payam Kiani:
TAS: an accurate timing analyser for CMOS VLSI. EURO-DAC 1991: 261-265 - [c2]A. Compan, Alain Greiner, François Pêcheux, Frédéric Pétrot:
GENVIEW: a portable source-level debugger for macrocell generators. EURO-DAC 1991: 408-412
1980 – 1989
- 1988
- [c1]F. Gourdy, Alain Greiner, M. Guillemet, Roland Marbot, J. Murzin:
NOISY: an electrical noise checker for ULSI. ICCAD 1988: 226-229
Coauthor Index
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