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3rd NOCS 2009: La Jolla, CA, USA
- Third International Symposium on Networks-on-Chips, NOCS 2009, May 10-13 2009, La Jolla, CA, USA. Proceedings. IEEE Computer Society 2009, ISBN 978-1-4244-4142-6
Keynote
- Ivo Bolsens:
NoCs: It is about the memory and the programming model. 1
Routing
- Rickard Holsmark, Shashi Kumar, Maurizio Palesi, Andres Mejia:
HiRA: A methodology for deadlock free routing in hierarchical networks on chip. 2-11 - Yury Markovsky, Yatish Patel, John Wawrzynek:
Using adaptive routing to compensate for performance heterogeneity. 12-21 - Adán Kohler, Martin Radetzki:
Fault-tolerant architecture and deflection routing for degradable NoC switches. 22-31 - Wei Song
, Doug A. Edwards, José Luis Núñez-Yáñez, Sohini Dasgupta:
Adaptive stochastic routing in fault-tolerant on-chip networks. 32-37 - Keun Sup Shim, Myong Hyon Cho, Michel A. Kinsy, Tina Wen, Mieszko Lis, G. Edward Suh
Static virtual channel allocation in oblivious routing. 38-43
Performance and Energy
- Yue Qian, Zhonghai Lu, Wenhua Dou:
Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip. 44-53 - Bo Fu, David Wolpert, Paul Ampadu:
Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links. 54-63 - Lei Wang, Yuho Jin, Hyungjun Kim, Eun Jung Kim:
Recursive partitioning multicast: A bandwidth-efficient routing for Networks-on-Chip. 64-73 - Mohamed Bakhouya
Analytical modeling and evaluation of On-Chip Interconnects using Network Calculus. 74-79 - Pavel Ghosh, Arunabha Sen, Alexander Hall:
Energy efficient application mapping to NoC processing elements operating at multiple voltage levels. 80-85
Poster Session
- Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny:
The design of a latency constrained, power optimized NoC for a 4G SoC. 86 - Henrique C. Freitas
Performance Evaluation of NoC Architectures for Parallel Workloads. 87 - Evgeni Krimer, Mattan Erez, Isaac Keslassy
Packet-level static timing analysis for NoCs. 88 - Guilherme Montez Guindani, Cezar Reinbrecht, Thiago R. da Rosa, Fernando Moraes
Increasing NoC power estimation accuracy through a rate-based model. 89 - Avinash Karanth Kodi, Randy Morris, Ahmed Louri, Xiang Zhang:
On-Chip photonic interconnects for scalable multi-core architectures. 90 - Ajay Joshi, Fred Chen, Vladimir Stojanovic
A Modeling and exploration framework for interconnect network design in the nanometer era. 91 - Daniel Gebhardt, Kenneth S. Stevens:
Power reduction through physical placement of asynchronous routers. 92
Networks-on-Chip in Emerging Interconnect Paradigms: Advantages And Challenges
- Luca P. Carloni, Partha Pande, Yuan Xie:
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges. 93-102
Keynote
- Andrew A. Chien:
NoC's at the center of chip architecture: Urgent needs (today) and what they must become (future). 103
3D and Optical Networks
- Gilbert Hendry, Shoaib Kamil, Aleksandr Biberman, Johnnie Chan, Benjamin G. Lee, Marghoob Mohiyuddin, Ankit Jain, Keren Bergman, Luca P. Carloni, John Kubiatowicz, Leonid Oliker, John Shalf
Analysis of photonic networks for a chip multiprocessor using scientific applications. 104-113 - Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa
Scalability of network-on-chip communication architecture for 3-D meshes. 114-123 - Ajay Joshi, Christopher Batten
Silicon-photonic clos networks for global on-chip communication. 124-133 - Somayyeh Koohi, Shaahin Hessabi:
Contention-free on-chip routing of optical packets. 134-143
Network Architecture
- Robin Emery, Alexandre Yakovlev
Connection-centric network for spiking neural networks. 144-152 - Fabien Clermidy, Romain Lemaire, Yvain Thonnart
A Communication and configuration controller for NoC based reconfigurable data flow architecture. 153-162 - Martti Forsell:
Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions. 163-172 - Ran Manevich, Isask'har Walter, Israel Cidon, Avinoam Kolodny:
Best of both worlds: A bus enhanced NoC (BENoC). 173-182
Flow Oriented Techniques
- Arnab Banerjee, Simon W. Moore
Flow-aware allocation for on-chip networks. 183-192 - Nicola Concer, Luciano Bononi, Michael Soulie, Riccardo Locatelli, Luca P. Carloni:
CTC: An end-to-end flow control protocol for multi-core systems-on-chip. 193-202 - Mehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol:
Performance and power efficient on-chip communication using adaptive virtual point-to-point connections. 203-212
Keynote
- Anant Agarwal:
Keynote 3 (Banquet Talk) Digital space. 213
Synchronization and Flow Control
- Anh Thien Tran, Dean Truong, Bevan M. Baas:
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network. 214-223 - Tarik Ono-Tesfaye, Mark R. Greenstreet:
A modular synchronizing FIFO for NoCs. 224-233 - Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet:
Estimating reliability and throughput of source-synchronous wave-pipelined interconnect. 234-243 - Daniele Ludovici, Alessandro Strano, Davide Bertozzi, Luca Benini
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture. 244-249 - Young Hoon Kang, Taek-Jun Kwon, Jeff Draper:
Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers. 250-255
Links and Channels
- Marcos Hervé, Érika F. Cota, Fernanda Lima Kastensmidt
Diagnosis of interconnect shorts in mesh NoCs. 256-265 - Ying-Cherng Lan, Shih-Hsin Lo, Yueh-Chi Lin, Yu Hen Hu, Sao-Jie Chen
BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel. 266-275 - Prabhat Kumar, Yan Pan, John Kim
Exploring concentration and channel slicing in on-chip network router. 276-285 - Author index. 286-287
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