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Cezar Reinbrecht
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2020 – today
- 2024
- [j7]Tara Ghasempouri
, Jaan Raik
Survey on Architectural Attacks: A Unified Classification and Attack Model. ACM Comput. Surv. 56(2): 42:1-42:32 (2024) - 2023
- [j6]Troya Çagil Köylü
A Survey on Machine Learning in Hardware Security. ACM J. Emerg. Technol. Comput. Syst. 19(2): 18:1-18:37 (2023) - [c33]Abdullah Aljuffri, Mudit Saxena, Cezar Reinbrecht
A Pre-Silicon Power Leakage Assessment Based on Generative Adversarial Networks. DSD 2023: 87-94 - 2022
- [j5]Troya Çagil Köylü, Cezar Rodolfo Wedig Reinbrecht
Instruction flow-based detectors against fault injection attacks. Microprocess. Microsystems 94: 104638 (2022) - [c32]Troya Çagil Köylü, Luíza C. Garaffa, Cezar Reinbrecht
Exploiting PUF Variation to Detect Fault Injection Attacks. DDECS 2022: 74-79 - [i1]Tara Ghasempouri
Survey on Architectural Attacks: A Unified Classification and Attack Model. CoRR abs/2208.14194 (2022) - 2021
- [j4]Abdullah Aljuffri
Applying Thermal Side-Channel Attacks on Asymmetric Cryptography. IEEE Trans. Very Large Scale Integr. Syst. 29(11): 1930-1942 (2021) - [c31]Cezar Reinbrecht
GRINCH: A Cache Attack against GIFT Lightweight Cipher. DATE 2021: 549-554 - [c30]Troya Çagil Köylü, Hans Okkerman, Cezar Rodolfo Wedig Reinbrecht
Protecting IoT Devices through a Hardware-driven Memory Verification. DSD 2021: 115-122 - [c29]Luíza C. Garaffa, Abdullah Aljuffri, Cezar Reinbrecht
Revealing the Secrets of Spiking Neural Networks: The Case of Izhikevich Neuron. DSD 2021: 514-518 - [c28]Abdullah Aljuffri, Cezar Reinbrecht
Impact of Data Pre-Processing Techniques on Deep Learning Based Power Attacks. DTIS 2021: 1-6 - [c27]Mottaqiallah Taouil, Cezar Reinbrecht
LightRoAD: Lightweight Rowhammer Attack Detector. ISVLSI 2021: 362-367 - [c26]Troya Çagil Köylü, Cezar Rodolfo Wedig Reinbrecht
Deterministic and Statistical Strategies to Protect ANNs against Fault Injection Attacks. PST 2021: 1-10 - [c25]Abdullah Aljuffri, Cezar Reinbrecht
Multi-Bit Blinding: A Countermeasure for RSA Against Side Channel Attacks. VTS 2021: 1-6 - 2020
- [c24]Tara Ghasempouri
A Security Verification Template to Assess Cache Architecture Vulnerabilities. DDECS 2020: 1-6 - [c23]Bruno Forlin, Ronaldo Husemann, Luigi Carro, Cezar Reinbrecht
G-PUF: An Intrinsic PUF Based on GPU Error Signatures. ETS 2020: 1-2 - [c22]Cezar Reinbrecht
LiD-CAT: A Lightweight Detector for Cache ATtacks. ETS 2020: 1-6 - [c21]Troya Çagil Köylü, Cezar Rodolfo Wedig Reinbrecht
RNN-Based Detection of Fault Attacks on RSA. ISCAS 2020: 1-5 - [c20]Cezar Reinbrecht
Guard-NoC: A Protection Against Side-Channel Attacks for MPSoCs. ISVLSI 2020: 536-541 - [c19]Abdullah Aljuffri, Pradeep Venkatachalam, Cezar Reinbrecht
S-NET: A Confusion Based Countermeasure Against Power Attacks for SBOX. SAMOS 2020: 295-307
2010 – 2019
- 2019
- [j3]Cezar Reinbrecht, Bruno Forlin, Johanna Sepúlveda:
Cache timing attacks on NoC-based MPSoCs. Microprocess. Microsystems 66: 1-9 (2019) - [j2]Leandro Soares Indrusiak
Side-channel protected MPSoC through secure real-time networks-on-chip. Microprocess. Microsystems 68: 34-46 (2019) - [c18]Tim Fritzmann, Uzair Sharif, Daniel Müller-Gritschneder
Towards Reliable and Secure Post-Quantum Co-Processors based on RISC-V. DATE 2019: 1148-1153 - [c17]Bruno Forlin, Cezar Reinbrecht, Johanna Sepúlveda:
Attacking Real-time MPSoCs: Preemptive NoCs are Vulnerable. VLSI-SoC 2019: 204-209 - [c16]Bruno Forlin, Cezar Reinbrecht, Johanna Sepúlveda:
Security Aspects of Real-Time MPSoCs: The Flaws and Opportunities of Preemptive NoCs. VLSI-SoC (Selected Papers) 2019: 209-233 - 2018
- [c15]Cezar Reinbrecht, Bruno Forlin, Andreas Zankl
Earthquake - A NoC-based optimized differential cache-collision attack for MPSoCs. DATE 2018: 648-653 - [c14]Johanna Sepúlveda, Cezar Reinbrecht, Jean-Philippe Diguet:
Security aspects of neuromorphic MPSoCs. ICCAD 2018: 45 - [c13]Johanna Sepúlveda, Cezar Reinbrecht
Understanding MPSoCs: exploiting memory microarchitectural vulnerabilities of high performance NoC-based MPSoCs. SAMOS 2018: 162-166 - 2017
- [j1]Cezar Reinbrecht
Timing attack on NoC-based systems: Prime+Probe attack and NoC-based protection. Microprocess. Microsystems 52: 556-565 (2017) - 2016
- [c12]Priscila C. Holanda, Cezar R. W. Reinbrecht, Guilherme Bontorin, Vitor V. Bandeira
DHyANA: A NoC-based neural network hardware architecture. ICECS 2016: 177-180 - [c11]Cezar Reinbrecht, Altamiro Amadeu Susin, Lilian Bossuet, Johanna Sepúlveda:
Gossip NoC - Avoiding Timing Side-Channel Attacks through Traffic Management. ISVLSI 2016: 601-606 - [c10]Cezar Reinbrecht, Altamiro Amadeu Susin, Lilian Bossuet, Georg Sigl, Martha Johanna Sepúlveda:
Side channel attack on NoC-based MPSoCs are practical: NoC Prime+Probe attack. SBCCI 2016: 1-6 - 2015
- [c9]Cezar R. W. Reinbrecht, Martha Johanna Sepúlveda, Altamiro Amadeu Susin:
PHiCIT: Improving Hierarchical Networks-on-chip through 3D Silicon Photonics Integration. SBCCI 2015: 28:1-28:7 - 2014
- [c8]Debora Matos, Márcio Eduardo Kreutz, Cezar Reinbrecht, Luigi Carro, Altamiro Amadeu Susin:
Adaptive multiple switching strategy toward an ideal NoC. ISCAS 2014: 1014-1017 - 2013
- [c7]Debora Matos, Cezar Reinbrecht, Márcio Eduardo Kreutz, Gianluca Palermo
Hierarchical and Multiple Switching NoC with Floorplan Based Adaptability. ARC 2013: 179-184 - [c6]Debora Matos, Cezar Reinbrecht, Tiago Motta, Altamiro Amadeu Susin:
A power-efficient hierarchical network-on-chip topology for stacked 3D ICs. VLSI-SoC 2013: 308-313 - 2012
- [c5]Debora Matos, Cezar Reinbrecht, Gianluca Palermo
Floorplan-aware hierarchical NoC topology with GALS interfaces. ISCAS 2012: 652-655 - 2011
- [c4]Debora Matos, Gianluca Palermo
Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip. NoCArc@MICRO 2011: 31-36
2000 – 2009
- 2009
- [c3]Guilherme Montez Guindani, Cezar Reinbrecht, Thiago R. da Rosa, Fernando Moraes
Increasing NoC power estimation accuracy through a rate-based model. NOCS 2009: 89 - [c2]Luciano Ost
A high abstraction, high accuracy power estimation model for networks-on-chip. SBCCI 2009 - 2008
- [c1]Guilherme Montez Guindani, Cezar Reinbrecht, Thiago Raupp da Rosa, Ney Calazans
NoC Power Estimation at the RTL Abstraction Level. ISVLSI 2008: 475-478
Coauthor Index
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last updated on 2024-08-22 19:46 CEST by the dblp team
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