default search action
Dinesh Pamunuwa
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
- [c30]Elliott Worsey, Qi Tang, Manu Bala Krishnan, Mukesh Kumar Kulsreshath, Dinesh Pamunuwa
:
Nanoelectromechanical analog-to-digital converter for low power and harsh environments. ISCAS 2024: 1-5
2010 – 2019
- 2018
- [j8]Tian Qin, Simon J. Bleiker, Sunil Rana
Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays. IEEE Access 6: 15997-16009 (2018) - 2015
- [j7]Awet Yemane Weldezion, Matt Grange, Axel Jantsch
Zero-load predictive model for performance analysis in deflection routing NoCs. Microprocess. Microsystems 39(8): 634-647 (2015) - [c29]Tian Qin, Sunil Rana
Design Methodologies, Models and Tools for Very-Large-Scale Integration of NEM Relay-Based Circuits. ICCAD 2015: 641-648 - 2014
- [j6]Sunil Rana
Energy and Latency Optimization in NEM Relay-Based Digital Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2348-2359 (2014) - 2013
- [c28]Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa
A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns. 3DIC 2013: 1-5 - [c27]Sunil Rana
Modelling NEM relays for digital circuit applications. ISCAS 2013: 805-808 - 2011
- [c26]Matthew Grange, Axel Jantsch
Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning. ICCAD 2011: 310-317 - [c25]Matt Grange, Roshan Weerasekera
Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks. NOCS 2011: 57-64 - [c24]Dinesh Pamunuwa
3-D integration and the limits of silicon computation. VLSI-SoC 2011: 343-348 - [p1]Axel Jantsch, Matthew Grange, Dinesh Pamunuwa
The Promises and Limitations of 3-D Integration. 3D Integration for NoC-based SoC Architectures 2011: 27-44 - 2010
- [c23]Roshan Weerasekera
On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits. DATE 2010: 1325-1328
2000 – 2009
- 2009
- [j5]Roshan Weerasekera
Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(8): 1237-1250 (2009) - [c22]Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa
Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh. 3DIC 2009: 1-7 - [c21]Roshan Weerasekera
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits. 3DIC 2009: 1-8 - [c20]Ci Lei, Dinesh Pamunuwa
Design of Robust Molecular Electronic Circuits. ISCAS 2009: 1819-1822 - [c19]Ci Lei, Dinesh Pamunuwa
Designing Reliable Digital Molecular Electronic Circuits. NanoNet 2009: 111-115 - [c18]Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa
Scalability of network-on-chip communication architecture for 3-D meshes. NOCS 2009: 114-123 - 2008
- [j4]Roshan Weerasekera
Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime. IEEE Trans. Very Large Scale Integr. Syst. 16(5): 589-593 (2008) - [c17]Dinesh Pamunuwa
Memory Technology for Extended Large-Scale Integration in Future Electronics Applications. DATE 2008: 1126-1127 - [c16]Ci Lei, Dinesh Pamunuwa
Application of Molecular Electronics Devices in Digital Circuit Design. NanoNet 2008: 61-65 - 2007
- [c15]Roshan Weerasekera
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. ICCAD 2007: 212-219 - [c14]Roshan Weerasekera
Early selection of system implementation choice among SoC, SoP and 3-D Integration. SoCC 2007: 187-190 - [c13]Roshan Weerasekera
Delay-Balanced Smart Repeaters for On-Chip Global Signaling. VLSI Design 2007: 308-313 - 2006
- [c12]Roshan Weerasekera
Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. SLIP 2006: 113-120 - 2005
- [j3]Dinesh Pamunuwa
Modeling delay and noise in arbitrarily coupled RC trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11): 1725-1739 (2005) - [c11]Roshan Weerasekera
Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses. PATMOS 2005: 277-285 - 2004
- [j2]Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch, Hannu Tenhunen:
A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. Integr. 38(1): 3-17 (2004) - [c10]Roshan Weerasekera
Crosstalk immune interconnect driver design. SoC 2004: 139-142 - 2003
- [j1]Dinesh Pamunuwa
Maximizing throughput over parallel wire structures in the deep submicrometer regime. IEEE Trans. Very Large Scale Integr. Syst. 11(2): 224-243 (2003) - [c9]Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen:
Analytic Modeling of Interconnects for Deep Sub-Micron Circuits. ICCAD 2003: 835-842 - [c8]Dinesh Pamunuwa
Closed form metrics to accurately model the response in general arbitrarily-coupled RC trees. ISCAS (4) 2003: 604-607 - [c7]Jian Liu, Li-Rong Zheng, Dinesh Pamunuwa
A global wire planning scheme for Network-on-Chip. ISCAS (4) 2003: 892-895 - [c6]Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch:
Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures. VLSI-SOC 2003: 362- - 2002
- [c5]Hannu Tenhunen, Dinesh Pamunuwa
On dynamic delay and repeater insertion. ISCAS (1) 2002: 97-100 - [c4]Dinesh Pamunuwa
Optimising bandwidth over deep sub-micron interconnect. ISCAS (4) 2002: 193-196 - [c3]Dinesh Pamunuwa
On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects. ISQED 2002: 240-245 - 2001
- [c2]Dinesh Pamunuwa
Repeater Insertion To Minimise Delay In Coupled Interconnects. VLSI Design 2001: 513-517 - 2000
- [c1]Dinesh Pamunuwa
Combating digital noise in high speed ULSI circuits using binary BCH encoding. ISCAS 2000: 13-16
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-08-05 20:13 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: