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A critical path delay check system

Published: 29 June 1981 Publication History

Abstract

A Critical Path Delay Check System for designing computers is described. It calculates the critical path delay between the start and end points. It can be used in the early stage of design when, for example, the location of the components on a plug-in card has not yet been determined. Some algorithms for predicting delays are also introduced.

References

[1]
Wold, M. A., "Design Verification and Performance Analysis", 1978 Design Automation Conference Proceedings, pp 264-270.
[2]
Y. Ohno et al., "Logic Verification System for Very Large Computers using LSI's" 1979 Design Automation Conference Proceedings, pp 367-374.

Cited By

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  • (1991)Timing- and constraint-oriented placement for interconnected LSIs in mainframe designProceedings of the 28th ACM/IEEE Design Automation Conference10.1145/127601.127676(253-258)Online publication date: 1-Jun-1991
  • (1988)Timing verification and the timing analysis programPapers on Twenty-five years of electronic design automation10.1145/62882.62936(446-456)Online publication date: 1-Jun-1988
  • (1986)An effective delay analysis system for a large scale computer designProceedings of the 23rd ACM/IEEE Design Automation Conference10.5555/318013.318077(398-403)Online publication date: 2-Jul-1986
  • Show More Cited By

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cover image ACM Conferences
DAC '81: Proceedings of the 18th Design Automation Conference
June 1981
899 pages

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IEEE Press

Publication History

Published: 29 June 1981

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all
  • (1991)Timing- and constraint-oriented placement for interconnected LSIs in mainframe designProceedings of the 28th ACM/IEEE Design Automation Conference10.1145/127601.127676(253-258)Online publication date: 1-Jun-1991
  • (1988)Timing verification and the timing analysis programPapers on Twenty-five years of electronic design automation10.1145/62882.62936(446-456)Online publication date: 1-Jun-1988
  • (1986)An effective delay analysis system for a large scale computer designProceedings of the 23rd ACM/IEEE Design Automation Conference10.5555/318013.318077(398-403)Online publication date: 2-Jul-1986
  • (1985)ACTASProceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.317849(152-158)Online publication date: 1-Jun-1985
  • (1983)Path delay analysis for hierarchical building block layout systemProceedings of the 20th Design Automation Conference10.5555/800032.800699(403-410)Online publication date: 27-Jun-1983
  • (1982)Synchronous path analysis in MOS circuit simulatorProceedings of the 19th Design Automation Conference10.5555/800263.809268(629-635)Online publication date: 1-Jan-1982
  • (1982)Timing verification system based on delay time hierarchical natureProceedings of the 19th Design Automation Conference10.5555/800263.809267(622-628)Online publication date: 1-Jan-1982
  • (1982)Developments in logic network path delay analysisProceedings of the 19th Design Automation Conference10.5555/800263.809265(605-615)Online publication date: 1-Jan-1982
  • (1982)Timing Verification and the Timing Analysis programProceedings of the 19th Design Automation Conference10.5555/800263.809264(594-604)Online publication date: 1-Jan-1982

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