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research-article

Path selection for transition path delay faults

Authors:

Irith Pomeranz,

Sudhakar M. ReddyAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 18, Issue 3

Pages 401 - 409

https://doi.org/10.1109/TVLSI.2008.2011913

Published: 01 March 2010 Publication History

Abstract

We propose a path selection criterion to improve the coverage of small delay defects. Under this criterion, every line in the circuit is covered by one of the longest testable paths or subpaths that goes through it. Earlier criteria that considered only complete paths (from inputs to outputs) did not use longest testable subpaths, which may be longer than the longest complete testable paths. Earlier criteria that considered subpaths considered only subpaths of longest paths. We apply the proposed criterion to a delay fault model called the transition path delay fault model. This model was introduced to capture both small and large delay defects. We present experimental results to demonstrate that consideration of subpaths improves the circuit coverage relative to the case where only complete paths are allowed

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Cited By

Pomeranz I(2018)Computing two-pattern test cubes for transition path delay faultsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218872721:3(475-485)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2012.2188727
Liu TZhou YLiu YCai S(2018)Harzard-Based ATPG for Improving Delay Test QualityJournal of Electronic Testing: Theory and Applications10.1007/s10836-014-5503-331:1(27-34)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1007/s10836-014-5503-3

Path selection for transition path delay faults
1. Hardware

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Information & Contributors

Information

Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 18, Issue 3

March 2010

170 pages

ISSN:1063-8210

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Copyright © 2010.

Publisher

IEEE Educational Activities Department

United States

Publication History

Published: 01 March 2010

Revised: 16 December 2008

Received: 31 August 2008

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Cited By

Pomeranz I(2018)Computing two-pattern test cubes for transition path delay faultsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218872721:3(475-485)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2012.2188727
Liu TZhou YLiu YCai S(2018)Harzard-Based ATPG for Improving Delay Test QualityJournal of Electronic Testing: Theory and Applications10.1007/s10836-014-5503-331:1(27-34)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1007/s10836-014-5503-3

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