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Exploiting Resonant Behavior to Reduce Inductive Noise

Authors:

Michael D. Powell,

T. N. VijaykumarAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 32, Issue 2

Page 288

https://doi.org/10.1145/1028176.1006726

Published: 02 March 2004 Publication History

Abstract

Inductive noise in high-performance microprocessors is a reliabilityissue caused by variations in processor current (di/dt)which are converted to supply-voltage glitches by impedances inthe power-supply network. Inductive noise has been addressed byusing decoupling capacitors to maintain low impedance in thepower supply over a wide range of frequencies. However, evenwell-designed power supplies exhibit (a few) peaks of high impedanceat resonant frequencies caused by RLC resonant loops. Previousarchitectural proposals adjust current variations bycontrolling instruction fetch and issue, trading off performanceand energy for noise reduction. However, the proposals do notconsider some conceptual issues and have implementation challenges.The issues include requiring fast response, responding tovariations that do not threaten the noise margins, or respondingto variations only at the resonant frequency while the range ofhigh impedance extends to a resonance band around the resonantfrequency. While previous schemes reduce the magnitude of variations,our proposal, called resonance tuning, changes the frequencyof current variations away from the resonance band to anon-resonant frequency to be absorbed by the power supply.Because inductive noise is a resonance problem, resonance tuningreacts only to repeated variations in the resonance band, andnot to isolated variations. Reacting after a few repetitions allowsmore time for the response and reduces unnecessary responses,decreasing performance and energy loss.

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Cited By

Zhang RWang KMeyer BStan MSkadron K(2014)Architecture implications of pads as a scarce resourceACM SIGARCH Computer Architecture News10.1145/2678373.266572842:3(373-384)Online publication date: 14-Jun-2014
https://dl.acm.org/doi/10.1145/2678373.2665728
Reddi VGupta M(2013)Resilient Architecture Design for Voltage VariationSynthesis Lectures on Computer Architecture10.2200/S00486ED1V01Y201303CAC0228:2(1-138)Online publication date: 29-May-2013
https://doi.org/10.2200/S00486ED1V01Y201303CAC022
Liu WWang YWang XXu JYang H(2013)On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on ChipIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2012.19324:4(767-777)Online publication date: 1-Apr-2013
https://dl.acm.org/doi/10.1109/TPDS.2012.193
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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 32, Issue 2

ISCA 2004

March 2004

373 pages

ISSN:0163-5964

DOI:10.1145/1028176

Issue’s Table of Contents

ISCA '04: Proceedings of the 31st annual international symposium on Computer architecture
June 2004
373 pages
ISBN:0769521436

Copyright © 2004 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 March 2004

Published in SIGARCH Volume 32, Issue 2

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Cited By

Zhang RWang KMeyer BStan MSkadron K(2014)Architecture implications of pads as a scarce resourceACM SIGARCH Computer Architecture News10.1145/2678373.266572842:3(373-384)Online publication date: 14-Jun-2014
https://dl.acm.org/doi/10.1145/2678373.2665728
Reddi VGupta M(2013)Resilient Architecture Design for Voltage VariationSynthesis Lectures on Computer Architecture10.2200/S00486ED1V01Y201303CAC0228:2(1-138)Online publication date: 29-May-2013
https://doi.org/10.2200/S00486ED1V01Y201303CAC022
Liu WWang YWang XXu JYang H(2013)On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on ChipIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2012.19324:4(767-777)Online publication date: 1-Apr-2013
https://dl.acm.org/doi/10.1109/TPDS.2012.193
Kim YJohn LPant SManne SSchulte MBircher WGovindan M(2013)Automating Stressmark Generation for Testing Processor Voltage FluctuationsIEEE Micro10.1109/MM.2013.7033:4(66-75)Online publication date: 1-Jul-2013
https://dl.acm.org/doi/10.1109/MM.2013.70
Gupta MBose P(2010)Variation-Tolerant Microprocessor Architecture at Low PowerLow-Power Variation-Tolerant Design in Nanometer Silicon10.1007/978-1-4419-7418-1_7(211-247)Online publication date: 25-Oct-2010
https://doi.org/10.1007/978-1-4419-7418-1_7
Hadjilambrou ZDas SAntoniades MSazeides YOskin MInoue K(2018)Leveraging CPU electromagnetic emanations for voltage noise characterizationProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00053(573-585)Online publication date: 20-Oct-2018
https://dl.acm.org/doi/10.1109/MICRO.2018.00053
Zhang RWang KMeyer BStan MSkadron KYew PZhai AKeckler S(2014)Architecture implications of pads as a scarce resourceProceeding of the 41st annual international symposium on Computer architecuture10.5555/2665671.2665728(373-384)Online publication date: 14-Jun-2014
https://dl.acm.org/doi/10.5555/2665671.2665728
Zhang RWang KMeyer BStan MSkadron K(2014)Architecture implications of pads as a scarce resourceACM SIGARCH Computer Architecture News10.1145/2678373.266572842:3(373-384)Online publication date: 14-Jun-2014
https://dl.acm.org/doi/10.1145/2678373.2665728
Bertran RBuyuktosunoglu ABose PSlegel TSalem GCarey SRizzolo RStrach TFlautner KWenisch TOzer EFerdman M(2014)Voltage Noise in Multi-Core ProcessorsProceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2014.12(368-380)Online publication date: 13-Dec-2014
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Wang TZhang CXiong JShi YHenkel J(2013)Eagle-eyeProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561915(437-443)Online publication date: 18-Nov-2013
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