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Power considerations in the design of the Alpha 21264 microprocessor

Authors:

Michael K. Gowan,

Larry L. Biro,

Daniel B. JacksonAuthors Info & Claims

DAC '98: Proceedings of the 35th annual Design Automation Conference

Pages 726 - 731

https://doi.org/10.1145/277044.277226

Published: 01 May 1998 Publication History

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Abstract

Power dissipation is rapidly becoming a limiting factor in high performance microprocessor design due to ever increasing device counts and clock rates. The 21264 is a third generation Alpha microprocessor implementation, containing 15.2 million transistors and operating at 600 MHz. This paper describes some of the techniques the Alpha design team utilized to help manage power dissipation. In addition, the electrical design of the power, ground, and clock networks is presented.

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Benschneider, B., et al., "A 300-MHz 64b Quad-Issue CMOS RISC Microprocessor," IEEE Journal of Solid State Circuits, vol. 30, no. 11, Nov., 1995.

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Gieseke, B., et al., "A 600 MHz Superscaler RISC Microprocessor With Out-of-Order Execution," ISSCC Digest of Technical Papers, pp. 222-223, Feb., 1996.

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Fair, H. and Bailey, D., "Clocking Design and Analysis for a 600 MHz Alpha Microprocessor," ISSCC Digest of Technical Papers, pp. 398-399, Feb., 1998.

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Cho MGill BSharma RGupta S(2024)Adaptive Clock Gating for Improving Wear out induced Duty Cycle Shift in the Clock Network2024 IEEE International Reliability Physics Symposium (IRPS)10.1109/IRPS48228.2024.10529398(1-4)Online publication date: 14-Apr-2024
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Power considerations in the design of the Alpha 21264 microprocessor

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Published In

DAC '98: Proceedings of the 35th annual Design Automation Conference

May 1998

820 pages

ISBN:0897919645

DOI:10.1145/277044

Chairmen:
Basant R. Chawla
Lucent Technologies, Warren, NJ
,
Randal E. Bryant
Carnegie Mellon Univ., Pittsburgh, PA
,
Jan M. Rabaey
Univ. of California, Berkeley
,
Editor:
M. J. Irwin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1998

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DAC98: The 35th ACM/IEEE-CAS/EDAC Design Automation Conference

June 15 - 19, 1998

California, San Francisco, USA

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Cho MGill BSharma RGupta S(2024)Adaptive Clock Gating for Improving Wear out induced Duty Cycle Shift in the Clock Network2024 IEEE International Reliability Physics Symposium (IRPS)10.1109/IRPS48228.2024.10529398(1-4)Online publication date: 14-Apr-2024
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