WO2024212975A1

WO2024212975A1 - Single chip manufacturing method, multi-chip integration method, chip structure, and chip

Info

Publication number: WO2024212975A1
Application number: PCT/CN2024/086900
Authority: WO
Inventors: 华菲; 赵作明
Original assignee: 北京华封集芯电子有限公司
Priority date: 2023-04-10
Filing date: 2024-04-10
Publication date: 2024-10-17

Abstract

The present invention relates to the technical field of chips, and in particular to a single chip manufacturing method, a multi-chip integration method, a chip structure, and a chip. The multi-chip integration method comprises: manufacturing a first group of chip stacking structures and a second group of chip stacking structures, wherein each group of chip stacking structures comprises a first heat dissipation plate, and a plurality of dies fixed on the first heat dissipation plate in a manner that the back surfaces of the dies face downwards; manufacturing a substrate, wherein the first substrate has a first surface and a second surface which are respectively provided with connection points and are opposite to each other; and respectively attaching the first group of chip stacking structures and the second group of chip stacking structures to the first surface and the second surface by bonding the connection points on the front surfaces of the dies in the corresponding chip stacking structures to the connection points on the corresponding surface of the first substrate, so as to form a multi-chip integrated structure. According to embodiments of the present invention, each chip stacking structure can be subjected to heat dissipation by means of the self-contained first heat dissipation plate, and the heat dissipation requirements of integrated chips with high performance, high power consumption and high frequency can be met.

Description

A single chip, multi-chip integration, preparation method, chip structure and chip

Technical Field

The present invention relates to the field of chip technology, and in particular to a single chip, multi-chip integration, a preparation method, a chip structure and a chip.

Background Art

At present, the development of various fields has higher and higher requirements for chip performance. Multiple performance chips such as CPU, GPU, storage chip, AI chip, communication chip, etc. need to be integrated to meet market demand. However, the integration of multiple chips in a package structure requires a large enough bandwidth to meet the signal transmission between chips, which inevitably requires the chips to be stacked as close together as possible, and this stacking will greatly increase power consumption, which in turn puts forward higher heat dissipation requirements. However, the existing multi-chip integrated structure has very limited heat dissipation capacity and cannot meet the current heat dissipation requirements of high-performance, high-power and high-frequency chip integration.

The existing solutions for preparing single chips are mostly to prepare wafers first, then prepare multiple bare chips on a large area of the wafer and connect the bare chips, and then cut them to obtain a single chip containing one or more bare chips. This large-area preparation solution can be based on large plates for molding, adding wire redistribution layers (RDL), etc., which is conducive to reducing chip preparation costs. However, this large-area preparation process relies on expensive equipment investment and the quality of the wafer itself. Defects in equipment or wafers will cause the loss of good chips, making it difficult to realize the benefits of large-area manufacturing, and it is not easy to guarantee the accuracy of the single chip.

In the existing chip manufacturing process, a heat sink is usually added to provide heat conduction after the basic chip packaging (flip chip or fan-out) is completed on the substrate.

However, the inventors of this application found that this process has at least the following defects in the process of realizing the present invention: the requirements for the heat dissipation material at the interface between the heat sink and the chip are relatively high. If the metal indium with a good thermal conductivity is selected, its low melting point will cause the indium to melt in the reflow soldering process of surface mounting, resulting in voids or delamination. However, if a high melting point heat dissipation material is selected, the flip-chip solder ball connection will melt in the heat sink mounting process, thereby causing poor connection between the chip and the substrate. In addition, organic heat dissipation adhesive is also used as the heat dissipation interface material of the existing chip, but the thermal conductivity of the existing organic heat dissipation adhesive is only about 5% of that of the metal interface thermal conductive material.

This defect makes the heat dissipation capacity of existing chips limited, and cannot meet the heat dissipation requirements of current high-performance, high-power and high-frequency chips.

The existing solutions for preparing single chips are mostly to prepare wafers first, then prepare multiple bare chips on a large area of the wafer and connect the bare chips, and then cut them to obtain a single chip containing one or more bare chips. This large-area preparation solution can be based on large plates for molding, adding wire redistribution layers (RDL), etc., which is conducive to reducing chip preparation costs. However, this large-area preparation process relies on expensive equipment investment and the quality of the wafer itself. Defects in equipment or wafers will cause a large loss of good chips, making it difficult to realize the benefits of large-area manufacturing, and it is not easy to guarantee the accuracy of the single chip.

Summary of the invention

The purpose of the embodiments of the present invention is to provide a multi-chip integration method and structure, which are used to at least partially solve the above technical problems.

In order to achieve the above-mentioned object, an embodiment of the present invention provides a multi-chip integration method, comprising: preparing two groups of chip stacking structures, namely a first group of chip stacking structures and a second group of chip stacking structures, and each group of chip stacking structures comprises a first heat sink and a plurality of bare chips fixed on the heat sink with the back side facing downward; preparing a first substrate, wherein the first substrate has respective A first surface and a second surface having connection points and facing each other; and the first group of chip stacking structures and the second group of chip stacking structures are respectively mounted on the first surface and the second surface by bonding the front connection points of the bare chips in the corresponding chip stacking structures with the connection points of the corresponding surface of the first substrate to form a multi-chip integrated structure.

Optionally, preparing the chip stacking structure includes: providing a first heat sink for each group of chip stacking structures, and the first heat sink has a plurality of chip fixing areas for fixing bare chips; and fixing all the bare chips in each group of chip stacking structures with their backs facing downwards on the corresponding chip fixing areas on the first heat sink.

Optionally, preparing the chip stacking structure includes: providing a common first heat sink for all bare chips, and the first heat sink has a plurality of chip fixing areas for fixing the bare chips; fixing all the bare chips with their backs facing downwards on corresponding chip fixing areas of the first heat sink respectively to form a chip plate arrangement structure; and pre-cutting the chip plate arrangement structure according to the quantity requirement of the bare chips for the chip stacking structure to obtain a corresponding chip stacking structure.

Optionally, providing a first heat sink includes: providing a planar heat sink or a heat sink with a groove; and arranging a first interface heat sink material layer on the surface of the planar heat sink or the surface of the groove to serve as a chip fixing area. The first interface heat sink material layer is made of any of the following heat sink materials: any one of nickel, tin, copper, gold, aluminum and silver; an alloy of any one of nickel, tin, copper, gold, aluminum and silver; and graphene.

Optionally, after forming the multi-chip integrated structure, the multi-chip integration method also includes: mounting contact pins on both sides of the second surface separated from the second group of chip stacking structures, and the contact pins are higher than the surface of the bare chips in the second group of chip stacking structures; and connecting the contact pins to the mainboard through a socket, the socket having an external first solder ball for electrically connecting to the mainboard and a step structure for controlling the insertion height of the contact pins.

Optionally, the multi-chip integration method further includes: providing a cooling device on the mainboard to cool the multi-chip integration structure.

An embodiment of the present invention also provides a multi-chip integrated structure prepared by any of the above-mentioned multi-chip integration methods, comprising: two groups of chip stacking structures, namely a first group of chip stacking structures and a second group of chip stacking structures, wherein each group of chip stacking structures comprises a first heat sink and a plurality of bare chips fixed on the first heat sink with their backs facing downward; and a first substrate, having a first surface and a second surface, each of which is provided with connection points and is opposite to each other; wherein the first group of chip stacking structures and the second group of chip stacking structures are respectively mounted on the first surface and the second surface, and the front connection points of the bare chips in the corresponding chip stacking structures are bonded to the connection points on the corresponding surfaces of the first substrate.

Optionally, the first heat sink is a planar heat sink or a heat sink with a groove, and a first interface heat sink material layer is provided on the surface of the planar heat sink or the surface of the groove to serve as a chip fixing area.

Optionally, a contact pin is also mounted on the second surface, and the contact pin is connected to the mainboard through the socket, wherein the contact pin is higher than the surface of the bare chip in the second group of chip stacking structure, and the socket is externally provided with a first solder ball for electrically connecting to the mainboard and a step structure for controlling the insertion height of the contact pin.

Optionally, a cooling device is provided on the mainboard.

Through the above technical scheme, in the embodiment of the present invention, before the bare chip is bonded to the substrate, the first heat sink is first mounted on the bare chip to form a chip stacking structure with the first heat sink. After the chip stacking structure is subsequently mounted to the first substrate, each chip stacking structure can dissipate heat through the first heat sink, thereby improving the heat dissipation capacity of the bare chip and meeting the heat dissipation requirements of high-performance, high-power consumption and high-frequency integrated chips.

The purpose of the embodiments of the present invention is to provide a method for preparing a single chip and a chip structure, so as to at least partially solve the above technical problems.

In order to achieve the above-mentioned purpose, an embodiment of the present invention provides a method for preparing a single chip, comprising the following steps performed in sequence: providing at least two bare chips and a second heat sink suitable for arranging the at least two bare chips, wherein the front side of the bare chip has a third group of bumps and a fourth group of bumps with a height smaller than the third group of bumps, and the surface of the second heat sink forms a chip fixing area through a second interface heat dissipation material layer; fixing the at least two bare chips with their backs facing downward to the chip fixing area on the surface of the second heat sink through the second interface heat dissipation material layer; flip-chip bonding the fourth group of bumps of the at least two bare chips through a second connection chip to form a first chip frame; bottom-filling the first chip frame; and flip-chip bonding the third group of bumps to the upper surface of the second substrate for the first chip frame after the bottom filling. The second chip frame is bottom-filled; and for the second chip frame after the bottom filling, a contact array package is manufactured on the lower surface of the second substrate to obtain a single chip.

Optionally, the second interface heat dissipation material layer adopts any of the following heat dissipation materials: any one of nickel, tin, copper, gold, aluminum and silver; alloys of any one of nickel, tin, copper, gold, aluminum and silver; and graphene.

Optionally, providing a second heat sink includes: providing a planar heat sink or a heat sink with a groove; setting a second metal coating on the surface of the planar heat sink or the surface of the groove; and setting the chip fixing area formed by the second interface heat dissipation material layer for each bare chip on the second metal coating.

Optionally, providing the second heat dissipation plate further includes: for each chip fixing area, setting a unique label for identifying the coordinates of the chip fixing area on the second heat dissipation plate.

Optionally, the preparation method further includes: after bottom filling the second chip frame, fixing the second heat sink with glue.

Optionally, making a contact array package on the lower surface of the second substrate includes: implanting a second solder ball on the lower surface of the second substrate to generate a ball grid array package; adding a planar grid array package on the lower surface of the second substrate; or performing a pin placement operation on the lower surface of the second substrate to generate a pin grid array package.

Another embodiment of the present invention provides a chip structure prepared by the above-mentioned preparation method, the chip structure comprising: at least two bare chips, wherein the front side of the bare chips has a third group of bumps and a fourth group of bumps with a height smaller than the third group of bumps; a second heat sink, the surface of which has a chip fixing area formed by a second interface heat dissipation material layer, wherein the back sides of the at least two bare chips face downward to be fixed to the chip fixing area by the second interface heat dissipation material layer; a second connecting chip, which after the bare chips are fixed to the chip fixing area, flip-chip bonds the fourth group of bumps of the at least two bare chips to form a first chip frame; a first bottom filling structure formed by bottom filling the first chip frame; a second substrate, wherein for the first chip frame after the bottom filling, the third group of bumps is flip-chip mounted to the upper surface of the second substrate to form a second chip frame; a second bottom filling structure formed by bottom filling the second chip frame; and a contact array package, and for the second chip frame after the bottom filling, the contact array package is made on the lower surface of the second substrate.

Optionally, the second heat sink is a planar heat sink or a heat sink with a groove, and a second metal coating is provided on the surface of the planar heat sink or the surface of the groove, and a chip fixing area formed by the second interface heat dissipation material layer is provided on the second metal coating for each bare chip; wherein each chip fixing area has a unique label for identifying the coordinates of the chip fixing area on the second heat sink.

Optionally, the second interface heat dissipation material layer is a material layer formed based on any of the following heat dissipation materials: any one of nickel, tin, copper, gold, aluminum, and silver; an alloy of any of nickel, tin, copper, gold, aluminum, and silver; and graphene.

Optionally, the contact array package includes a ball grid array package, a planar grid array package or a pin grid array package.

Through the above technical scheme, all packaging processes of the embodiments of the present invention are targeted at single chip product processing, avoiding the influence of chip shifting on chip bonding accuracy during large-area preparation, and easily obtaining a single chip with higher precision; at the same time, it avoids the molding, RDL addition, cutting and other processes involved in large-area preparation. For scenarios where the number of chips is not high, the difficulty and cost of chip preparation are reduced by simplifying the process.

The purpose of the embodiments of the present invention is to provide a chip manufacturing method and a chip structure to at least partially solve the above technical problems.

In order to achieve the above-mentioned purpose, an embodiment of the present invention provides a chip preparation method, comprising: providing a third heat sink and at least two groups of chip units, wherein the surface of the third heat sink forms a chip fixing area through a third interface heat dissipation material layer, and each group of chip units includes at least two bare chips, and each group of chip units corresponds to a single chip product; and for each group of chip units, all the bare chips included in the group of chip units are fixed with their backs facing down to the chip fixing area on the surface of the third heat sink through the third interface heat dissipation material layer, and then chip packaging is performed to obtain a chip structure fixed to the same third heat sink and corresponding to at least two single chip products.

Optionally, the third interface heat dissipation material layer adopts any of the following heat dissipation materials: any one of nickel, tin, copper, gold, aluminum and silver; alloys of any one of nickel, tin, copper, gold, aluminum and silver; and graphene.

Optionally, the third heat sink is circular or square.

Optionally, providing a third heat sink includes: providing a planar heat sink or a heat sink with a groove; setting a third metal coating on the surface of the planar heat sink or the surface of the groove; and setting a chip fixing area formed by the third interface heat dissipation material layer on the third metal coating for each bare chip.

Optionally, providing at least two groups of chip units includes: for each group of chip units, preparing a fifth group of bumps and a sixth group of bumps on the front side of the bare chip, wherein the height of the sixth group of bumps is smaller than that of the fifth group of bumps, and the height difference between the two groups of bumps can accommodate a third connecting chip for bonding the sixth group of bumps of different bare chips.

Optionally, the chip packaging includes: for each group of chip units, bonding the sixth group of bumps of each bare chip in the group of chip units through a third connecting chip; performing bottom filling on the bonded bumps and then performing molding; thinning the second mold layer structure formed by the molding to expose the fifth group of bumps of each bare chip; and adding a third solder ball to the exposed fifth group of bumps.

Optionally, the chip packaging further comprises: before adding the third solder ball, preparing a wire redistribution layer on the fifth group of bumps.

Optionally, the chip preparation method further includes: cutting the third heat sink to obtain a single chip product.

On the other hand, an embodiment of the present invention also provides a chip structure prepared by any of the above-mentioned chip preparation methods, comprising: a third heat sink, wherein the surface of the third heat sink forms a chip fixing area through a third interface heat dissipation material layer; at least two groups of chip units, each group of chip units includes at least two bare chips, and each group of chip units corresponds to a single chip product, wherein all the bare chips included in each group of chip units are fixed with their backs facing downward to the chip fixing area on the surface of the third heat sink through the third interface heat dissipation material layer; and a chip packaging structure formed for the bare chip after the bare chip is fixed to the third heat sink.

Optionally, the third interface heat dissipation material layer is a material layer formed based on any of the following heat dissipation materials: any one of nickel, tin, copper, gold, aluminum and silver; an alloy of any of nickel, tin, copper, gold, aluminum and silver; and graphene.

Optionally, the third heat sink is circular or square.

Optionally, the third heat sink is a planar heat sink or a heat sink with a groove, and a third metal coating is provided on the surface of the planar heat sink or the surface of the groove, and a chip fixing area formed by the third interface heat dissipation material layer is provided on the third metal coating for each bare chip.

Optionally, for each group of chip units, the front side of the bare chip has a fifth group of bumps and a sixth group of bumps, wherein the height of the sixth group of bumps is smaller than that of the fifth group of bumps, and the height difference between the two groups of bumps can accommodate a third connecting chip for bonding the sixth group of bumps of different bare chips.

Optionally, the chip packaging structure includes: a third connecting chip, used to bond the sixth group of bumps of each bare chip in each group of chip units; a second mold layer structure formed by sequentially bottom filling and molding the bonded bumps, the second mold layer structure being able to expose the fifth group of bumps; and a third solder ball added to the exposed fifth group of bumps.

Optionally, the chip packaging structure further includes: a wire redistribution layer disposed on the fifth group of bumps before adding the third solder balls.

Through the above technical solution, the embodiment of the present invention first provides a third heat sink, and then fixes the bare chips in multiple groups of chip units on the third heat sink for chip packaging. Therefore, on the one hand, the interface heat dissipation material range between the third heat sink and the bare chip is expanded, and on the other hand, the chip preparation process is optimized.

In order to achieve the above-mentioned purpose, an embodiment of the present invention provides a multi-chip integration method, comprising the following steps performed in sequence: providing a third substrate with a hollow in the middle part, the third substrate having a first surface and a second surface opposite to each other, and the first surface having connection points; flip-chip bonding a part of the front connection points of each bare chip in the first group of bare chips to the connection points of the first surface of the third substrate, and leaving another part of the front connection points suspended in the hollow; placing a second group of bare chips in the hollow, and flip-chip bonding the front connection points of each bare chip to the part of the suspended connection points of each bare chip in the first group of bare chips in a face-to-face direct interconnection manner; attaching a heat sink on the back of each bare chip in the first group of bare chips and the second group of bare chips; and preparing a fourth solder ball on the second surface of the third substrate.

Optionally, the first group of bare chips includes at least two bare chips, and the second group of bare chips includes a single bare chip, the size of the single bare chip is smaller than the cavity, and the connection points of the single bare chip are bonded to some of the connection points of all the bare chips in the first group of bare chips that are suspended.

Optionally, after each bare chip in the first group of bare chips is bonded to the third substrate, the multi-chip integration method further includes: performing bottom filling on the first group of bare chips.

Optionally, after the second group of bare chips are bonded to the part of the connection points, the multi-chip integration method further includes: performing bottom filling on the second group of bare chips.

An embodiment of the present invention also provides a multi-chip integrated structure prepared by any of the above-mentioned multi-chip integration methods, comprising: a third substrate with a hollow in the middle part, the third substrate having a first surface and a second surface opposite to each other, and the first surface having connection points; a first group of bare chips and a second group of bare chips, wherein a part of the front connection points of each bare chip in the first group of bare chips are flip-chip bonded downward to the first surface of the third substrate, and another part of the front connection points are suspended in the hollow; the second group of bare chips is placed in the hollow, and the front connection points of each bare chip are flip-chip bonded to the part of the suspended connection points of each bare chip in the first group of bare chips in a face-to-face direct interconnection manner; a heat sink mounted on the back of each bare chip in the first group of bare chips and the second group of bare chips; and a fourth solder ball prepared on the second surface of the third substrate.

The embodiment of the present invention utilizes a hollow circular third substrate to specifically design a single chip, and connects multiple bare chips into a large single chip through face-to-face direct interconnection, which can reduce the manufacturing cost of chip integration and provide connection between different chips.

Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

FIG1 is a schematic flow chart of a chip preparation method according to Embodiment 1 of the present invention;

2(a) to 2(k) are schematic diagrams of various steps of preparing a chip involved in an example of Embodiment 1 of the present invention, and also illustrate the chip structure of Embodiment 2 of the present invention;

3(a)-3(b) are plan views respectively showing the distribution of two bare chips and four bare chips on the first heat sink; and

4(a) to 4(c) are schematic diagrams showing a process of cutting a first heat dissipation plate;

FIG5 is a schematic diagram of a process for preparing a single chip according to Embodiment 3 of the present invention;

FIG. 6 (a1) to FIG. 6 (g) are schematic diagrams of various steps of preparing a chip involved in an example of Embodiment 3 of the present invention, and also illustrate an exemplary chip structure of Embodiment 4 of the present invention; and

7(a)-7(b) are plan views respectively showing the distribution of two bare chips and four bare chips on the second heat sink;

FIG8 is a schematic flow chart of a chip preparation method according to Embodiment 1 of the present invention;

9(a) to 9(k) are schematic diagrams of various steps of preparing a chip involved in an example of the first embodiment of the present invention, and also illustrate the chip structure of the second embodiment of the present invention;

10(a)-10(b) are plan views respectively showing the distribution of two bare chips and four bare chips on the third heat sink; and

11(a) to 11(c) are schematic diagrams showing a process of cutting a third heat dissipation plate;

12 is a schematic diagram of a flow chart of a multi-chip integration method according to Embodiment 7 of the present invention;

FIG. 13( a ) to FIG. 13( n ) are schematic diagrams of various steps of preparing a chip involved in an example of Embodiment 7 of the present invention. At the same time, the multi-chip integrated structure of the eighth embodiment of the present invention is shown; and

FIG. 14 is a schematic diagram of bonding four bare chips through one bare chip in an example of an embodiment of the present invention.

Description of reference numerals:
100, first heat sink; 110, first metal plating layer; 120, first interface heat dissipation material layer; 210, first bare chip;
220, a second bare chip; 230, a first group of bumps; 240, a second group of bumps; 300, a first connection chip; 400, a first mold layer structure; 500, a first solder ball; 600, a first RDL.
101, second heat sink; 111, second interface heat dissipation material layer; 211, third bare chip; 221, fourth bare chip;
231, a third group of bumps; 241, a fourth group of bumps; 301, a second connection chip; 401, a first chip frame; 500, a first bottom filling structure; 200, a second substrate; 700, a second chip frame; 800, a second bottom filling structure; 900, a second solder ball; 1000, a chip structure.
102, third heat sink; 112, third metal coating; 121, third interface heat dissipation material layer; 212, fifth bare chip;
222, sixth bare chip; 232, fifth group of bumps; 242, sixth group of bumps; 302, third connection chip; 402, second mold layer structure; 901, third solder ball; 601, second RDL.
903, third substrate; 410, cavity; 420, connection point area; 213, seventh bare chip; 223, eighth bare chip;
224, the ninth bare chip; 904, the heat sink; 905, the fourth solder ball.

DETAILED DESCRIPTION

The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

Before introducing the solutions of the embodiments of the present invention, some of the terms involved are introduced first so that those skilled in the art can better understand the solutions of the embodiments of the present invention.

1) Chip packaging: refers to the protection of bare chips to prevent them from being damaged by the outside world. Different packaging technologies vary greatly in preparation procedures and processes.

2) Flip-chip: The chip flipping process refers to placing the chip connection points downward for operation. For example, flip-chip bonding refers to placing the chip connection points downward to connect to a substrate, a carrier, a circuit board, another chip, etc. Among them, a bump is a typical connection point.

3) Compression molding: The chip compression molding process refers to placing the chip connection frame in a mold and then injecting the curing material into the mold to form a mold layer structure that protects the chip connection frame through compression.

4) Bottom filling: This refers to applying epoxy resin glue or the like on the edge of the flip chip frame. Through the "capillary effect", the glue is sucked to the opposite side of the frame to complete the bottom filling process. The glue is then cured by heating to obtain a reliable and stable chip process.

5) Substrate and carrier: The substrate has electrical properties and has wiring inside so that the bare chip can transmit signals horizontally and vertically through the wiring; the carrier does not have electrical properties and only plays a mechanical bearing role.

6) Single chip: refers to a single chip that has been cut and separated (i.e. no further cutting is required) and can independently perform specific calculations after packaging. It can integrate multiple bare chips to achieve multiple calculations, such as powerful CPUs, GPUs, and AI chips.

7) Face-to-face direct interconnection: For example, for two chips, one chip is vertically soldered to the flip-chip connection point array of another chip without additional substrates, wires, RDL, etc. to achieve chip interconnection.

Embodiment 1.

Fig. 1 is a schematic flow chart of a chip manufacturing method according to Embodiment 1 of the present invention. As shown in Fig. 1, the chip manufacturing method according to the embodiment of the present invention comprises the following steps S100 and S200.

Step S100: providing a first heat sink and at least two groups of chip units.

The first heat sink 100 is a flat heat sink (as shown in FIG. 2( a )) or a heat sink with a groove (as shown in FIG. 2( b )), and the surface of the flat heat sink or the surface of the groove is formed by a first interface heat sink material layer 120. A chip fixing area is formed. The groove depth can be determined by the chip thickness design. Each group of chip units includes at least two bare chips, and each group of chip units corresponds to a single chip product. Thus, it can be seen that the embodiment of the present invention is intended to prepare a large-board chip product, which has multiple single chip products on the large-board chip product.

In a preferred embodiment, the first interface heat dissipation material layer 120 is made of any of the following heat dissipation materials: any one of nickel, tin, copper, gold, aluminum and silver; an alloy of any one of nickel, tin, copper, gold, aluminum and silver; and graphene. In addition, the first heat dissipation plate itself can also be made of these materials. However, it should be noted that the embodiments of the present invention include but are not limited to these materials, and other high thermal conductivity interface heat dissipation metals are also applicable.

In a more preferred embodiment, a planar heat sink or a heat sink with a groove is provided, a first metal coating is arranged on the surface of the planar heat sink or the surface of the groove, and a chip fixing area formed by the first interface heat dissipation material layer 120 is arranged on the first metal coating for each bare chip.

In addition, the first heat sink is circular or square. The circular heat sink is suitable for wafer-level processes, and the square heat sink is suitable for panel-level processes. The size of the first heat sink can be selected according to specific process capabilities.

In step S200, for each group of chip units, all the bare chips included therein are fixed with their backs facing downward to the chip fixing area on the surface of the first heat sink 100 through the first interface heat dissipation material layer 120, and then the chips are packaged to obtain a chip structure fixed to the same heat sink and corresponding to at least two single chip products.

In order to fix the bare chip on the first heat sink, as described above, a metal coating is first provided on the surface of the first heat sink, and a chip fixing area formed by the first interface heat dissipation material layer 120 is divided and provided for each bare chip on the first metal coating; a first metal coating is also prepared on the back side of the bare chip, so that the first metal coating of each bare chip and the first heat sink is bonded through the first interface heat dissipation material layer, thereby fixing the corresponding bare chip to the corresponding chip fixing area.

With respect to chip packaging, a detailed description will be given in the following example of the application of the chip manufacturing method according to the embodiment of the present invention.

Figure 2 (a) to Figure 2 (k) are schematic diagrams of various processes involved in this example. This example takes a group of chip units including two bare chips as an example, as shown in the figure, the corresponding chip preparation processes are sequentially as follows: processes s1-s6.

Step s1: As shown in FIG. 2( a ) to FIG. 2( c ), prepare a first heat sink 100 .

Specifically, as shown in FIG2(a), the first heat sink 100 is a planar heat sink, or as shown in FIG2(b), the first heat sink 100 is a heat sink with a groove, and the first heat sink uses, for example, a thin interface heat dissipation material of SnAu or a high-temperature heat dissipation glue. The groove is intended to accommodate a bare chip, and its depth is determined by the chip thickness design. It should be noted that the following process takes the planar heat sink shown in FIG2(a) as an example.

As further shown in FIG. 2( c ), a first metal coating 110 is provided on the surface of the first heat sink 100. For example, a coating made of a metal that is not easily oxidized, such as nickel or gold, is used to enhance corrosion resistance and facilitate bonding with a bare chip having the first metal coating on the back. A chip fixing area formed by a first interface heat dissipation material layer 120 is provided on the first metal coating 110 for each bare chip. For example, if the first metal coating is a nickel layer, a gold coating layer may be further provided on the nickel layer to form a chip fixing area for placing the bare chip.

Here, the first metal plating layer on the back of the bare chip and the surface of the first heat sink helps to improve the bonding between the first interface heat dissipation material layer and the bare chip, and prevents surface oxidation and delamination of the interface heat dissipation material layer and the bare chip at high temperatures.

Step s2: As shown in FIG. 2( d ), bare chips are prepared, namely a first bare chip 210 and a second bare chip 220 .

Specifically, a first group of bumps 230 and a second group of bumps 240 are prepared on the front side of the bare chip, wherein the height of the second group of bumps 240 is smaller than that of the first group of bumps 230, and the height difference between the two groups of bumps can accommodate a first connection chip for bonding the second group of bumps 240 of different bare chips. The second group of bumps is, for example, copper (Cu) bumps, and the first group of bumps is, for example, a taller Cu column.

Step s3: As shown in FIG. 2( e ), the bare chips are distributed on the first heat sink 100 .

For example, a first metal coating layer (not shown in FIG. 2( d) ) such as a nickel layer may be prepared on the back side of the bare chip using a back side metal (BSM) process to facilitate bonding with the first metal coating layer 110 of the heat sink 100 , so that the corresponding bare chip is placed in a corresponding chip fixing area formed by the first interface heat dissipation material layer 120 .

It should also be noted that, considering that the second group of bumps 240 will be used for chip bonding in subsequent processes, the first group of bumps 240 may be used for chip bonding in subsequent processes. A bare chip 210 and a second bare chip 220 are arranged on the first heat sink 100 in a manner that the second group of bumps 240 are close to each other.

Step s4: as shown in FIG. 2( f ), the second group of bumps of each bare chip is bonded via the first connection chip 300 .

Specifically, the first connection chip 300 is preferably smaller than the first bare chip 210 and the second bare chip 220, and is more preferably a hyperlink chip of a low-power chip to reduce the overall power consumption of the final chip structure. In addition, the first connection chip 300 is flip-chip mounted on the second group of bumps 240 of the two bare chips to achieve bonding between the first bare chip 210 and the second bare chip 220.

This example uses flip chip bonding, but it is understandable that in other examples, thermal compression bonding, laser assisted bonding, etc. may also be used.

Step s5: As shown in FIG. 2( g ), after the bonding is completed, bottom filling is performed on the corresponding bonded bumps, and then molding is performed.

Specifically, the first mold layer structure 400 is formed by bottom filling and molding, and the first mold layer structure 400 is similar to the chip connection frame shown in FIG. 2(f) and is filled or cured to protect the connection points between each bare chip and the first heat sink 100 and the first connection chip 300, and helps to improve the flatness of the chip surface. In addition, the molding scheme using the mold is suitable for large-scale molding for large boards, for example, there are 500 chips on a large heat sink (hereinafter also referred to as a large board), but only one molding is required.

Step s6: as shown in FIG. 2( h ), the first mold layer structure 400 formed by the compression mold is thinned to expose the first group of bumps 230 of each bare chip, and first solder balls 500 are added to the exposed first group of bumps 230 .

Specifically, thinning the first mold layer structure 400 helps to further improve the flatness of the chip surface on the one hand, and facilitates the implantation of the first solder ball 500 on the other hand.

Thus, through the above steps s1 to s6, the chip structure of this example is obtained, and its plan view distributed on the first heat sink is shown in FIG. 3(a).

The above example takes a group of chip units and the chip unit includes two bare chips as an example, but it should be clear that a group of chip units can include more bare chips, as shown in Figure 3(b), and the four bare chips can also be interconnected based on a first connecting chip, that is, the first connecting chip in the middle of Figure 3(b) (for example, marked as Die5) is used to bond the four bare chips around it (for example, marked as Die1-Die4).

It should also be clear that a large heat sink can be distributed with multiple groups of chip units, and each group corresponds to a single chip product. For example, as shown in FIG4(a), a group of chip units includes bare chip 1-bare chip 3, and as shown in FIG4(b), a large first heat sink can have multiple groups of such chip units. In this regard, corresponding to the chip arrangement of the large board in FIG4(b), after completing the first solder ball addition, the large board can also include the following step s7.

Process s7: As shown in FIG2(i), the required bare chips are cut out as single chip products based on the cutting process. Continuing from FIG4(b), FIG4(c) shows the application of the cutting process, for example, cutting the heat sink along the dotted line in the figure to obtain multiple single chip products. For example, the single chip product includes bare chip 1 and bare chip 2, which are the CPU and GPU of the host, respectively. In addition, after the single chip product is cut out, the function of bare chip 1 and bare chip 2 can also be tested based on the single chip product. It should be noted that the functions of each single chip product after cutting are independent, and this method of manufacturing multiple single chip products through a large plate and a large area helps to reduce the cost of chip preparation.

In another example, for step s6, it can also include: before adding the first solder ball, preparing a first wire redistribution layer (RDL) 600 on the first group of bumps 230. Specifically, as shown in FIG2(j), a first RDL 600 is added to the exposed first group of bumps, and then as shown in FIG2(k), a first solder ball 500 is implanted on the first RDL. Here, the solder ball spacing in FIG2(h) is limited by the chip bumps, and through the first RDL, the solder ball spacing in FIG2(k) can be changed according to demand, which helps to set different solder ball distributions, thereby realizing more communication methods between the chip and other components. In addition, the first RDL can also be connected to the mainboard of the host to expand the bandwidth, and then use the cooperation with the mainboard to realize more functions.

In summary, the embodiment of the present invention first provides a first heat sink, and then fixes the bare chips in the plurality of chip units on the first heat sink for chip packaging. This process has at least the following advantages over the existing process of first packaging the chips and then adding the heat sink.

1) A wider range of interface heat dissipation materials can be used between the first heat dissipation plate and the bare chip in the embodiment of the present invention. Specifically, because the first heat dissipation plate is provided before the reflow process and the heat sink mounting process, compared with the existing process that can only use metal indium or low melting point heat dissipation materials, the interface heat dissipation material in the embodiment of the present invention can be made of more types of materials, such as the nickel, tin, copper, gold, aluminum, silver and their alloys mentioned above.

2) The embodiment of the present invention automatically integrates the heat sink on the chip, and does not require an additional process to add the heat sink. The heat dissipation performance that can be provided is at least 3 times higher than that of the above-mentioned existing process. It is more suitable for manufacturing high-performance, high-power consumption, high-frequency chips such as CPUs and GPUs that meet the performance requirements and heat dissipation requirements of data center servers, big data servers, and vehicle-mounted servers.

3) The first heat sink is provided before the chip is packaged, and can be combined with the existing wafer and panel mass production process. As described above, it is easy to obtain a large-panel chip structure, so that the large-panel chip structure can be sold directly, and single chip products cut from the heat sink can also be sold.

4) In the embodiment of the present invention, the first heat sink is prepared before other processes are started. It can be determined in advance whether to use a circular heat sink or a square heat sink, and then consider using a wafer-level process or a panel-level process.

5) The embodiments of the present invention realize the interconnection of multiple bare chips, thereby realizing, for example, chiplet stacking to obtain stronger chip performance.

6) The embodiment of the present invention first provides a first heat sink, and then the bare chip can be directly soldered to the first heat sink, so that it is not easy to shift in the subsequent process. The existing process generally requires the use of mechanical glue for fixing, and the accuracy is not as good as the solution of the embodiment of the present invention.

7) In the existing process, the heat sink is mounted after the first solder ball is implanted, which may affect the stability of the first solder ball. However, the embodiments of the present invention can avoid this defect.

8) In the existing process, the chip must first be placed on the first carrier, which needs to be removed by high temperature or laser in the subsequent process. This carrier removal process not only introduces additional costs, but also introduces additional stress and causes poor product performance. The embodiment of the present invention is equivalent to using the first heat sink as the carrier, and does not require a subsequent carrier removal process, which not only improves the heat dissipation performance, but also helps maintain the reliability of the electrical connection.

Embodiment 2.

The second embodiment of the present invention provides a chip structure, as shown in FIG. 2(h) and FIG. 2(k), which is formed by the chip preparation method of the first embodiment above, corresponding to at least two single chip products fixed on the same first heat sink, and includes: a first heat sink 100, wherein the surface of the first heat sink 100 forms a chip fixing area through a first interface heat dissipation material layer 120; at least two groups of chip units, and each group of chip units corresponds to a single chip product, wherein all bare chips included in each group of chip units are fixed to the chip fixing area on the surface of the first heat sink 100 with their backs facing downward through the first interface heat dissipation material layer 120; and a chip packaging structure formed for the bare chip after the bare chip is fixed to the first heat sink. Among them, FIG. 2(k) is relative to FIG. 2(h), and a first RDL 600 is additionally provided in the chip packaging structure, and the specific structures of other components can refer to the above-mentioned FIG. 2(a)-FIG. 2(k).

In a preferred embodiment, the first interface heat dissipation material layer 120 is a material layer formed based on any of the following heat dissipation materials, and can also be in the form of a heat dissipation film or heat dissipation glue: any one of nickel, tin, copper, gold, aluminum and silver; an alloy of any of nickel, tin, copper, gold, aluminum and silver; and graphene. In addition, the heat dissipation plate can be round or square.

Furthermore, as shown in FIG2(c), a first metal coating 110 is provided on the surface of the first heat sink, and a chip fixing area formed by the first interface heat dissipation material layer 120 is provided on the first metal coating 110 for each bare chip; as shown in FIG2(e), a first metal coating is also prepared on the back side of the bare chip, so that the first metal coatings of the bare chip and the first heat sink are bonded through the first interface heat dissipation material layer to place the corresponding bare chip in the correspondingly provided chip fixing area.

Furthermore, as shown in FIG2(d), for each group of chip units, the front side of the bare chip has a first group of bumps 230 and a second group of bumps 240, wherein the height of the second group of bumps 240 is smaller than that of the first group of bumps 230, and the height difference between the two groups of bumps can accommodate a first connecting chip for bonding the second group of bumps 240 of different bare chips.

Furthermore, as shown in FIG. 2( f) to FIG. 2( h), the chip packaging structure includes: a first connection chip 300, A second group of bumps for bonding each bare chip in each group of chip units; a first mold layer structure 400 formed by sequentially bottom-filling and molding the bonded bumps, the first mold layer structure being capable of exposing the first group of bumps (achieved by thinning the first mold layer structure); and a first solder ball 500 added to the exposed first group of bumps.

In a more preferred embodiment, as shown in Figures 2(j) and 2(k), the chip packaging structure also includes: a first RDL 600 set on the first group of bumps 230 before adding the first solder ball 500.

For more implementation details and effects of the chip structure, reference may be made to the aforementioned embodiments of the chip preparation method, which will not be described in detail here.

Embodiment three.

FIG5 is a flow chart of a method for preparing a single chip according to the third embodiment of the present invention, the method includes steps S5100 to S5700 executed in sequence, and FIG6(a1) to FIG6(g) are process charts of an example of applying the method, including steps s51 to s58. In combination with FIG5 and FIG6(a1) to FIG6(g), the implementation of the method includes steps S5100 to S5700.

Step S5100: provide at least two bare chips and a second heat sink suitable for arranging the at least two bare chips.

This step S5100 corresponds to the steps s51 - s52 of the example.

Step s51: As shown in FIG. 6( a1 ) and FIG. 6( a2 ), a second heat sink 101 is provided.

Specifically, the second heat sink 101 is a flat heat sink (as shown in FIG6(a1)) or a heat sink with a groove (as shown in FIG6(a2)), and a second metal coating is provided on the surface of the flat heat sink or the surface of the groove. The second metal coating is, for example, a multilayer structure including nickel and gold, and a chip fixing area formed by a second interface heat dissipation material layer 111 is provided on the second metal coating for each bare chip. The groove is intended to accommodate the bare chip, and its depth can be determined by the chip thickness design. It should be noted that the following process takes the flat heat sink shown in FIG6(a1) as an example.

The second interface heat dissipation material layer 111 is made of any of the following heat dissipation materials: any one of nickel, tin, copper, gold, aluminum and silver; an alloy of any one of nickel, tin, copper, gold, aluminum and silver; and graphene.

Furthermore, for each chip fixing area, a unique label can be set to identify the coordinates of the chip fixing area on the second heat sink, so that the fixing position of the bare chip on the second heat sink can be easily determined through the label.

Step s52 : as shown in FIG. 6( b ), provide bare chips, including a third bare chip 211 and a fourth bare chip 221 .

The front side of the bare chip has a third group of bumps 231 and a fourth group of bumps 241, and the height of the fourth group of bumps 241 is less than that of the third group of bumps 231. The fourth group of bumps is, for example, copper (Cu) bumps, and the third group of bumps is, for example, a higher Cu column. In a preferred embodiment, the height difference between the two groups of bumps is required to accommodate a second connection chip for chip bonding in a subsequent process.

In addition, for each bare chip, another material layer (such as a second metal coating layer) compatible with the second interface heat dissipation material layer corresponding to the second heat dissipation plate can be prepared on the back of the bare chip to facilitate subsequent fixing of the bare chip on the second heat dissipation plate.

Step S5200: fix the at least two bare chips with their backs facing downward on the chip fixing area on the surface of the second heat dissipation plate through bonding with the second interface heat dissipation material layer.

Corresponding step s53 : as shown in FIG. 6( c ), the third bare chip 211 and the fourth bare chip 221 are distributed on the second heat sink 101 .

Specifically, the back side of the bare chip (such as having a gold-plated layer) is bonded to the surface of the second heat sink 101 (such as also a gold-plated layer) through the second interface heat dissipation material layer 111, so that the corresponding bare chip is fixed to the chip fixing area formed corresponding to the second interface heat dissipation material layer 111. For example, there are multiple layers of second metal coatings plated with titanium, nickel, vanadium, and gold on the back side of the bare chip, which helps to improve the bonding between the second interface heat dissipation material layer and the bare chip, prevent surface oxidation and delamination of the second interface heat dissipation material layer and the bare chip at high temperatures. Similarly, the second heat sink and the chip fixing area on the second heat sink can also be plated with a second metal coating such as nickel and gold to prevent surface oxidation and interface bonding delamination.

It should be noted that, considering that the fourth group of bumps 241 of the bare chip will be used for chip bonding in the subsequent process, the third bare chip 211 and the fourth bare chip 221 can be fixed on the second heat sink 101 in such a way that the fourth group of bumps 241 are close to each other.

Step S5300: flip-chip bonding the fourth group of bumps of the at least two bare chips through a second connecting chip to form a first chip frame.

Corresponding step s54: as shown in FIG. 6( d ), the fourth group of bumps 241 of the two bare chips are bonded via the second connecting chip 301 to obtain a first chip frame 401 .

Specifically, the second connection chip 301 is also a bare chip, but preferably has a size smaller than the third bare chip 211 and the fourth bare chip 221, and more preferably has a thickness less than the height difference between the two groups of bumps on the bare chip, that is, the height difference between the two groups of bumps can accommodate the second connection chip 301. In addition, the second connection chip 301 preferably uses a low-power chip to reduce the overall power consumption of the final chip structure. The second connection chip 301 is flip-chip mounted on the fourth group of bumps 241 of the two bare chips to achieve signal transmission between the third bare chip 211 and the fourth bare chip 221, and the first chip frame 401 shown in FIG. 6 (d) is obtained.

Step S5400 , bottom filling is performed on the first chip frame, for example, to protect the connection points between the chip 301 and the chips 211 and 221 .

Corresponding step s55: Also as shown in FIG. 6( d ), the first chip frame 401 is bottom-filled, and a first bottom-filling structure 500 is shown in the figure.

Step S5500: For the first chip frame after the bottom filling, flip-chip the third group of bumps onto the upper surface of the second substrate to form a second chip frame.

Corresponding step s56: as shown in FIG. 6( e ), the second substrate 200 is flipped to obtain a second chip frame 700 .

Step S5600: performing bottom filling on the second chip frame.

Corresponding step s57: as shown in Fig. 6(f), the second chip frame 700 is bottom-filled, and the figure shows a second bottom-filling structure 800. Preferably, the second heat sink may be fixed by glue to ensure the stability of the second heat sink.

Step S5700: For the second chip frame after the bottom filling, a contact array package is manufactured on the lower surface of the second substrate to obtain a single chip.

Among them, the S5700 may include making a contact array package on the lower surface of the second substrate: implanting a second solder ball on the lower surface of the second substrate to generate a ball grid array package (Ball Grid Array, BGA); adding a land grid array package (Land Grid Array, LGA) on the lower surface of the second substrate; or performing a pin placement operation on the lower surface of the second substrate to generate a pin grid array package (Pin Grid Array, PGA).

Corresponding step s58: as shown in FIG. 6( g ), second solder balls 900 are implanted on the lower surface of the second substrate 200 to generate a BGA and obtain a final chip structure 1000 .

Thus, through the above steps s51 to s58, an exemplary chip structure 1000 is obtained, and its plan view distributed on the second heat sink is shown in FIG7(a). It is easy to know that the third bare chip 211 and the fourth bare chip 221 can be bare chips of the same or different sizes. For example, the third bare chip 211 and the fourth bare chip 221 are CPU chips of exactly the same size, and through the above steps s1 to s8, a chip with more powerful computing functions is generated for use in big data computing of servers, etc.; for example, the third bare chip 211 and the fourth bare chip 221 are CPU chips and GPU chips of different sizes, respectively, and thus through the above steps s51 to s58, a multifunctional chip integrating data processing functions and image processing functions is generated, for example, for use in vehicle terminals for autonomous driving, etc.

In addition, the above example takes two bare chips as an example, but it should be clear that more bare chips can be included. As shown in Figure 7(b), four bare chips can be interconnected based on a second connecting chip, that is, the second connecting chip in the middle of Figure 7(b) (for example, Die5) is used to bond the four bare chips around it (for example, Die1-Die4).

In summary, compared with the large-area chip preparation solution in the prior art, the embodiment of the present invention is specially designed for a single chip preparation solution, which has at least the following advantages.

1) The embodiment of the present invention is specifically designed for a single chip, avoiding the impact of chip displacement (such as thermal expansion of the carrier or wafer or displacement of the interface material) on the chip bonding accuracy in the large-area preparation process, making it easy to obtain a single chip with higher precision; at the same time, it avoids the processes of molding, RDL addition, cutting, etc. involved in large-area preparation. For scenes with low requirements for the number of chips, the difficulty and cost of chip preparation are reduced by simplifying the process. It can be seen from experiments that the single chip preparation method of the embodiment of the present invention can obtain a yield of more than >99.9%, and the cost of equipment and process is less than <10% of the wafer process.

2) In the single chip preparation method of the embodiment of the present invention, a second heat sink is first provided, and then the bare chip is placed on the second heat sink for chip packaging. Therefore, compared with the existing process of first packaging the chip and then adding a heat sink, the interface heat dissipation material between the second heat sink and the chip can use a wider range of heat dissipation materials, and metals with good thermal conductivity can be selected to improve heat dissipation. These metals have relatively high melting points. For example, nickel, tin, copper, gold, aluminum, silver and their alloys have melting points higher than 241 degrees Celsius. In the existing process, if the chip is flip-chip bonded first and the heat sink is added last, it will lead to poor bonding connection points. However, this invention can use interface heat dissipation materials with high melting point and high thermal conductivity, and then bond the chip, which can maintain a good heat dissipation interface and also have good bonding of the chip electrical connection points.

3) The embodiment of the present invention realizes the interconnection of multiple bare chips, and further realizes high-speed electrical connection and signal transmission between bare chips to obtain stronger chip performance.

4) The embodiment of the present invention first provides a second heat sink, and then the bare chip can be directly soldered to the second heat sink, so that it is not easy to shift in the subsequent process. The existing process generally requires the use of organic glue for fixing. This organic glue will shift in the subsequent high-temperature process, resulting in the failure of bonding in the subsequent process.

5) In the existing process, the heat sink is usually mounted after the chip is bonded, which may affect the stability of the solder joints. However, the embodiments of the present invention can avoid this defect.

6) In the existing process, the bare chip must first be placed on a carrier, which needs to be removed by high temperature or laser in the subsequent process. This carrier removal process not only introduces additional costs, but also introduces additional stress and causes poor product performance. The embodiment of the present invention is equivalent to using the second heat sink as a carrier, and does not require a subsequent carrier removal process, which not only improves the heat dissipation performance, but also helps maintain the reliability of the electrical connection.

Embodiment 4.

Embodiment 4 of the present invention provides a chip structure, as shown in FIG. 6 (a1) to FIG. 6 (g), the chip structure is prepared by the preparation method of the above-mentioned embodiment 3, and the chip structure 1000 includes: at least two bare chips, wherein the front side of the bare chips has a third group of bumps 231 and a fourth group of bumps 241 whose height is smaller than the third group of bumps; a second heat sink 101, the surface of which has a chip fixing area formed by a second interface heat dissipation material layer 111, wherein the back side of the at least two bare chips faces downward to be fixed to the chip fixing area by the second interface heat dissipation material layer; a second connecting chip 301, which is flip-chip bonded to the chip fixing area after the bare chips are fixed to the chip fixing area. A fourth group of bumps 241 of at least two bare chips to form a first chip frame 401; a first bottom filling structure 500 formed by bottom filling the first chip frame 401; a second substrate 200, wherein for the first chip frame 401 after the bottom filling, the third group of bumps 231 are flip-chip mounted to the upper surface of the second substrate 200 to form a second chip frame 700; a second bottom filling structure 800 formed by bottom filling the second chip frame 700; and a contact array package, wherein for the second chip frame after the bottom filling, the contact array package is made on the lower surface of the second substrate, for example, a second solder ball 900 is implanted.

In a preferred embodiment, the second heat sink 101 is a planar heat sink or a heat sink with a groove, and a second metal coating is provided on the surface of the planar heat sink or a specific area of the surface of the groove, and a chip fixing area formed by the second interface heat dissipation material layer is provided on the second metal coating for each bare chip; wherein each chip fixing area has a unique label for identifying the coordinates of the chip fixing area on the second heat sink 101.

In a preferred embodiment, the second interface heat dissipation material layer 111 is a material layer formed based on any of the following heat dissipation materials: any one of nickel, tin, copper, gold, aluminum, and silver; an alloy of any of nickel, tin, copper, gold, aluminum, and silver; and graphene.

In a preferred embodiment, the contact array package includes BGA, LGA or PGA.

For more implementation details and effects of the chip structure, please refer to the aforementioned embodiment 3 regarding the preparation method, which will not be described in detail here.

Embodiment five.

Fig. 8 is a schematic flow chart of a chip manufacturing method according to Embodiment 5 of the present invention. As shown in Fig. 8, the chip manufacturing method according to the embodiment of the present invention includes the following steps S8100 and S8200.

Step S8100: provide a third heat sink and at least two groups of chip units.

The third heat sink 102 is a flat heat sink (as shown in FIG. 9( a) ) or a heat sink with grooves (as shown in FIG. 9(b)), and the surface of the planar heat sink or the surface of the groove forms a chip fixing area through a third interface heat dissipation material layer 121. The groove depth can be determined by the chip thickness design. Each group of chip units includes at least two bare chips, and each group of chip units corresponds to a single chip product. In this way, it can be seen that the embodiment of the present invention is intended to prepare a large-board chip product, which has multiple single chip products on it.

In a preferred embodiment, the third interface heat dissipation material layer 121 is made of any of the following heat dissipation materials: any one of nickel, tin, copper, gold, aluminum and silver; an alloy of any one of nickel, tin, copper, gold, aluminum and silver; and graphene. In addition, the third heat dissipation plate itself can also be made of these materials. However, it should be noted that the embodiments of the present invention include but are not limited to these materials, and other high thermal conductivity interface heat dissipation metals are also applicable.

In a more preferred embodiment, a planar heat sink or a heat sink with a groove is provided, a third metal coating is arranged on the surface of the planar heat sink or the surface of the groove, and a chip fixing area formed by the third interface heat dissipation material layer 121 is arranged on the third metal coating for each bare chip.

In addition, the third heat sink is circular or square. The circular heat sink is suitable for wafer-level processes, and the square heat sink is suitable for panel-level processes. The size of the third heat sink can be selected according to specific process capabilities.

Step S8200, for each group of chip units, all the bare chips included therein are fixed with their backs facing down to the chip fixing area on the surface of the third heat sink 102 through the third interface heat dissipation material layer 121, and then the chips are packaged to obtain a chip structure fixed to the same third heat sink and corresponding to at least two single chip products.

With regard to the fixation of the bare chip on the third heat sink, as described above, a third metal coating is provided on the surface of the third heat sink, and a chip fixing area formed by the third interface heat dissipation material layer 121 is divided and provided on the third metal coating for each bare chip; a third metal coating is also prepared on the back side of the bare chip, so that the third metal coating of each bare chip and the third heat sink is bonded through the third interface heat dissipation material layer, thereby achieving the fixation of the corresponding bare chip to the corresponding chip fixing area.

Figures 9(a) to 9(k) are schematic diagrams of various processes involved in this example. This example takes a group of chip units including two bare chips as an example, as shown in the figure, the corresponding chip preparation processes are sequentially as follows: processes s81 to s86.

Step s81: As shown in FIG. 9( a ) to FIG. 9 ( c ), prepare the third heat sink 102 .

Specifically, as shown in FIG9(a), the third heat sink 102 is a planar heat sink, or as shown in FIG9(b), the third heat sink 102 is a heat sink with a groove, and the third heat sink uses, for example, a thin interface heat dissipation material of SnAu or a high-temperature heat dissipation glue. The groove is intended to accommodate a bare chip, and its depth is determined by the chip thickness design. It should be noted that the following process takes the planar heat sink shown in FIG9(a) as an example.

As further shown in FIG9(c), a third metal coating 112 is provided on the surface of the third heat sink 102. For example, a coating made of a metal that is not easily oxidized, such as nickel or gold, is used to enhance corrosion resistance and facilitate bonding with a bare chip having a third metal coating on the back. A chip fixing area formed by a third interface heat dissipation material layer 121 is provided on the third metal coating 112 for each bare chip. For example, the third metal coating is a nickel layer, and a gold coating layer can be further provided on the nickel layer to form a chip fixing area for placing the bare chip.

Here, the third metal plating layer on the back of the bare chip and the surface of the third heat sink helps to improve the bonding between the third interface heat dissipation material layer and the bare chip, and prevents surface oxidation and delamination of the third interface heat dissipation material layer and the bare chip at high temperatures.

Step s82: As shown in FIG. 9( d ), bare chips are prepared, namely the fifth bare chip 212 and the sixth bare chip 222 .

Specifically, a fifth group of bumps 232 and a sixth group of bumps 242 are prepared on the front side of the bare chip, wherein the height of the sixth group of bumps 242 is smaller than that of the fifth group of bumps 232, and the height difference between the two groups of bumps can accommodate a third connection chip for bonding the sixth group of bumps 242 of different bare chips. The sixth group of bumps is, for example, copper (Cu) bumps, and the fifth group of bumps is, for example, a taller Cu column.

Step s83: As shown in FIG. 9( e ), the bare chips are distributed on the third heat sink 102 .

For example, a third metal coating (not shown in FIG. 9( d)) may be prepared on the back of the bare chip by using a back side metal (BSM) process, such as a nickel layer, so as to facilitate bonding with the third metal coating 112 of the third heat sink 102, so that the corresponding bare chip is placed on the corresponding chip solid formed by the third interface heat dissipation material layer 121. Fixed area.

It should also be noted that, considering that the sixth group of bumps 242 will be used for chip bonding in subsequent processes, the fifth bare chip 212 and the sixth bare chip 222 can be arranged on the third heat sink 102 in such a way that the sixth group of bumps 242 are close to each other.

Step s84: as shown in FIG. 9( f ), the sixth group of bumps of each bare chip is bonded through the third connection chip 302 .

Specifically, the third connection chip 302 is preferably smaller in size than the fifth bare chip 212 and the sixth bare chip 222, and is more preferably a hyperlink chip of a low-power chip to reduce the overall power consumption of the final chip structure. In addition, the third connection chip 302 is flip-chip mounted on the sixth group of bumps 242 of the two bare chips to achieve bonding between the fifth bare chip 212 and the sixth bare chip 222.

Step s85: As shown in FIG. 9( g ), after the bonding is completed, bottom filling is performed on the corresponding bonded bumps, and then molding is performed.

Specifically, the second mold layer structure 402 is formed by bottom filling and molding, and the second mold layer structure 402 is similar to the chip connection frame shown in FIG. 9(f) and is filled or cured to protect the connection points between each bare chip and the third heat sink 102 and the third connection chip 302, and helps to improve the flatness of the chip surface. In addition, the molding scheme using the mold is suitable for large-scale molding for large boards, for example, there are 500 chips on a large third heat sink (hereinafter also referred to as a large board), but only one molding is required.

Step s86: as shown in FIG. 9( h ), the second mold layer structure 402 formed by the compression mold is thinned to expose the fifth group of bumps 232 of each bare chip, and third solder balls 901 are added to the exposed fifth group of bumps 232 .

Specifically, thinning the second mold layer structure 402 helps to further improve the flatness of the chip surface on the one hand, and facilitates the implantation of the third solder ball 901 on the other hand.

In this way, through the above steps s81 to s86, the chip structure of this example is obtained, and its planar top view distributed on the third heat sink is shown in FIG. 10( a ).

The above example takes a group of chip units and the chip unit includes two bare chips as an example, but it should be clear that a group of chip units can include more bare chips, as shown in Figure 10(b), and the four bare chips can also be interconnected based on a third connecting chip, that is, the third connecting chip in the middle of Figure 10(b) (for example, marked as Die5) is used to bond the four bare chips around it (for example, marked as Die1-Die4).

It should also be clear that a large third heat sink can be distributed with multiple groups of chip units, and each group corresponds to a single chip product. For example, as shown in FIG11(a), a group of chip units includes bare chip 1-bare chip 3, and as shown in FIG11(b), a large third heat sink can have multiple groups of such chip units. In this regard, the chip arrangement corresponding to the large board in FIG11(b) is carried out in accordance with the above-mentioned process s86. After the third solder ball is added, the large board can also include the following process s87.

Process s87: As shown in FIG9(i), the required bare chips are cut out as single chip products based on the cutting process. Continuing from FIG11(b), FIG11(c) shows the application of the cutting process, for example, cutting the heat sink along the dotted line in the figure to obtain multiple single chip products. For example, the single chip product includes bare chip 1 and bare chip 2, which are the CPU and GPU of the host respectively. In addition, after the single chip product is cut out, the function of bare chip 1 and bare chip 2 can also be tested based on the single chip product. It should be noted that the functions of each single chip product after cutting are independent, and this method of manufacturing multiple single chip products through a large plate and a large area helps to reduce the cost of chip preparation.

In another example, for process s86, it can also include: before adding the third solder ball, preparing a second wire redistribution layer (RDL) 601 on the fifth group of bumps 232. Specifically, as shown in FIG9(j), a second RDL 601 is added to the exposed fifth group of bumps, and then as shown in FIG9(k), a third solder ball 901 is implanted on the second RDL. Here, the third solder ball spacing in FIG9(h) is limited by the chip bumps, and through the second RDL, the third solder ball spacing in FIG9(k) can be changed according to demand, which helps to set different third solder ball distributions, thereby realizing more communication methods between the chip and other components. In addition, the second RDL can also be connected to the main board of the host to expand the bandwidth, and then use the cooperation with the main board to realize more functions.

In summary, the embodiment of the present invention first provides a third heat sink, and then fixes the bare chips in the plurality of chip units on the third heat sink. The chip is packaged on a hot plate. Compared with the existing process of first packaging the chip and then adding a heat sink, this process has at least the following advantages.

1) A wider range of interface heat dissipation materials can be used between the third heat dissipation plate and the bare chip in the embodiment of the present invention. Specifically, because the third heat dissipation plate is provided before the reflow process and the heat sink mounting process, compared with the existing process that can only use metal indium or low melting point heat dissipation materials, the interface heat dissipation material in the embodiment of the present invention can be made of more types of materials, such as the nickel, tin, copper, gold, aluminum, silver and their alloys mentioned above.

3) The third heat sink is provided before the chip is packaged, and can be combined with the existing wafer and panel mass production process. As mentioned above, it is easy to obtain a large-panel chip structure, so that the large-panel chip structure can be sold directly, and single chip products cut based on the third heat sink can also be sold.

4) In the embodiment of the present invention, the third heat sink is prepared before other processes are started. It can be determined in advance whether to use a circular heat sink or a square heat sink, and then consider using a wafer-level process or a panel-level process.

6) The embodiment of the present invention first provides a third heat sink, and then the bare chip can be directly soldered to the third heat sink, so that it is not easy to shift in the subsequent process. The existing process generally requires the use of mechanical glue for fixing, and the accuracy is not as good as the solution of the embodiment of the present invention.

7) In the existing process, the heat sink is mounted after the third solder ball is implanted, which may affect the stability of the third solder ball. However, the embodiment of the present invention can avoid this defect.

8) In the existing process, the chip must first be placed on a carrier, which needs to be removed by high temperature or laser in the subsequent process. This carrier removal process not only introduces additional costs, but also introduces additional stress and causes poor product performance. The embodiment of the present invention is equivalent to using the third heat sink as a carrier, and does not require a subsequent carrier removal process, which not only improves the heat dissipation performance, but also helps maintain the reliability of the electrical connection.

Embodiment six.

The sixth embodiment of the present invention provides a chip structure, as shown in FIG. 9(h) and FIG. 9(k), which is formed by the chip preparation method of the fifth embodiment above, corresponding to at least two single chip products fixed on the same third heat sink, and includes: a third heat sink 102, wherein the surface of the third heat sink 102 forms a chip fixing area through a third interface heat dissipation material layer 121; at least two groups of chip units, and each group of chip units corresponds to a single chip product, wherein all bare chips included in each group of chip units are fixed to the chip fixing area on the surface of the third heat sink 102 with their backs facing downward through the third interface heat dissipation material layer 121; and a chip packaging structure formed for the bare chip after the bare chip is fixed to the third heat sink. Among them, FIG. 9(k) is relative to FIG. 9(h), and a second RDL 601 is additionally provided in the chip packaging structure, and the specific structures of other components can refer to the above-mentioned FIG. 9(a)-FIG. 9(k).

In a preferred embodiment, the third interface heat dissipation material layer 121 is a material layer formed based on any of the following heat dissipation materials, and can also be in the form of a heat dissipation film or heat dissipation glue: any one of nickel, tin, copper, gold, aluminum and silver; an alloy of any one of nickel, tin, copper, gold, aluminum and silver; and graphene. In addition, the third heat dissipation plate can be round or square.

Furthermore, as shown in FIG9(c), a third metal coating 112 is provided on the surface of the third heat sink, and a chip fixing area formed by the third interface heat dissipation material layer 121 is provided on the third metal coating 112 for each bare chip; as shown in FIG9(e), a third metal coating is also prepared on the back side of the bare chip, so that the third metal coatings of the bare chip and the third heat sink are bonded to each other through the third interface heat dissipation material layer to place the corresponding bare chip in the correspondingly provided chip fixing area.

Further, as shown in FIG. 9( d ), for each group of chip units, the front side of the bare chip has a fifth group of bumps 232 and a sixth group of bumps 242, wherein the height of the sixth group of bumps 242 is smaller than that of the fifth group of bumps 232, and the two groups of bumps are The height difference of the dots can accommodate a third connection chip for bonding a sixth group of bumps 242 of a different die.

Furthermore, as shown in Figures 9(f) to 9(h), the chip packaging structure includes: a third connecting chip 302, used to bond the sixth group of bumps of each bare chip in each group of chip units; a second mold layer structure 402 formed by sequentially bottom filling and molding the bonded bumps, the second mold layer structure can expose the fifth group of bumps (achieved by thinning the second mold layer structure); and a third solder ball 901 added to the exposed fifth group of bumps.

In a more preferred embodiment, as shown in Figures 9(j) and 9(k), the chip packaging structure also includes: a second RDL 601 is arranged on the fifth group of bumps 232 before adding the third solder ball 901.

Embodiment seven.

FIG12 is a flow chart of a multi-chip integration method according to Embodiment 7 of the present invention, and the multi-chip integration method includes the following steps S9100-S9500, while FIG13(a)-FIG13(n) are process charts of an example of applying the multi-chip integration method, including steps s91-s96. In combination with FIG12 and FIG13(a)-FIG13(n), the multi-chip integration method includes the following steps S9100-S9500.

Step S9100: providing a third substrate having a meander shape and a hole in the middle, wherein the third substrate has a first surface and a second surface opposite to each other, and the first surface has a connection point.

Corresponding to step s91: As shown in FIG13(a), a third substrate 903 is provided, wherein the middle portion thereof has a cavity 410. In addition, the third substrate 903 has two surfaces, and a connection point area 420 can be set on the first surface, as shown in FIG13(b) (which is a cross-sectional view of the third substrate shown in FIG13(a) based on the cavity), and a clear connection point is prepared thereon for realizing chip bonding with a bare chip.

Step S9200, flip-chip bonding a portion of the front connection points of each bare chip in the first group of bare chips to the first surface of the third substrate, and leaving another portion of the front connection points suspended in the cavity.

Corresponding to step s92: As shown in FIG13(c), the first group of bare chips includes the seventh bare chip 213 and the eighth bare chip 223, and the two bare chips are flip-chip bonded to the connection points on the first surface (upper surface) of the third substrate 903. As further shown in FIG13(d) (which is a cross-sectional view based on the cavity of the structure corresponding to FIG13(c)), part of the front connection points of the seventh bare chip 213 and the eighth bare chip 223 are flip-chip bonded to the connection point area on the first surface of the third substrate, while another part of the front connection points are suspended in the cavity.

Step S9300, placing the front connection points of each bare chip of the second group of bare chips in the cavity in a face-to-face direct interconnection manner, so as to flip-chip bond the suspended part of the connection points of each bare chip in the first group of bare chips through the front connection points of each bare chip.

Corresponding to step s93: As shown in FIG. 13(e) and FIG. 13(f) (wherein FIG. 13(f) is a cross-sectional view based on the cavity of the structure corresponding to FIG. 13(e)), the second group of bare chips includes a ninth bare chip 224, the size of which is smaller than the cavity 410, and its front connection points are flip-chip bonded to some connection points of the seventh bare chip 213 and the eighth bare chip 223 suspended in the cavity 410 in a face-to-face direct interconnection manner. That is, the connection points of the ninth bare chip 224 are bonded to some connection points of all bare chips in the first group of bare chips.

The definition of face-to-face direct interconnection has been given above, and it should be pointed out in conjunction with FIG. 13(f) that face-to-face direct interconnection includes the following two characteristics:

1) The ninth bare chip is directly connected to the first and eighth bare chips without using RDL, for example, by wire bonding;

2) The "face-to-face" connection between the ninth bare chip and the first and eighth bare chips is achieved by vertical and direct bonding between the two.

In a preferred embodiment, the multi-chip integration method may also include: performing bottom filling on the first group of bare chips after each bare chip in the first group of bare chips is bonded to the third substrate; and/or performing bottom filling on the second group of bare chips after the second group of bare chips is bonded to the partial connection points.

Corresponding to step s94: as shown in FIG. 13(g) and FIG. 13(h) (FIG. 13(h) is the structure corresponding to FIG. 13(g)) As shown in the cross-sectional view based on the void, the current chip structure is first flipped; then referring to Figure 13(i) and Figure 13(j) (Figure 13(j) is a cross-sectional view based on the void of the structure corresponding to Figure 13(i)), the bottom filling is performed on the flipped structure to protect the connection points between the seventh bare chip 213, the eighth bare chip 223 and the ninth bare chip 224 and the third substrate 903.

S9400: Attach a heat sink to the back side of each bare chip in the first group of bare chips and the second group of bare chips.

Corresponding to process s95: as shown in Figure 13(k) and Figure 13(l) (Figure 13(l) is a cavity-based cross-sectional view of the structure corresponding to Figure 13(k)), a heat sink 904 is mounted on the back of the seventh bare chip 213, the eighth bare chip 223 and the ninth bare chip 224.

In an example, the interface heat dissipation material may use organic heat dissipation glue, interface metal (such as indium) or graphene according to power consumption requirements.

S9500: Prepare fourth solder balls on a second surface of the third substrate, wherein the second surface is an opposite surface to the first surface.

Corresponding to step s96: As shown in FIG. 13(m) and FIG. 13(n) (FIG. 13(n) is a cross-sectional view based on a cavity of the structure corresponding to FIG. 13(m)), a fourth solder ball 905 is prepared on the second surface (lower surface) of the third substrate. The fourth solder ball 905 can use a fourth solder ball with a copper core to control the height of the soldering and provide sufficient space for the ninth bare chip 224 to dissipate heat.

In an example, an external device can be electrically connected via the fourth solder ball 905 to achieve signal transmission between each bare chip and the external device based on the fourth solder ball. For example, if the external device is a power supply, power supply to each bare chip can be guaranteed.

In a preferred embodiment, the first group of bare chips includes at least two bare chips, and the second group of bare chips includes a single bare chip, the size of the single bare chip is smaller than the cavity, and the connection point of the single bare chip is bonded to the suspended connection points of all bare chips in the first group of bare chips. For example, as shown in Figure 14, the first group of bare chips includes four bare chips around (for example, Die1-Die4), and the second group of bare chips includes another bare chip in the middle (for example, Die5), Die5 is placed in the cavity of the third substrate, and is bonded to the suspended connection points of Die1-Die4 in the cavity, thereby realizing face-to-face direct interconnection between Die5 and bare chips Die1-Die4. Die1-Die4 can also transmit low-frequency, low-bandwidth signals through the third substrate 903 according to the needs of signal transmission, for example, signals of peripherals such as mouse and keyboard, while high-frequency, high-bandwidth signals are such as transmission signals between CPU and GPU, CPU/GPU and DRAM, CPU/GPU and communication chip, CPU/GPU and AI chip, etc.

Therefore, the multi-chip integration method of the embodiment of the present invention has at least the following advantages over the existing large-area preparation solutions.

1) The embodiment of the present invention utilizes a circular third substrate with a cavity to specifically design a single chip, and connects multiple bare chips into a large single chip through face-to-face direct interconnection, which can not only reduce the manufacturing cost of chip integration, but also provide connection between different chips; at the same time, it avoids the influence of thermal expansion of the carrier or wafer or displacement of the interface material on the chip placement accuracy in the large-area preparation process, and it is easy to obtain a single chip with higher precision; in addition, it also avoids the processes involved in large-area preparation, such as molding, RDL addition, and cutting. The difficulty and cost of chip preparation are reduced by simplifying the process, but a high-precision multi-chip integrated structure can still be obtained.

2) The embodiment of the present invention utilizes the hollow space of the third substrate in the shape of a circle to realize the face-to-face direct interconnection of two groups of bare chips, so that the connecting wire between the two groups of bare chips is the shortest. According to the theory that "the longer the wire, the greater the RC", it is easy to know that shortening the wire will significantly reduce RC, thereby reducing signal delay and distortion, improving the bandwidth of signal transmission between the two groups of bare chips, and realizing high-speed connection between the two groups of bare chips. In the example, this high-speed connection can be applied to the integrated chip of DRAM and CPU/GPU, or to the integrated chip structure of RF chip and digital chip in the communication system, so as to greatly improve the overall performance of the integrated chip.

3) The embodiment of the present invention adds a heat sink to a single chip, thereby ensuring normal heat dissipation of high-power chips such as CPU and GPU, and avoiding ineffective heat dissipation that reduces chip reliability.

4) The embodiment of the present invention adds a fourth solder ball to a single chip, thereby ensuring signal transmission between the bare chip and external devices.

Embodiment eight.

Embodiment 8 of the present invention provides a multi-chip integrated structure, as shown in Figures 13(a) to 13(n), the multi-chip integrated structure is prepared by the method of the above-mentioned embodiment 7, and the multi-chip integrated structure includes: a third substrate 903 with a hollow 410 in the middle part, the third substrate 903 has a first surface and a second surface opposite to each other, and the first surface has a connection point; a first group of bare chips and a second group of bare chips, wherein a part of the front connection points of each bare chip in the first group of bare chips are flip-chip bonded downward to the first surface of the third substrate 903, and another part of the front connection points are suspended in the hollow 410; the second group of bare chips are placed in the hollow 410, and the front connection points of each bare chip are flip-chip bonded to the part of the connection points of each bare chip in the first group of bare chips in a face-to-face direct interconnection manner; a heat sink 904 mounted on the back of each bare chip in the first group of bare chips and the second group of bare chips; and a fourth solder ball 905 prepared on the second surface of the third substrate.

In a preferred embodiment, the first group of bare chips includes at least two bare chips, and the second group of bare chips includes a single bare chip, the size of the single bare chip is smaller than the cavity, and the connection points of the single bare chip are bonded to some of the connection points of all the bare chips in the first group of bare chips that are suspended.

For more implementation details and effects of the multi-chip integration structure, reference may be made to the aforementioned seventh embodiment of the multi-chip integration method, which will not be described in detail here.

It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

A multi-chip integration method, characterized in that:

include:

Two groups of chip stacking structures are prepared, namely a first group of chip stacking structures and a second group of chip stacking structures, and each group of chip stacking structures comprises a first heat sink (100) and a plurality of bare chips fixed on the first heat sink (100) with their backs facing downward, and the bare chips are high-performance chips, high-power consumption chips or high-frequency chips, wherein the preparation of the chip stacking structure comprises the following steps performed in sequence:

A first heat dissipation plate (100) is provided for each group of chip stacking structures, and the first heat dissipation plate (100) has a plurality of chip fixing areas formed by a first interface heat dissipation material layer (120) for fixing bare chips;

as well as

All bare chips in each group of chip stacking structures are fixed with their backs facing downward to the chip fixing area on the corresponding first heat sink (100) through bonding of the first interface heat dissipation material layer (120), wherein the first interface heat dissipation material layer (120) is made of any of the following heat dissipation materials: any one of nickel, tin, copper, gold, aluminum and silver; an alloy of any one of nickel, tin, copper, gold, aluminum and silver; and graphene;

Prepare a first substrate (300), the first substrate (300) having a first surface and a second surface, each of which is provided with a connection point and is opposite to each other;

The first group of chip stacking structures and the second group of chip stacking structures are respectively mounted on the first surface and the second surface by bonding the front connection points of the bare chips in the corresponding chip stacking structures to the connection points on the corresponding surface of the first substrate (300) to form a multi-chip integrated structure;

Mounting contact pins (500) on both sides of the second surface separated from the second group of chip stacking structures, and the contact pins (500) are higher than the surface of the bare chip in the second group of chip stacking structures;

The contact pin is connected to the main board (700) via a socket (600), the socket (600) being externally provided with a first solder ball (610) for electrically connecting the main board (700) and a step structure (620) for controlling the insertion height of the contact pin (500);

as well as

A cooling device is arranged on the mainboard (700) to cool the multi-chip integrated structure.
The multi-chip integration method according to claim 1, characterized in that:

Preparing a chip stacking structure includes:

A common first heat sink (100) is provided for all bare chips, and the first heat sink (100) has a plurality of chip fixing areas for fixing the bare chips;

Fixing all the bare chips with their backs facing downwards to the corresponding chip fixing areas of the first heat sink (100) to form a chip plate arrangement structure; and

According to the quantity requirement of the chip stacking structure for bare chips, the chip plate arrangement structure is pre-cut to obtain a corresponding chip stacking structure.
The multi-chip integration method according to claim 1, characterized in that:

Providing a first heat dissipation plate (100) includes:

Providing a flat heat sink or a heat sink with grooves; and

The first interface heat dissipation material layer (120) is arranged on the surface of the planar heat dissipation plate or the surface of the groove to serve as a chip fixing area.
A multi-chip integrated structure prepared by the multi-chip integration method according to any one of claims 1 to 3, characterized in that:

include:

Two groups of chip stacking structures are respectively a first group of chip stacking structures and a second group of chip stacking structures, wherein each group of chip stacking structures comprises a first heat sink (100) having a first interface heat dissipation material layer (120) and a plurality of bare chips with their backs facing downwards and fixed on the first heat sink (100) through bonding of the first interface heat dissipation material layer (120), wherein the bare chips are high-performance chips, high-power consumption chips or high-frequency chips, and the first interface heat dissipation material layer (120) is made of any of the following heat dissipation materials: any one of nickel, tin, copper, gold, aluminum and silver; with respect to nickel, tin, copper, gold, aluminum and silver, the first heat dissipation material layer (120) is preferably any one of nickel, tin, copper, gold, aluminum and silver. An alloy of any of silver; and graphene;

A first substrate (300) having a first surface and a second surface, each of which is provided with a connection point and is opposite to each other;

The first group of chip stacking structures and the second group of chip stacking structures are mounted on the first surface and the second surface respectively, and the front connection points of the bare chips in the corresponding chip stacking structures are bonded to the connection points of the corresponding surfaces of the first substrate (300);

The second surface is also mounted with a contact pin (500), and the contact pin (500) is connected to the mainboard (700) through a socket (600), wherein the contact pin (500) is higher than the surface of the bare chip in the second group of chip stacking structures, and the socket (600) is externally provided with a first solder ball (610) for electrically connecting to the mainboard (700) and a step structure (620) for controlling the insertion height of the contact pin;

The mainboard (700) is provided with a cooling device.
The multi-chip integrated structure according to claim 4 is characterized in that:

The first heat dissipation plate (100) is a planar heat dissipation plate or a heat dissipation plate with a groove, and the surface of the planar heat dissipation plate or the surface of the groove is provided with the first interface heat dissipation material layer (120) to serve as a chip fixing area.
A method for preparing a single chip, characterized by comprising the following steps performed in sequence:

S1, providing at least two bare chips and a second heat sink (101) suitable for arranging the at least two bare chips, wherein the front side of the bare chip has a third group of bumps (231) and a fourth group of bumps (241) whose height is smaller than the third group of bumps (231), and the back side of the bare chip has a second metal coating, and the surface of the second heat sink forms a chip fixing area through a second interface heat dissipation material layer (111), wherein providing the second heat sink (101) comprises: providing a planar heat sink or a heat sink with a groove; arranging a second metal coating on the surface of the planar heat sink or the surface of the groove; and arranging the chip fixing area formed by the second interface heat dissipation material layer (111) on the second metal coating for each bare chip;

S2, fixing the at least two bare chips with their backs facing downwards on the chip fixing area on the surface of the second heat dissipation plate through bonding of the second interface heat dissipation material layer (111);

S3, flip-chip bonding the fourth group of bumps (241) of the at least two bare chips through a second connecting chip (301) to form a first chip frame (400); the height of the second connecting chip (301) is smaller than the height difference between the fourth group of bumps (241) of the third group of bumps (231);

S4, performing bottom filling on the first chip frame (400) to form a first bottom filling structure (500); the first bottom filling structure (500) covers the fourth group of bumps (241);

S5, for the first chip frame (400) after the bottom filling, flip-chip bonding the third group of bumps (231) to the upper surface of the second substrate (600) to form a second chip frame (700);

S6, performing bottom filling on the second chip frame (700) to form a second bottom filling structure (800); a first portion of the second bottom filling structure (800) covers the third group of bumps (231), and a second portion of the second bottom filling structure (800) covers the second heat sink and the second substrate;

And, S7, for the second chip frame (700) after the bottom filling, a contact array package is manufactured on the lower surface of the second substrate (200) to obtain a single chip.
The preparation method according to claim 6, characterized in that the second interface heat dissipation material layer (111) is made of any of the following heat dissipation materials:

Any of nickel, tin, copper, gold, aluminum and silver;

Alloys of any of nickel, tin, copper, gold, aluminum and silver; and

Graphene.
The preparation method according to claim 6, characterized in that providing the second heat dissipation plate (101) further comprises:

For each chip fixing area, a unique label is set to identify the coordinates of the chip fixing area on the second heat sink (101).
The preparation method according to claim 6, characterized in that it also includes:

After the second chip frame (700) is bottom-filled, the second heat sink (101) is fixed by glue dispensing.
The preparation method according to claim 6, characterized in that manufacturing a contact array package on the lower surface of the second substrate (200) comprises:

Implanting second solder balls (900) on the lower surface of the second substrate (200) to generate a ball grid array package (BGA);

Adding a land grid array package LGA on the lower surface of the second substrate (200); or

A pin placement operation is performed on the lower surface of the second substrate (200) to generate a pin grid array package (PGA).
A chip structure (1000) prepared by the preparation method according to any one of claims 6 to 10, characterized in that the chip structure (1000) comprises:

At least two bare chips, wherein the front side of the bare chip has a third group of bumps (231) and a fourth group of bumps (241) whose height is smaller than the third group of bumps (231), and the back side of the bare chip has a second metal plating layer;

A second heat sink (101), the surface of which has a chip fixing area formed by a second interface heat sink material layer (111), wherein the at least two bare chips are fixed to the chip fixing area with their backs facing downwards through bonding of the second interface heat sink material layer (111), wherein the second heat sink (101) is a planar heat sink or a heat sink with a groove, and the surface of the planar heat sink or the surface of the groove is provided with a second metal coating, and a chip fixing area formed by the second interface heat sink material layer (111) is provided on the second metal coating for each bare chip;

a second connecting chip (301) which, after the bare chip is fixed on the chip fixing area, flips and bonds the fourth group of bumps (241) of the at least two bare chips to form a first chip frame (400); the height of the second connecting chip (301) is smaller than the height difference of the fourth group of bumps (241) of the third group of bumps (231);

A first bottom filling structure (500) is formed by bottom filling the first chip frame (400); the first bottom filling structure (500) covers the fourth group of bumps (241);

A second substrate (600), wherein the third group of bumps (231) is flip-chip mounted on the upper surface of the second substrate (600) after the bottom filling of the first chip frame (400) to form a second chip frame (700);

A second bottom filling structure (800) is formed by bottom filling the second chip frame (700); a first portion of the second bottom filling structure (800) covers the third group of bumps (231), and a second portion of the second bottom filling structure (800) covers the second heat sink and the second substrate;

as well as,

A contact array package is provided, and for the second chip frame (700) after bottom filling, the contact array package is made on the lower surface of the second substrate (600).
The chip structure (1000) according to claim 11 is characterized in that each chip fixing area has a unique label for identifying the coordinates of the chip fixing area on the second heat sink.
The chip structure (1000) according to claim 11 is characterized in that the second interface heat dissipation material layer (111) is a material layer formed based on any of the following heat dissipation materials: any one of nickel, tin, copper, gold, aluminum, and silver; an alloy of any one of nickel, tin, copper, gold, aluminum, and silver; and graphene.
The chip structure (1000) according to claim 11 is characterized in that the contact array package includes a ball grid array package (BGA), a land grid array package (LGA) or a pin grid array package (PGA).
A chip preparation method, characterized by comprising:

A third heat sink (102) and at least two groups of chip units are provided, wherein the surface of the third heat sink (102) forms a chip fixing area through a third interface heat dissipation material layer (121), each group of chip units includes at least two bare chips, and each group of chip units corresponds to a single chip product; the heat dissipation material layer (121) is a highly thermally conductive interface heat dissipation metal;

For each group of chip units, all bare chips included therein are fixed with their backs facing downward to the chip fixing area on the surface of the third heat sink (102) through the third interface heat dissipation material layer (121), and then the chips are packaged to obtain a chip structure fixed to the same third heat sink (102) and corresponding to at least two single chip products;

Wherein, providing the third heat dissipation plate (102) comprises:

Providing a flat heat sink or a heat sink with grooves;

Disposing a second metal coating on the surface of the planar heat sink or the surface of the groove;

The back side of the bare chip is provided with a second metal plating layer, so that the second metal plating layer of the bare chip and the third heat sink is The metal coating layer is bonded through the third interface heat dissipation material layer to place the corresponding bare chip in the corresponding bare chip fixing area.
The chip preparation method according to claim 15, characterized in that the third interface heat dissipation material layer (121) is made of any of the following heat dissipation materials:

Any of nickel, tin, copper, gold, aluminum and silver;

Alloys of any of nickel, tin, copper, gold, aluminum and silver.
The chip preparation method according to claim 15 is characterized in that the third heat sink (102) is circular or square.
The chip preparation method according to claim 15, characterized in that providing at least two groups of chip units comprises:

For each group of chip units, a fifth group of bumps (232) and a sixth group of bumps (242) are prepared on the front side of the bare chip, wherein the height of the sixth group of bumps (242) is smaller than that of the fifth group of bumps (232), and the height difference between the two groups of bumps can accommodate a third connecting chip for bonding the sixth group of bumps (242) of different bare chips.
The chip preparation method according to claim 18, characterized in that chip packaging comprises:

For each group of chip units, the sixth group of bumps (242) of each bare chip in the group of chip units are bonded via a third connection chip (302);

Perform bottom filling on the bumps after bonding, and then perform molding;

Thinning the second mold layer structure (402) formed by the compression mold to expose the fifth group of bumps (232) of each bare chip; and

A third solder ball (901) is added to the exposed fifth group of bumps (232).
The chip preparation method according to claim 19, characterized in that chip packaging further comprises:

Before adding the third solder ball (901), a second conductive line redistribution layer (RDL) (601) is prepared on the fifth group of bumps (232).
The chip preparation method according to claim 15, characterized in that the chip preparation method further comprises:

The third heat dissipation plate (102) is cut to obtain a single chip product.
A chip structure prepared by the chip preparation method according to any one of claims 15 to 21, characterized in that the chip structure corresponds to at least two single chip products fixed on the same third heat sink, and comprises:

A third heat sink (102), wherein a chip fixing region is formed on the surface of the third heat sink (102) through a third interface heat sink material layer (121), wherein the third heat sink (102) is a planar heat sink or a heat sink with a groove, and a second metal coating layer (112) is provided on the surface of the planar heat sink or the surface of the groove, and a chip fixing region formed by the third interface heat sink material layer (121) is provided on the second metal coating layer for each bare chip;

At least two groups of chip units, each group of chip units includes at least two bare chips, and each group of chip units corresponds to a single chip product, wherein all bare chips included in each group of chip units are fixed with their backs facing downward to the chip fixing area on the surface of the third heat dissipation plate (102) through the third interface heat dissipation material layer (121); and

After the bare chip is fixed on the third heat sink, a chip packaging structure is formed for the bare chip.
The chip structure according to claim 22, characterized in that the third interface heat dissipation material layer (121) is a material layer formed based on any of the following heat dissipation materials:

Any of nickel, tin, copper, gold, aluminum and silver;

Alloys of any of nickel, tin, copper, gold, aluminum and silver.
The chip structure according to claim 22 is characterized in that the third heat dissipation plate (102) is circular or square.
The chip structure according to claim 22 is characterized in that, for each group of chip units, the front side of the bare chip has a fifth group of bumps (232) and a sixth group of bumps (242), wherein the height of the sixth group of bumps (242) is smaller than that of the fifth group of bumps (232), and the height difference between the two groups of bumps can accommodate a third connecting chip for bonding the sixth group of bumps (242) of different bare chips.
The chip structure according to claim 25, characterized in that the chip packaging structure comprises:

A third connection chip (302) is used for bonding the sixth group of bumps of each bare chip in each group of chip units;

A second mold layer structure (402) is formed by sequentially performing bottom filling and compression molding on the bonded bumps, wherein the second mold layer structure (402) is capable of exposing the fifth group of bumps (232); and

A third solder ball (901) is added on the exposed fifth group of bumps (232).
The chip structure according to claim 26, characterized in that the chip packaging structure further comprises:

Before adding the third solder ball (901), a second conductive line redistribution layer (RDL) (601) is disposed on the fifth group of bumps (232).
A multi-chip integration method, characterized by comprising the following steps performed in sequence:

Providing a third substrate (903) having a meander shape and a hollow (410) in the middle portion, wherein the third substrate (903) has a first surface and a second surface opposite to each other, and the first surface has a connection point;

Flip-chip bonding a portion of the front connection points of each bare chip in the first group of bare chips to the connection points of the first surface of the third substrate (903), and leaving another portion of the front connection points suspended in the cavity;

Placing the second group of bare chips in the cavity (410), and making the front connection points of each bare chip flip-chip bonded to the suspended connection points of each bare chip in the first group of bare chips in a face-to-face direct interconnection manner;

Performing bottom filling on the first group of bare chips and the second group of bare chips; attaching a heat sink to the back side of each bare chip in the first group of bare chips and the second group of bare chips (904); and

A fourth solder ball (905) is prepared on the second surface of the third substrate (903).
The multi-chip integration method according to claim 28 is characterized in that the first group of bare chips includes at least two bare chips, and the second group of bare chips includes a single bare chip, the size of the single bare chip is smaller than the cavity (410), and the connection points of the single bare chip are bonded to some of the connection points of all the bare chips in the first group of bare chips that are suspended.
A multi-chip integrated structure prepared by the multi-chip integration method according to claim 28 or 29, characterized in that it comprises:

A third substrate (903) having a meander shape and a hollow (410) in the middle, wherein the third substrate (903) has a first surface and a second surface opposite to each other, and the first surface has a connection point;

A first group of bare chips and a second group of bare chips, wherein a portion of front connection points of each bare chip in the first group of bare chips are flip-chip bonded downward to the first surface of the third substrate (903), and another portion of front connection points are suspended in the cavity (410); the second group of bare chips are placed in the cavity (410), and the front connection points of each bare chip are flip-chip bonded to the suspended portion of connection points of each bare chip in the first group of bare chips in a face-to-face direct interconnection manner;

A heat sink (904) is attached to the backside of each die in the first group of die and the second group of die; and

A fourth solder ball (905) is prepared on the second surface of the third substrate (903).