CN107134440A - Fan-out-type wafer level packaging structure and preparation method thereof - Google Patents
Fan-out-type wafer level packaging structure and preparation method thereof Download PDFInfo
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- CN107134440A CN107134440A CN201710475121.5A CN201710475121A CN107134440A CN 107134440 A CN107134440 A CN 107134440A CN 201710475121 A CN201710475121 A CN 201710475121A CN 107134440 A CN107134440 A CN 107134440A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 75
- 238000002360 preparation method Methods 0.000 title claims abstract description 26
- 239000004033 plastic Substances 0.000 claims abstract description 37
- 229920003023 plastic Polymers 0.000 claims abstract description 37
- 239000010410 layer Substances 0.000 claims description 277
- 229910052751 metal Inorganic materials 0.000 claims description 76
- 239000002184 metal Substances 0.000 claims description 76
- 230000004888 barrier function Effects 0.000 claims description 52
- 238000000034 method Methods 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 32
- 238000001465 metallisation Methods 0.000 claims description 21
- 239000012790 adhesive layer Substances 0.000 claims description 17
- 238000010276 construction Methods 0.000 claims description 15
- 238000001259 photo etching Methods 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 13
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 claims description 10
- 239000000853 adhesive Substances 0.000 claims description 9
- 230000001070 adhesive effect Effects 0.000 claims description 9
- 238000005520 cutting process Methods 0.000 claims description 8
- 238000004528 spin coating Methods 0.000 claims description 8
- 238000012546 transfer Methods 0.000 claims description 7
- 238000009413 insulation Methods 0.000 claims description 6
- 239000002390 adhesive tape Substances 0.000 claims description 5
- 239000000919 ceramic Substances 0.000 claims description 5
- 239000003822 epoxy resin Substances 0.000 claims description 5
- 238000003475 lamination Methods 0.000 claims description 5
- 229920000647 polyepoxide Polymers 0.000 claims description 5
- 239000000741 silica gel Substances 0.000 claims description 4
- 229910002027 silica gel Inorganic materials 0.000 claims description 4
- 238000000465 moulding Methods 0.000 claims description 3
- 238000007493 shaping process Methods 0.000 claims description 3
- 239000004952 Polyamide Substances 0.000 claims 1
- 150000001336 alkenes Chemical class 0.000 claims 1
- 150000001412 amines Chemical class 0.000 claims 1
- 229910002804 graphite Inorganic materials 0.000 claims 1
- 239000010439 graphite Substances 0.000 claims 1
- 229920002647 polyamide Polymers 0.000 claims 1
- 238000007789 sealing Methods 0.000 claims 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 16
- 229910021389 graphene Inorganic materials 0.000 description 11
- 239000004411 aluminium Substances 0.000 description 10
- 229910052782 aluminium Inorganic materials 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 10
- 239000010931 gold Substances 0.000 description 10
- 229910052737 gold Inorganic materials 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 8
- 229910052759 nickel Inorganic materials 0.000 description 8
- 229910052709 silver Inorganic materials 0.000 description 8
- 239000004332 silver Substances 0.000 description 8
- 229910052718 tin Inorganic materials 0.000 description 8
- 239000011135 tin Substances 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- 229910052719 titanium Inorganic materials 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 239000004642 Polyimide Substances 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 239000006185 dispersion Substances 0.000 description 4
- 229920000139 polyethylene terephthalate Polymers 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000005020 polyethylene terephthalate Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- HBGPNLPABVUVKZ-POTXQNELSA-N (1r,3as,4s,5ar,5br,7r,7ar,11ar,11br,13as,13br)-4,7-dihydroxy-3a,5a,5b,8,8,11a-hexamethyl-1-prop-1-en-2-yl-2,3,4,5,6,7,7a,10,11,11b,12,13,13a,13b-tetradecahydro-1h-cyclopenta[a]chrysen-9-one Chemical compound C([C@@]12C)CC(=O)C(C)(C)[C@@H]1[C@H](O)C[C@]([C@]1(C)C[C@@H]3O)(C)[C@@H]2CC[C@H]1[C@@H]1[C@]3(C)CC[C@H]1C(=C)C HBGPNLPABVUVKZ-POTXQNELSA-N 0.000 description 2
- PFRGGOIBYLYVKM-UHFFFAOYSA-N 15alpha-hydroxylup-20(29)-en-3-one Natural products CC(=C)C1CCC2(C)CC(O)C3(C)C(CCC4C5(C)CCC(=O)C(C)(C)C5CCC34C)C12 PFRGGOIBYLYVKM-UHFFFAOYSA-N 0.000 description 2
- SOKRNBGSNZXYIO-UHFFFAOYSA-N Resinone Natural products CC(=C)C1CCC2(C)C(O)CC3(C)C(CCC4C5(C)CCC(=O)C(C)(C)C5CCC34C)C12 SOKRNBGSNZXYIO-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000006193 liquid solution Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002905 metal composite material Substances 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- -1 polyethylene terephthalates Polymers 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 239000005439 thermosphere Substances 0.000 description 2
- 229910000906 Bronze Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 208000037998 chronic venous disease Diseases 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 150000002148 esters Chemical class 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The present invention provides a kind of fan-out-type wafer level packaging structure and preparation method thereof, and the encapsulating structure includes heat dissipating layer；Bonding layer positioned at heat dissipating layer upper surface；Chip structure positioned at bonding layer upper surface, the chip structure includes bare chip and the contact pad being electrically connected on bare chip and with bare chip, wherein, surface where contact pad is the upper surface of chip structure, and chip structure upper surface away from bonding layer；Plastic packaging layer positioned at heat dissipating layer upper surface, bonding layer and chip structure sidewall surfaces；Re-wiring layer positioned at plastic packaging layer and chip structure upper surface, re-wiring layer is electrically connected with contact pad；And the soldered ball projection positioned at re-wiring layer upper surface, the soldered ball projection is electrically connected with re-wiring layer.Fan-out-type wafer level packaging structure by the present invention and preparation method thereof, solve existing fan-out package structure causes the problem of device size is larger due to installing fin at its back side.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, more particularly to a kind of fan-out-type wafer level packaging structure and its system
Preparation Method.
Background technology
It is more inexpensive, more reliable, faster and more highdensity circuit be integrated antenna package pursue target.In future,
Integrated antenna package will improve the integration density of various electronic components by constantly reducing minimum feature size.At present, first
The method for packing entered includes：Wafer chip level chip-scale package (Wafer Level Chip Scale Packaging,
WLCSP), fan-out-type wafer-level packaging (Fan-Out Wafer Level Package, FOWLP), flip-chip (Flip
Chip), stacked package (Package on Package, POP) etc..
Fan-out-type wafer-level packaging is a kind of embedded chip method for packing of wafer level processing, be current a kind of input/
Output port (I/O) is more, one of the integrated preferable Advanced Packaging method of flexibility.Fan-out-type wafer-level packaging is compared to routine
Wafer-level packaging have the advantages that its is unique：1. I/O spacing is flexible, independent of chip size；2. effective nude film is only used
(die), product yield is improved；3. there is flexible 3D package paths, you can to form the figure of General Cell at top；4. have
There are preferable electrical property and hot property；5. frequency applications；6. easily high-density wiring is realized in re-wiring layer (RDL).
At present, fan-out-type wafer-level packaging method is generally：Carrier is provided, in carrier surface formation adhesive layer；In bonding
Photoetching on layer, electroplate out re-wiring layer (Redistribution Layers, RDL)；Chip is pacified using chip bonding process
It is attached on re-wiring layer；Using Shooting Technique by chip plastic packaging in capsulation material layer in；Remove carrier and adhesive layer；Again
Photoetching, plating form Underbump metallization layer (UBM) on wiring layer；Carry out planting ball backflow on UBM, form soldered ball projection；Then
Carry out wafer and stick piece, cutting scribing；It is last that fin is installed at the encapsulating structure back side.Although existing encapsulating structure is all by dissipating
Backing realizes radiating, but the encapsulating structure back side installation fin after scribing, considerably increases the device size of encapsulating structure.
In consideration of it, being necessary that a kind of new fan-out-type wafer level packaging structure of design and preparation method thereof is above-mentioned to solve
Technical problem.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of fan-out-type wafer-level packaging knot
Structure and preparation method thereof, for solve existing fan-out package structure due to its back side install fin cause device size compared with
Big the problem of.
In order to achieve the above objects and other related objects, the present invention provides a kind of fan-out-type wafer level packaging structure, described
Encapsulating structure includes：
Heat dissipating layer；
Bonding layer positioned at the heat dissipating layer upper surface；
Chip structure positioned at the bonding layer upper surface, the chip structure includes bare chip and positioned at the bare chip
Contact pad that is upper and being electrically connected with the bare chip, wherein, surface where the contact pad is the upper of chip structure
Surface, and the chip structure upper surface away from the bonding layer；
Positioned at the plastic packaging layer of the heat dissipating layer upper surface, bonding layer and chip structure sidewall surfaces；
Re-wiring layer positioned at plastic packaging layer and chip structure upper surface, the re-wiring layer and the Contact welding
Disk is electrically connected；And
Soldered ball projection positioned at the re-wiring layer upper surface, the soldered ball projection carries out electricity with the re-wiring layer
Connection.
Preferably, the encapsulating structure also includes the Underbump metallization being located between the re-wiring layer and soldered ball projection
Layer, the Underbump metallization layer is electrically connected with the re-wiring layer.
Preferably, the heat dissipating layer includes one kind in graphene, metal-to-metal adhesive or ceramics.
Preferably, the thickness of the heat dissipating layer is 1~200um.
Preferably, the bonding layer includes one kind in DAF films, metal-to-metal adhesive or adhesive tape.
Preferably, the plastic packaging layer includes one kind in polyimide layer, layer of silica gel or epoxy resin layer.
Preferably, the re-wiring layer includes：
The first insulating barrier positioned at plastic packaging layer and chip structure upper surface, first insulating barrier, which is provided with, to be exposed
The opening of the contact pad；
Metal level positioned at first insulating barrier and contact pad upper surface；And
The second insulating barrier positioned at first insulating barrier and metal level upper surface, second insulating barrier is provided with exposure
Go out the opening of the metal level.
Preferably, the re-wiring layer includes：
The laminated construction constituted positioned at plastic packaging layer and chip structure upper surface, by alternate insulating barrier and metal level,
The top layer of the laminated construction be insulating barrier, and the laminated construction first layer metal layer be electrically connected with the contact pad
Connect, adjacent two layers metal level is electrically connected by the metal plug through respective insulation layers, wherein, the alternate number of times is
Not less than 2 times.
Preferably, the soldered ball projection includes the metal column positioned at the re-wiring layer upper surface, and positioned at the gold
Belong to the soldered ball of post upper surface.
The present invention also provides a kind of preparation method of fan-out-type wafer level packaging structure, and the preparation method includes：
1) carrier is provided, an adhesive layer is formed in the upper surface of the carrier；
2) heat dissipating layer is formed in the adhesive layer upper surface；
3) grafting material is formed in the heat dissipating layer upper surface, and photoetching is carried out to the grafting material, is connect with being formed
Close layer；
4) chip structure is formed in the bonding layer upper surface, the chip structure includes bare chip and positioned at the naked core
The contact pad being electrically connected on piece and with the bare chip, wherein, surface where the contact pad is chip structure
Upper surface, and the chip structure upper surface away from the bonding layer；
5) in the heat dissipating layer upper surface, bonding layer and chip structure sidewall surfaces formation plastic packaging layer；
6) re-wiring layer is formed in plastic packaging layer and chip structure upper surface, wherein, the re-wiring layer and institute
Contact pad is stated to be electrically connected；
7) soldered ball projection is formed in the re-wiring layer upper surface, the soldered ball projection is carried out with the re-wiring layer
Electrical connection；
8) carrier and adhesive layer are removed；
9) wafer is carried out to structure described in 8) and sticks piece and cutting scribing, multiple encapsulating structure chips are obtained.
Preferably, the preparation method is additionally included between the re-wiring layer and soldered ball projection and forms Underbump metallization
The step of layer, the step is included in the re-wiring layer upper surface and forms Underbump metallization material, and under the projection
Metal material carries out photoetching, to form Underbump metallization layer, wherein, the Underbump metallization layer is carried out with the re-wiring layer
Electrical connection.
Preferably, the heat dissipating layer is formed using spin coating proceeding or bonding technology in 2).
Preferably, using compressing and forming process, transfer shaping technology, hydraulic seal moulding process, vacuum lamination work in 5)
Skill or spin coating proceeding form the plastic packaging layer.
Preferably, the method for the re-wiring layer is formed in 6) to be included：
6.1) the first insulating barrier is formed in plastic packaging layer and chip structure upper surface, and first insulating barrier is carried out
Photoetching, to expose the contact pad；
6.2) in first surface of insulating layer and contact pad forming metal layer on surface, and light is carried out to the metal level
Carve, to expose first insulating barrier；
6.3) in first insulating barrier and layer on surface of metal the second insulating barrier of formation, and second insulating barrier is carried out
Photoetching, to expose the metal level.
Preferably, the method for the re-wiring layer is formed in 6) to be included：
The laminated construction of insulating barrier and metal level, the lamination are alternatively formed in plastic packaging layer and chip structure upper surface
The top layer of structure be insulating barrier, and the laminated construction first layer metal layer be electrically connected with the contact pad, it is adjacent
Two metal layers are electrically connected by the metal plug through respective insulation layers, wherein, the alternate number of times is not less than 2
It is secondary.
Preferably, the step of soldered ball projection is formed in 9) includes first forming metal column in the re-wiring layer upper surface,
Then soldered ball is formed in the metal column upper surface.
As described above, fan-out-type wafer level packaging structure of the present invention and preparation method thereof, has the advantages that：
1st, heat dissipating layer is formed in the side of chip structure in encapsulation process of the present invention, using relatively thin radiating layer film to institute
State chip structure to be radiated, it is to avoid the step of existing process installs fin at the encapsulating structure back side that encapsulation is completed, letter
While changing manufacture craft, reduce cost, the size of device is substantially reduced.
2nd, the chip structure is radiated using heat dissipating layer, the more existing fin effect of its radiating effect is more preferable.
3rd, by forming a bonding layer between the heat dissipating layer and chip structure, using the bonding layer not only realize by
The chip structure is bonded on the heat dissipating layer, the heat transfer also produced the chip structure by the bonding layer to institute
State on heat dissipating layer, and then radiated using heat dissipating layer.
Brief description of the drawings
Fig. 1~Figure 10 is shown as each making step schematic diagram of encapsulating structure of the present invention.
Component label instructions
1 carrier
2 adhesive layers
3 heat dissipating layers
4 bonding layers
5 chip structures
51 bare chips
52 contact pads
6 plastic packagings layer
7 re-wiring layers
71 first insulating barriers
72 metal levels
73 second insulating barriers
8 Underbump metallizations layer
9 soldered ball projections
91 metal columns
92 soldered balls
10 bearing films
1)~9) step
6.1)~6.3) step
Embodiment
Embodiments of the present invention are illustrated by particular specific embodiment below, those skilled in the art can be by this explanation
Content disclosed by book understands other advantages and effect of the present invention easily.
Fig. 1 is referred to Figure 10.It should be clear that structure, ratio, size depicted in this specification institute accompanying drawings etc., is only used
To coordinate the content disclosed in the specification of carrier 1, so that those skilled in the art is understood with reading, this hair is not limited to
Bright enforceable qualifications, therefore do not have technical essential meaning, the modification of any structure, the change of proportionate relationship or size
Adjustment, in the case where not influenceing of the invention effect that can be generated and the purpose that can reach, all should still fall disclosed
Technology contents obtain and can cover in the range of.Meanwhile, in this specification it is cited as " on ", " under ", "left", "right", " in
Between " and " one " etc. term, be merely convenient to understanding for narration, and be not used to limit enforceable scope of the invention, its is relative
Relation is altered or modified, under without essence change technology contents, when being also considered as enforceable category of the invention.
Embodiment one
As shown in Figures 1 to 10, the present embodiment provides a kind of preparation method of fan-out-type wafer level packaging structure, the system
Preparation Method includes：
1) carrier 1 is provided, an adhesive layer 2 is formed in the upper surface of the carrier 1；
2) heat dissipating layer 3 is formed in the upper surface of adhesive layer 2；
3) grafting material is formed in the upper surface of heat dissipating layer 3, and photoetching is carried out to the grafting material, is connect with being formed
Close layer 4；
4) chip structure 5 is formed in the upper surface of bonding layer 4, the chip structure 5 includes bare chip 51 and positioned at institute
The contact pad 52 stated on bare chip 51 and be electrically connected with the bare chip 51, wherein, the place table of contact pad 52
Face be chip structure 5 upper surface, and the chip structure 5 upper surface away from the bonding layer 4；
5) in the upper surface of heat dissipating layer 3, bonding layer 4 and the sidewall surfaces of chip structure 5 formation plastic packaging layer 6；
6) re-wiring layer 7 is formed in plastic packaging layer 6 and the upper surface of chip structure 5, wherein, the re-wiring layer 7
It is electrically connected with the contact pad 52；
7) soldered ball projection 9, the soldered ball projection 9 and the re-wiring layer 7 are formed in the upper surface of re-wiring layer 7
It is electrically connected；
8) carrier 1 and adhesive layer 2 are removed；
9) wafer is carried out to structure described in 8) and sticks piece and cutting scribing, multiple encapsulating structure chips are obtained.
Fig. 1 to Figure 10 is referred to below to carry out in detail the preparation method of fan-out-type wafer level packaging structure described in the present embodiment
Describe in detail bright.
As shown in Figure 1 there is provided a carrier 1, an adhesive layer 2 is formed in the upper surface of the carrier 1.
As an example, the material of the carrier 1 includes but is not limited to silicon, glass, silica, ceramics, polymer and gold
Category one or both of more than composite, its shape can for wafer shape, it is square or it is other arbitrarily needed for shape；This reality
Apply example prevents subsequent preparation process SMIS chip architecture 3 from occurring the problems such as rupture, warpage, fracture by the carrier 1.
As an example, the material of the adhesive layer 2 includes but is not limited to adhesive tape, adhesive glue, epoxy resin (Epoxy), silicon
One kind in rubber (silicone rubber), polyimides (PI), polybenzoxazoles (PBO) or benzocyclobutene (BCB)；
Made by (ultraviolet) solidifications of UV or heat cure, for the separating layer as carrier 1 and the chip-packaging structure being subsequently formed.
As shown in Fig. 2 forming a heat dissipating layer 3 in the upper surface of adhesive layer 2.
As an example, one kind that the heat dissipating layer 3 includes but is not limited in graphene, metal-to-metal adhesive or ceramics；By using
Spin coating proceeding or bonding technology are prepared.
Preferably, in the present embodiment, the material of the heat dissipating layer 3 is graphene, is prepared by spin coating proceeding.
(its thermal conductivity factor is respectively it should be noted that for existing frequently-used copper radiating rib and aluminium radiator fin
401W/mK and 237W/mK), graphene has high thermal conductivity factor, about 5300W/mK~6600W/mK, by described
The side of chip structure forms graphene heat dissipating layer, may be such that the hot(test)-spot temperature of the chip structure declines to a great extent, greatly improves
Heat dispersion；And the thinner thickness of graphene film, be conducive to reducing the size of device.
As an example, the thickness of the heat dissipating layer 3 is 1~200um.
Preferably, in the present embodiment, the thickness of the heat dissipating layer 3 is 100um；Certainly, in other embodiments, it is described
The thickness of heat dissipating layer 3 can also be 1um, 35um, 53um, 82um, 110um, 135um, 178um or 200um etc..
It should be noted that the thickness of heat dissipating layer described in the present embodiment is by considering dissipating for the encapsulating structure
The thickness of hot property and encapsulating structure is obtained, if it is desired to obtain more preferable heat dispersion, is radiated described in the present embodiment
The thickness of layer can also be more than 200um.
As shown in figure 3, forming a grafting material in the upper surface of heat dissipating layer 3, and photoetching is carried out to the grafting material,
To form bonding layer 4.
As an example, one kind that the material of the bonding layer 4 includes but is not limited in DAF films, metal-to-metal adhesive or adhesive tape；Also
It can be nanometer processing procedure, dissolve in liquid solution, engagement, any metal composite film of heat conduction function can be realized；For by subsequently
The chip structure 5 of formation is bonded on the heat dissipating layer 3, while the heat transfer that can also produce chip structure 5 dissipates to described
On thermosphere 3.
As shown in figure 4, forming chip structure 5 in the upper surface of bonding layer 4, the chip structure 5 includes bare chip 51
And the contact pad 52 being electrically connected on the bare chip 51 and with the bare chip 51, wherein, the contact pad
52 places surface be chip structure 5 upper surface, and the chip structure 5 upper surface away from the bonding layer 4.
As an example, the contact pad 52 is by one or both of copper, aluminium, nickel, gold, silver, tin, titanium above material group
Into.
As shown in figure 5, in the upper surface of heat dissipating layer 3, bonding layer 4 and the sidewall surfaces of chip structure 5 formation plastic packaging layer 6.
As an example, the material of plastic packaging layer 6 include but is not limited in polyimides, silica gel or epoxy resin one
Kind；Prepared using compressing and forming process, transfer shaping technology, hydraulic seal moulding process, vacuum lamination process or spin coating proceeding
Obtain.
It should be noted that the plastic packaging layer formed by above-mentioned technique, it is tightly enclosed in the bonding layer 4 and chip knot
Structure 5 sidewall surfaces, it is to avoid gap occur in the sidewall surfaces of chip structure 5, are prevented effectively from the appearance of interface debonding, greatly improve
The stability of the encapsulating structure.
As shown in fig. 6, the plastic packaging layer 6 and the upper surface of chip structure 5 formed re-wiring layer 7, wherein, it is described again
Wiring layer 7 is electrically connected with the contact pad 52.
As an example, forming the method for the re-wiring layer includes：
6.1) the first insulating barrier 71 is formed in plastic packaging layer 6 and the upper surface of chip structure 5, and to first insulating barrier
71 carry out photoetching, to expose the contact pad 52；
6.2) in the surface of the first insulating barrier 71 and the forming metal layer on surface 72 of contact pad 52, and to the metal level
72 carry out photoetching, to expose first insulating barrier 71；
6.3) the second insulating barrier 73 is formed in first insulating barrier 71 and the surface of metal level 72, and is insulated to described second
Layer 73 carries out photoetching, to expose the metal level 72.
As another example, forming the method for the re-wiring layer includes：
The laminated construction of insulating barrier and metal level is alternatively formed in plastic packaging layer 6 and the upper surface of chip structure 5, it is described folded
The top layer of Rotating fields be insulating barrier, and the laminated construction first layer metal layer be electrically connected with the contact pad, phase
Adjacent two metal layers are electrically connected by the metal plug through respective insulation layers, wherein, the alternate number of times is not small
In 2 times.
As an example, the material of first, second insulating barrier is silica or PET (polyethylene terephthalates
Ester), prepared by techniques such as spin coating, chemical vapor deposition method (CVD), plasma enhanced CVDs.
As an example, the metal level and the metal plug are by one kind in copper, aluminium, nickel, gold, silver, tin, titanium or two
Above material composition is planted, passes through physical gas-phase deposition (PVD), chemical vapor deposition method (CVD), sputtering, plating or changes
Plating is learned to prepare.
Preferably, in the present embodiment, using the method formation re-wiring layer 7 described in the first example, wherein, it is described heavy
New route layer 7 includes layer of metal layer 72.
As shown in fig. 7, form soldered ball projection 9 in the upper surface of re-wiring layer 7, the soldered ball projection 9 with it is described heavy
New route layer 7 is electrically connected.
As an example, the step of forming soldered ball projection 9 includes first forming metal column in the upper surface of re-wiring layer 7
91, then form soldered ball 92 in the upper surface of metal column 91.
Formed as an example, the preparation method is additionally included between the re-wiring layer 7 and soldered ball projection 9 under projection
The step of metal level 8, the step is included in the upper surface of re-wiring layer 7 and forms Underbump metallization material, and to described
Underbump metallization material carries out photoetching, to form Underbump metallization layer 8, wherein, the Underbump metallization layer 8 and the cloth again
Line layer 7 is electrically connected.
As an example, the Underbump metallization layer 8 and metal column 91 are by one kind in copper, aluminium, nickel, gold, silver, tin, titanium
Or two or more material compositions, pass through physical gas-phase deposition (PVD), chemical vapor deposition method (CVD), sputtering, plating
Or one kind in chemical plating is prepared.
As an example, the soldered ball 92 is made up of one or both of copper, aluminium, nickel, gold, silver, tin, titanium above material,
Prepared by planting ball reflux technique.
As shown in figure 8, removing the carrier 1 and adhesive layer 2.
As an example, removing the carrier 1 and the adhesive layer 2 using grinding technics or reduction process technique etc..
As shown in Figures 9 and 10, wafer is carried out to structure described above and sticks piece and cutting scribing, multiple encapsulating structures are obtained
Chip.
As an example, as shown in figure 9, structure described above is transferred on bearing film 10, and carried out by cutting machine
Scribing is cut, multiple encapsulating structure chips as shown in Figure 10 are obtained.
It should be noted that because heat dissipating layer 3 is film layer, can directly be cut by cutting machine, without to institute
The cutting scribing for stating encapsulating structure produces influence.
Embodiment two
As shown in Figure 10, the present embodiment provides a kind of fan-out-type wafer level packaging structure, and the encapsulating structure includes：
Heat dissipating layer 3；
Bonding layer 4 positioned at the upper surface of heat dissipating layer 3；
Chip structure 5 positioned at the upper surface of bonding layer 4, the chip structure 5 includes bare chip 51 and positioned at described
The contact pad 52 being electrically connected on bare chip 51 and with the bare chip 51, wherein, the place surface of contact pad 52
For the upper surface of chip structure 5, and the chip structure 5 upper surface away from the bonding layer 4；
Positioned at the plastic packaging layer 6 of the upper surface of heat dissipating layer 3, bonding layer 4 and the sidewall surfaces of chip structure 5；
Re-wiring layer 7 positioned at plastic packaging layer 6 and the upper surface of chip structure 5, the re-wiring layer 7 connects with described
Pad 52 is touched to be electrically connected；And
Soldered ball projection 9 positioned at the upper surface of re-wiring layer 7, the soldered ball projection 9 enters with the re-wiring layer 7
Row electrical connection.
As an example, one kind that the material of the heat dissipating layer 3 includes but is not limited in graphene, metal-to-metal adhesive or ceramics.
Preferably, in the present embodiment, the heat dissipating layer 3 is graphene layer；Relative to existing frequently-used copper radiating rib and
For aluminium radiator fin (its thermal conductivity factor is respectively 401W/mK and 237W/mK), graphene has high thermal conductivity factor, about
5300W/mK~6600W/mK, by forming graphene heat dissipating layer in the side of the chip structure, may be such that the chip knot
The hot(test)-spot temperature of structure declines to a great extent, and greatly improves heat dispersion, and the thinner thickness of graphene heat dissipating layer, is conducive to reducing device
The size of part.
As an example, the thickness of the heat dissipating layer 3 is 1~200um.
Preferably, in the present embodiment, the thickness of the heat dissipating layer 3 is 100um；Certainly, in other embodiments, it is described
The thickness of heat dissipating layer 3 can also be 1um, 35um, 53um, 82um, 110um, 135um, 178um or 200um etc..
It should be noted that the thickness of heat dissipating layer described in the present embodiment is by considering dissipating for the encapsulating structure
The thickness of hot property and encapsulating structure is obtained, if it is desired to obtain more preferable heat dispersion, is radiated described in the present embodiment
The thickness of layer can also be more than 200um.
As an example, one kind that the material of the bonding layer 4 includes but is not limited in DAF films, metal-to-metal adhesive or adhesive tape；Also
It can be nanometer processing procedure, dissolve in liquid solution, engagement, any metal composite film of heat conduction function can be realized；For by subsequently
The chip structure 5 of formation is bonded on the heat dissipating layer 3, while the heat transfer that can also produce chip structure 5 dissipates to described
On thermosphere 3.
As an example, the contact pad is by one or both of 52 bronze medals, aluminium, nickel, gold, silver, tin, titanium above material group
Into.
As an example, the material of plastic packaging layer 6 include but is not limited in polyimides, silica gel or epoxy resin one
Kind；By the way that 6 plastic packaging layer is tightly enclosed in into the bonding layer 4 and the sidewall surfaces of chip structure 5, it is to avoid chip structure 5
Sidewall surfaces there is gap, be prevented effectively from the appearance of interface debonding, substantially increase the stability of the encapsulating structure.
As an example, the re-wiring layer 7 includes：
The first insulating barrier 71 positioned at plastic packaging layer 6 and the upper surface of chip structure 5, first insulating barrier 71 is provided with
Expose the opening of the contact pad 52；
Metal level 72 positioned at first insulating barrier 71 and the upper surface of contact pad 52；And
On the second insulating barrier 73 positioned at first insulating barrier 71 and the upper surface of metal level 72, second insulating barrier 73
Provided with the opening for exposing the metal level 72.
As another example, the re-wiring layer 7 includes：
The lamination knot constituted positioned at plastic packaging layer 6 and the upper surface of chip structure 5, by alternate insulating barrier and metal level
Structure, the top layer of the laminated construction is insulating barrier, and the first layer metal layer of the laminated construction is carried out with the contact pad
Electrical connection, adjacent two layers metal level is electrically connected by the metal plug through respective insulation layers, wherein, described alternate time
Number is not less than 2 times.
As an example, the material of the insulating barrier is silica or PET (polyethylene terephthalate).
As an example, the metal level and the metal plug are by one kind in copper, aluminium, nickel, gold, silver, tin, titanium or two
Plant above material composition.
Preferably, in the present embodiment, the structure of the re-wiring layer such as the first example, i.e., described re-wiring layer bag
Include layer of metal layer.
As an example, the soldered ball projection 9 includes the metal column 91 positioned at the upper surface of re-wiring layer 7, and it is located at
The soldered ball 92 of the upper surface of metal column 91.
As an example, the metal column 91 is by one or both of copper, aluminium, nickel, gold, silver, tin, titanium above material group
Into.
As an example, the soldered ball 92 is made up of one or both of copper, aluminium, nickel, gold, silver, tin, titanium above material.
As an example, the encapsulating structure also includes under the projection between the re-wiring layer 7 and soldered ball projection 9
Metal level 8, the Underbump metallization layer 8 is electrically connected with the re-wiring layer 7.
In summary, fan-out-type wafer level packaging structure of the invention and preparation method thereof, has the advantages that：
1st, heat dissipating layer is formed in the side of chip structure in encapsulation process of the present invention, using relatively thin radiating layer film to institute
State chip structure to be radiated, it is to avoid the step of existing process installs fin at the encapsulating structure back side that encapsulation is completed, letter
While changing manufacture craft, reduce cost, the size of device is substantially reduced.
2nd, the chip structure is radiated using heat dissipating layer, the more existing fin effect of its radiating effect is more preferable.
3rd, by forming a bonding layer between the heat dissipating layer and chip structure, using the bonding layer not only realize by
The chip structure is bonded on the heat dissipating layer, the heat transfer also produced the chip structure by the bonding layer to institute
State on heat dissipating layer, and then radiated using heat dissipating layer.
So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (16)
1. a kind of fan-out-type wafer level packaging structure, it is characterised in that the encapsulating structure includes：
Heat dissipating layer；
Bonding layer positioned at the heat dissipating layer upper surface；
Chip structure positioned at the bonding layer upper surface, the chip structure include bare chip and on the bare chip,
And the contact pad being electrically connected with the bare chip, wherein, surface where the contact pad is the upper table of chip structure
Face, and the chip structure upper surface away from the bonding layer；
Positioned at the plastic packaging layer of the heat dissipating layer upper surface, bonding layer and chip structure sidewall surfaces；
Re-wiring layer positioned at plastic packaging layer and chip structure upper surface, the re-wiring layer enters with the contact pad
Row electrical connection；And
Soldered ball projection positioned at the re-wiring layer upper surface, the soldered ball projection is electrically connected with the re-wiring layer
Connect.
2. fan-out-type wafer level packaging structure according to claim 1, it is characterised in that the encapsulating structure also includes position
Underbump metallization layer between the re-wiring layer and soldered ball projection, the Underbump metallization layer and the re-wiring layer
It is electrically connected.
3. fan-out-type wafer level packaging structure according to claim 1, it is characterised in that the heat dissipating layer includes graphite
One kind in alkene, metal-to-metal adhesive or ceramics.
4. fan-out-type wafer level packaging structure according to claim 1, it is characterised in that the thickness of the heat dissipating layer is 1
~200um.
5. fan-out-type wafer level packaging structure according to claim 1, it is characterised in that the bonding layer include DAF films,
One kind in metal-to-metal adhesive or adhesive tape.
6. fan-out-type wafer level packaging structure according to claim 1, it is characterised in that it is sub- that the plastic packaging layer includes polyamides
One kind in amine layer, layer of silica gel or epoxy resin layer.
7. fan-out-type wafer level packaging structure according to claim 1, it is characterised in that the re-wiring layer includes：
The first insulating barrier positioned at plastic packaging layer and chip structure upper surface, first insulating barrier is described provided with exposing
The opening of contact pad；
Metal level positioned at first insulating barrier and contact pad upper surface；And
The second insulating barrier positioned at first insulating barrier and metal level upper surface, second insulating barrier, which is provided with, exposes institute
State the opening of metal level.
8. fan-out-type wafer level packaging structure according to claim 1, it is characterised in that the re-wiring layer includes：
The laminated construction constituted positioned at plastic packaging layer and chip structure upper surface, by alternate insulating barrier and metal level, it is described
The top layer of laminated construction be insulating barrier, and the laminated construction first layer metal layer be electrically connected with the contact pad,
Adjacent two layers metal level is electrically connected by the metal plug through respective insulation layers, wherein, the alternate number of times is not
Less than 2 times.
9. fan-out-type wafer level packaging structure according to claim 1, it is characterised in that the soldered ball projection includes being located at
The metal column of the re-wiring layer upper surface, and the soldered ball positioned at the metal column upper surface.
10. a kind of preparation method of fan-out-type wafer level packaging structure, it is characterised in that the preparation method includes：
1) carrier is provided, an adhesive layer is formed in the upper surface of the carrier；
2) heat dissipating layer is formed in the adhesive layer upper surface；
3) grafting material is formed in the heat dissipating layer upper surface, and photoetching is carried out to the grafting material, to form bonding layer；
4) chip structure is formed in the bonding layer upper surface, the chip structure includes bare chip and positioned at the bare chip
Contact pad that is upper and being electrically connected with the bare chip, wherein, surface where the contact pad is the upper of chip structure
Surface, and the chip structure upper surface away from the bonding layer；
5) in the heat dissipating layer upper surface, bonding layer and chip structure sidewall surfaces formation plastic packaging layer；
6) re-wiring layer is formed in plastic packaging layer and chip structure upper surface, wherein, the re-wiring layer connects with described
Tactile pad is electrically connected；
7) soldered ball projection is formed in the re-wiring layer upper surface, the soldered ball projection is electrically connected with the re-wiring layer
Connect；
8) carrier and adhesive layer are removed；
9) wafer is carried out to structure described in 8) and sticks piece and cutting scribing, multiple encapsulating structure chips are obtained.
11. the preparation method of fan-out-type wafer level packaging structure according to claim 10, it is characterised in that the preparation
Method is additionally included between the re-wiring layer and soldered ball projection the step of forming Underbump metallization layer, and the step is included in
The re-wiring layer upper surface forms Underbump metallization material, and carries out photoetching to the Underbump metallization material, to be formed
Underbump metallization layer, wherein, the Underbump metallization layer is electrically connected with the re-wiring layer.
12. the preparation method of fan-out-type wafer level packaging structure according to claim 10, it is characterised in that used in 2)
Spin coating proceeding or bonding technology form the heat dissipating layer.
13. the preparation method of fan-out-type wafer level packaging structure according to claim 10, it is characterised in that used in 5)
Compressing and forming process, transfer shaping technology, hydraulic seal moulding process, vacuum lamination process or spin coating proceeding form the modeling
Sealing.
14. the preparation method of fan-out-type wafer level packaging structure according to claim 10, it is characterised in that formed in 6)
The method of the re-wiring layer includes：
6.1) the first insulating barrier is formed in plastic packaging layer and chip structure upper surface, and light is carried out to first insulating barrier
Carve, to expose the contact pad；
6.2) in first surface of insulating layer and contact pad forming metal layer on surface, and photoetching is carried out to the metal level,
To expose first insulating barrier；
6.3) in first insulating barrier and layer on surface of metal the second insulating barrier of formation, and light is carried out to second insulating barrier
Carve, to expose the metal level.
15. the preparation method of fan-out-type wafer level packaging structure according to claim 10, it is characterised in that formed in 6)
The method of the re-wiring layer includes：
The laminated construction of insulating barrier and metal level, the laminated construction are alternatively formed in plastic packaging layer and chip structure upper surface
Top layer be insulating barrier, and the laminated construction first layer metal layer be electrically connected with the contact pad, adjacent two layers
Metal level is electrically connected by the metal plug through respective insulation layers, wherein, the alternate number of times is not less than 2 times.
16. the preparation method of fan-out-type wafer level packaging structure according to claim 10, it is characterised in that formed in 9)
The step of soldered ball projection, includes first forming metal column in the re-wiring layer upper surface, then in metal column upper surface shape
Into soldered ball.
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| CN112509998A (en) * | 2020-11-18 | 2021-03-16 | 杰群电子科技（东莞）有限公司 | Wafer-level packaging process for high-power semiconductor product and semiconductor product |
| CN114121888A (en) * | 2021-11-19 | 2022-03-01 | 华天科技（昆山）电子有限公司 | Fan-out type ultrathin packaging structure of chip and manufacturing method thereof |
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| CN115763400A (en) * | 2022-11-24 | 2023-03-07 | 成都海光集成电路设计有限公司 | Chip fan-out packaging method and chip fan-out packaging part |
| CN116093046A (en) * | 2023-04-10 | 2023-05-09 | 北京华封集芯电子有限公司 | Preparation method of single chip and chip structure |
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