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WO2024065693A1 - Procédé et dispositif de génération de motif de test de compression - Google Patents

Procédé et dispositif de génération de motif de test de compression Download PDF

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Publication number
WO2024065693A1
WO2024065693A1 PCT/CN2022/123320 CN2022123320W WO2024065693A1 WO 2024065693 A1 WO2024065693 A1 WO 2024065693A1 CN 2022123320 W CN2022123320 W CN 2022123320W WO 2024065693 A1 WO2024065693 A1 WO 2024065693A1
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column vector
interval
maximally
vector
matrix
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PCT/CN2022/123320
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English (en)
Chinese (zh)
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王泽中
王幸
王乃行
黄宇
张威威
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华为技术有限公司
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Priority to PCT/CN2022/123320 priority Critical patent/WO2024065693A1/fr
Publication of WO2024065693A1 publication Critical patent/WO2024065693A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers

Definitions

  • Embodiments of the present application relate to the field of integrated circuits, and more specifically, to a method and apparatus for generating a compressed test vector.
  • test vectors are needed to test the chip.
  • a technology for generating compressed test vectors namely test compression technology, has been derived.
  • test compression technology in the test vector generation process will bring many additional software solution power consumption and automatic test pattern generation (ATPG) tool performance issues.
  • vector compaction technology is usually basically used, that is, the ATPG tool first generates fault detection stimuli and then uses the compressed increment solution solution.
  • the implicit values in the compressor increase, which will lead to a decrease in the success rate of vector compaction and a large number of test vectors; at the same time, the unsuccessful fault detection stimuli need to be regenerated in the subsequent vector compaction process, which also introduces a lot of software power consumption.
  • the commonly used Gaussian elimination technology calculates the compressed implicit values on the irrelevant bits and updates them to the background of vector compaction to improve the success rate of vector compaction.
  • the Gaussian elimination technology consumes a lot of power, resulting in a low efficiency in the process of generating compressed test vectors.
  • the embodiments of the present application provide a method and device for generating compressed test vectors, which can greatly reduce the power consumption of test vector generation and improve the efficiency of generating compressed test vectors while increasing the success rate of test vector merging.
  • a method for generating a compressed test vector comprising: obtaining a first linear correlation matrix and a first maximally irrelevant group according to a decompression matrix corresponding to a chip under test, wherein the decompression matrix is a matrix corresponding to a decompression circuit structure of the chip under test; filling a first target bit in a first background vector with an implicit value according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector, wherein the first target bit includes all or part of the irrelevant bits in the first background vector; and generating a compressed test vector according to the second background vector.
  • the above method generates a compressed test vector after filling the first background vector with an implicit value, that is, updates the first background vector, thereby avoiding the problem of subsequent merging and compression conflicts caused by the fact that the value that should be determined by the compression operation in the first background vector is not determined. While increasing the success rate of test vector merging, it can greatly reduce the power consumption of test vector generation and improve the efficiency of generating compressed test vectors.
  • filling the first target bit in the first background vector with an implicit value according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector includes: determining first target bit information indicating the first target bit according to the first linear correlation matrix and the first maximally irrelevant group, the first target bit information being the second linear correlation matrix; and filling the first target bit with an implicit value according to the first target bit information to obtain a second background vector.
  • the linear correlation matrix By using a linear correlation matrix to determine which irrelevant bits need to be filled with implicit values, and the linear correlation matrix can be updated according to the original linear correlation matrix of the decompressed matrix, the filling of implicit values can be flexibly implemented dynamically, thereby improving the efficiency of generating compressed test vectors.
  • the first target bit information indicating the first target bit is determined based on the first linear correlation matrix and the first maximally irrelevant group
  • the first target bit information is a second linear correlation matrix, including: according to the decompression matrix, obtaining the second maximally irrelevant group of the coefficient matrix of the first linear equation group corresponding to the first background vector, the first linear equation group including the decompression equation corresponding to the first background vector; according to the first maximally irrelevant group, adding the orthogonal complement of the second maximally irrelevant group to the second maximally irrelevant group to obtain a third maximally irrelevant group; determining the second linear correlation matrix based on the third maximally irrelevant group, the first maximally irrelevant group and the first linear correlation matrix.
  • the linear correlation matrix By using a linear correlation matrix to determine which irrelevant bits need to be filled with implicit values, and the linear correlation matrix can be updated according to the original linear correlation matrix of the decompressed matrix and the background vector that needs to be filled, the filling of implicit values can be flexibly implemented dynamically, thereby improving the efficiency of generating compressed test vectors.
  • filling the first target bit with an implicit value based on the first target bit information includes: determining the position of the first target bit based on whether the elements in the second linear correlation matrix are 1, the irrelevant bits in the first target bit corresponding one-to-one to the elements in the second linear correlation matrix; and filling the implicit value into the determined position of the first target bit based on the decompression matrix and the first background vector.
  • filling an implicit value into the first target bit in the first background vector according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector includes: determining first target bit information indicating the first target bit according to the first maximally irrelevant group, the first target bit information being a target column vector interval in the first background vector; and filling an implicit value in the first target bit according to the first target bit information to obtain a second background vector.
  • the background vector is updated, and subsequent partial conflict problems are avoided. While taking into account the software power consumption, the efficiency of generating compressed test vectors is improved.
  • the first background vector includes at least one column vector
  • the first maximally irrelevant group corresponds one-to-one to the column vector
  • determining the first target bit information indicating the first target bit based on the first maximally irrelevant group includes: determining the target column vector interval based on the ranks of multiple of the first maximally irrelevant groups, the target column vector interval including at least one continuous column vector.
  • determining the target column vector interval based on the ranks of multiple first maximal independent groups includes: obtaining at least one second linear equation group based on the decompression matrix and the first background vector, the second linear equation group including the decompression equations of the first background vector, and the second linear equation group corresponding one-to-one to continuous column vector intervals in the first background vector; determining at least one first column vector interval based on the at least one second linear equation group, the number of linear independent equations of the second linear equation group corresponding to the first column vector interval being greater than a first threshold; determining a second column vector interval based on the at least one first column vector interval, the second column vector interval being the column vector interval with the largest number of column vectors included in the at least one first column vector interval; determining the target column vector interval based on the second column vector interval, the target column vector interval including the second column vector interval.
  • determining the target column vector interval based on the second column vector interval includes: determining that the rank of at least one of the first maximally irrelevant groups corresponding to the second column vector interval is a first value; judging whether the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is equal to the first value; updating the second column vector interval to a third column vector interval based on the judgment result; determining that the rank of at least one of the first maximally irrelevant groups corresponding to a fourth column vector interval is equal to the number of linearly independent equations of the second linear equation group corresponding to the fourth column vector interval, and the fourth column vector interval is an adjacent column vector interval of the third column vector interval; and determining the target column vector interval to be the union of the third column vector interval and the fourth column vector interval.
  • updating the second column vector interval to a third column vector interval based on the judgment result includes: when the judgment result is that the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is not equal to the first numerical value, determining the values of some constant terms in the linearly independent equations so that the second column vector interval is updated to the third column vector interval, and the number of linearly independent equations of the second linear equation group corresponding to the third column vector interval is equal to the first numerical value.
  • filling the first target bit with an implicit value based on the first target bit information includes: calculating the implicit value of the irrelevant bits in the target column vector interval based on the target column vector interval and the decompression matrix; and filling the implicit value into the first target bit.
  • the product of the first linear correlation matrix and the first maximally independent group corresponds to a matrix block row of the decompressed matrix; or, the product of the first linear correlation matrix and the first maximally independent group corresponds to the decompressed matrix.
  • a device for generating a compressed test vector comprising a processing module, the processing module being used to: obtain a first linear correlation matrix and a first maximally irrelevant group according to a decompression matrix corresponding to a chip under test, wherein the decompression matrix is a matrix corresponding to a decompression circuit structure of the chip under test; fill a first target bit in a first background vector with an implicit value according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector, the first target bit including all or part of the irrelevant bits in the first background vector; and generate a compressed test vector according to the second background vector.
  • the processing module is specifically used to: determine first target bit information indicating a first target bit based on the first linear correlation matrix and the first maximally irrelevant group, the first target bit information being a second linear correlation matrix; and fill an implicit value in the first target bit based on the first target bit information to obtain a second background vector.
  • the processing unit is further specifically used to: obtain a second maximally irrelevant group of the coefficient matrix of the first linear equation group corresponding to the first background vector according to the decompression matrix, the first linear equation group including the decompression equation corresponding to the first background vector; add the orthogonal complement of the second maximally irrelevant group to the second maximally irrelevant group according to the first maximally irrelevant group to obtain a third maximally irrelevant group; determine the second linear correlation matrix according to the third maximally irrelevant group, the first maximally irrelevant group and the first linear correlation matrix.
  • the processing unit is further specifically used to: determine the position of the first target bit according to whether the elements in the second linear correlation matrix are 1, and the irrelevant bits in the first target bit correspond one-to-one to the elements in the second linear correlation matrix; fill the determined position of the first target bit with an implicit value according to the decompression matrix and the first background vector.
  • the processing unit is specifically used to: determine first target bit information indicating a first target bit based on the first maximally irrelevant group, the first target bit information being a target column vector interval in the first background vector; and fill an implicit value in the first target bit based on the first target bit information to obtain a second background vector.
  • the first background vector includes at least one column vector
  • the first maximally irrelevant group corresponds one-to-one to the column vector
  • the processing unit is further specifically used to: determine the target column vector interval based on the ranks of multiple first maximally irrelevant groups, and the target column vector interval includes at least one continuous column vector.
  • the processing unit is further specifically used to: obtain at least one second linear equation group based on the decompression matrix and the first background vector, the second linear equation group including the decompression equation of the first background vector, and the second linear equation group corresponding one-to-one to the continuous column vector interval in the first background vector; determine at least one first column vector interval based on the at least one second linear equation group, the number of linearly independent equations of the second linear equation group corresponding to the first column vector interval is greater than a first threshold; determine a second column vector interval based on the at least one first column vector interval, the second column vector interval being the column vector interval with the largest number of column vectors included in the at least one first column vector interval; determine the target column vector interval based on the second column vector interval, the target column vector interval including the second column vector interval.
  • the processing unit is further specifically used to: determine that the rank of at least one of the first maximally irrelevant groups corresponding to the second column vector interval is a first value; determine whether the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is equal to the first value; based on the judgment result, update the second column vector interval to the third column vector interval; determine that the rank of at least one of the first maximally irrelevant groups corresponding to the fourth column vector interval is equal to the number of linearly independent equations of the second linear equation group corresponding to the fourth column vector interval, and the fourth column vector interval is an adjacent column vector interval of the third column vector interval; determine that the target column vector interval is the union of the third column vector interval and the fourth column vector interval.
  • the processing unit is also used to: when the judgment result is that the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is not equal to the first numerical value, determine the values of some constant terms in the linearly independent equations so that the second column vector interval is updated to the third column vector interval, and the number of linearly independent equations of the second linear equation group corresponding to the third column vector interval is equal to the first numerical value.
  • the processing unit is also used to: calculate the implicit value of the irrelevant bits in the target column vector interval based on the target column vector interval and the decompression matrix; and fill the implicit value into the first target bit.
  • the product of the first linear correlation matrix and the first maximally independent group corresponds to a matrix block row of the decompressed matrix; or, the product of the first linear correlation matrix and the first maximally independent group corresponds to the decompressed matrix.
  • a computer program product which includes instructions. When the instructions are executed on a computer, the computer executes the method described in the first aspect or any implementation of the first aspect.
  • a device for generating a compressed test vector comprising a processor and a memory, wherein the memory is used to store a program, and the processor is used to call and run the program from the memory to execute the method in the above-mentioned first aspect or any possible implementation manner of the first aspect.
  • a computer-readable storage medium comprising a computer program, which, when executed on a computer, enables the computer to execute the method for testing control software in the first aspect or any possible implementation of the first aspect.
  • FIG. 1 is a schematic block diagram of a chip design and manufacturing process applicable to an embodiment of the present application.
  • FIG. 2 is a schematic block diagram of a process for generating a compressed test vector applicable to an embodiment of the present application.
  • FIG3 is a schematic diagram of a method for generating a compressed test vector provided in an embodiment of the present application.
  • FIG. 4 is a schematic diagram of another exemplary method for generating a compressed test vector provided in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of another exemplary method for generating a compressed test vector provided in an embodiment of the present application.
  • FIG. 6 is a schematic block diagram of an apparatus for generating a compressed test vector according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of the hardware structure of an apparatus for compressing test vectors according to an embodiment of the present application.
  • Chips which can also be called integrated circuits (ICs), or can be understood as the carrier of integrated circuits, are usually a way to miniaturize circuits and are often manufactured on the surface of semiconductor wafers.
  • the process 100 of chip design and manufacturing can usually be divided into three parts: design part 101, manufacturing part 102, and packaging and testing part 103.
  • design part 101 design part 101
  • manufacturing part 102 manufacturing part 102
  • packaging and testing part 103 packaging and testing part 103.
  • DFT design for testability
  • the specific chip testing process mainly includes: first, generate test patterns through automatic test pattern generation (ATPG) tools; then input the test patterns into the chip under test through automatic test equipment (ATE); finally, compare the test response of the chip under test with the expected response to see if it is consistent, to know whether the chip has defects.
  • ATG automatic test pattern generation
  • ATE automatic test equipment
  • test compression technology is used in the packaging test part of the chip.
  • the generation process of the compressed test vector can be: (1)
  • the ATPG tool models the possible faults of the chip (such as the faults in the fault list) and generates a fault detection stimulus.
  • the fault detection stimulus includes one or more bits, which include fixed bits and don't care bits.
  • the value filled with the fixed bit is a valid value (specified bit), and the value filled with the don't care bit is a don't care value (don't care bit).
  • the valid value can be understood as a fixed value in the fault detection stimulus, which is used to detect the corresponding fault.
  • the don't care value can be understood as a value that can be arbitrarily set in the fault detection stimulus, for example, it can be any value between 0 and 1.
  • n fault detection stimuli ( a1 , a2 , ..., an ) are generated, wherein each box represents a bit, and a box filled with a pattern indicates that the bit is a fixed bit, and a box without a pattern fill indicates that the bit is a don't care bit.
  • each fault detection stimulus shown in FIG2 includes only 10 bits. In the actual generated fault detection stimulus, the bits included can be in the millions, and the data scale is relatively large. It should be understood that one fault detection stimulus corresponds to one fault;
  • n fault detection stimuli (a 1 , a 2 , ..., a n ) are merged and compressed one by one, that is, two fault detection stimuli in the n fault detection stimuli are merged to obtain a background vector (background merged cube), and then compressed to obtain a compressed background vector, ensuring that the merged fault detection stimuli can be compressed successfully, and then adding another fault detection stimuli to the background vector obtained by merging the two fault detection stimuli, that is, merging and compressing the three fault detection stimuli, and so on.
  • the n fault detection stimuli can finally be merged to obtain a background vector A, and then the background vector is compressed to obtain a compressed background vector A'.
  • the number of elements included in the background vector A is the same as the number of elements included in a fault detection stimuli, and the number of elements included in the compressed background vector A' is less than the number of elements included in the background vector A.
  • merging is to merge multiple fault detection stimuli into one, that is, merging is to reduce the number of fault detection stimuli, and compression is to shorten the length of the fault detection stimuli, that is, compression is to reduce the number of elements in the fault detection stimuli, and the merging process is accompanied by compression, or it can be called incremental compression during the merging process, that is, each time a fault detection stimulus is merged, it is necessary to check whether incremental compression can be successfully performed to ensure that the merged state can be compressed successfully;
  • a fault detection stimulus is generated, and then the generated fault detection stimulus increments are merged and compressed into the compressed background vector to generate a compressed test pattern. For example, as shown in FIG2 , based on the background vector A, a fault detection stimulus b1 is generated, and then A and b1 are merged and compressed. After the compression is successful, a fault detection stimulus b2 is generated based on the background vector generated by merging A and b1 . Then the background vector generated by merging A and b1 and b2 are merged and compressed. After the compression is successful, a fault detection stimulus b3 is generated based on the background vector generated by merging b2 .
  • a background vector B is obtained by merging A and m fault detection stimuli ( b1 , b2 , ..., bm ).
  • a compressed test vector B' is obtained.
  • the compressed test vector may be stored in ATE. After ATE injects the compressed test vector into the chip under test, the compressed test vector is decompressed by a decompression circuit on the chip under test and then input into the circuit under test in the chip under test.
  • the compressed test vector B' may be injected into the chip under test and then input into the circuit under test through a decompression circuit to be restored to a merged vector of the n fault detection stimuli ( a1 , a2 , ..., an ) and the m fault detection stimuli ( b1 , b2 , ..., bm ), that is, a merged background vector B.
  • the compressed test vector may also be referred to as a compressed seed. It should also be understood that the generation process of the compressed test vector may be performed by an ATPG tool. It should also be understood that in the generation process of the compressed test vector, the vector obtained by merging the fault detection stimulus may be referred to as a background vector, and after further compression, the vector obtained may be referred to as a compressed background vector, and the vector finally obtained may be referred to as a compressed test vector, that is, after merging the compressed background vector and compressing the last fault detection stimulus, the vector obtained may be referred to as a compressed test vector.
  • the fixed bits in the fault detection stimulus generated by the ATPG tool correspond to the don't care bits before the background vector is compressed, that is, they correspond to the don't care bits of the background vector obtained by merging the fault detection stimulus.
  • the fill value of the don't care bits before the background vector is compressed may be determined due to the compression operation.
  • the fill value of the don't care bits before the background vector is compressed can be called an implied value.
  • the fault detection stimulus generated by the ATPG tool may not satisfy the compression operation and therefore cannot be incrementally merged into the background vector, thereby causing a conflict and increasing the power consumption of dynamic compaction.
  • the background vector B restored in the above-mentioned circuit under test corresponds to a scan chain in the circuit under test.
  • a scan chain includes at least one scan cell.
  • the value of each scan cell is a value in the background vector B, that is, an element in the vector.
  • the vector input to the circuit under test is the compressed test vector B'. If each compressed value in the compressed test vector B' is regarded as a free variable, each value in the background vector B can be linearly represented by part of the compressed value or all of the compressed value in the compressed test vector B' due to the compression operation, that is, the value of each scan cell can be linearly represented by the input free variable, and the number of scan cells is much larger than the number of free variables. Therefore, there are a lot of linear correlations between the multiple equations corresponding to the multiple scan cells, that is, the values on many scan cells can be linearly represented by the values on other scan cells.
  • an embodiment of the present application proposes a method for generating test vectors, which can greatly reduce the power consumption of test vector generation while increasing the success rate of test vector merging.
  • Matrix A set of complex or real numbers arranged in a rectangular array. For example, a table of m ⁇ n numbers with m rows and n columns is called a matrix of m rows and n columns, or m ⁇ n matrix for short. A matrix with n rows and columns is called an n-order matrix, or an n-order square matrix. In the embodiments of the present application, when the test vectors involved are represented by matrices, the matrix elements mainly include 0 and 1.
  • Vector group A set of column vectors or row vectors of the same dimension.
  • a matrix can be understood as consisting of vector groups.
  • Maximal independent group generally refers to the maximal linearly independent group, which is the linearly independent vector group with the largest number of vectors in the linear space. For example, its definition can be: suppose there is a vector group A: ⁇ 1, ⁇ 2, ⁇ 3, ..., ⁇ s, if r vectors ⁇ 1, ⁇ 2, ..., ⁇ r can be selected from A, satisfying the vector group A0: ⁇ 1, ⁇ 2, ..., ⁇ r are linearly independent, and any vector in the vector group A can be linearly represented by several vectors in the vector group A0, then the vector group A0 is called a maximal linearly independent group of the vector group A, abbreviated as the maximal independent group.
  • the rank of a matrix is the highest order of its non-zero minors
  • the rank of a vector group is the number of vectors contained in its maximal independent group.
  • the matrix is said to be full rank.
  • the vector group when the number of vectors contained in the maximal independent group is equal to the number of vector groups, the vector group is said to be full rank.
  • FIG3 shows a schematic diagram of a method for generating a compressed test vector provided in an embodiment of the present application.
  • the method 300 includes:
  • the chip under test is a chip for testing with compressed test vectors
  • the chip under test includes a decompression circuit, which can decompress the compressed test vectors.
  • the above step S301 can be performed by an ATPG tool, which can obtain the decompression circuit structure of the chip under test, and then model according to the decompression circuit structure to extract the decompression matrix.
  • the decompression circuit structure is the decompression circuit structure of the test circuit of the chip to be tested. Therefore, when the ATPG tool generates fault detection stimuli, and merges and compresses the fault detection stimuli, the fault detection stimuli are merged and compressed according to the relevant characteristics of the decompression circuit structure, so that the decompression circuit can subsequently completely decompress the merged and compressed fault detection stimuli, thereby improving the test efficiency of the chip.
  • the decompression circuit structure is a linear-based decompression circuit structure.
  • the decompression circuit structure includes a ring generator and a phase shifter, so that a decompression matrix can be constructed according to the mapping relationship between the ring generator and the phase shifter.
  • the ring generator includes a plurality of shift registers, and the mapping relationship corresponding to the ring generator can be expressed by the following formula (1):
  • r t represents the value of the shift register at time t
  • R f represents the linear matrix corresponding to the feedback connection structure of the shift register itself
  • r t-1 represents the value of the shift register in the ring generator at time t-1
  • R v represents the linear matrix corresponding to the connection structure between the input pin and the shift register
  • x t represents the compressed value injected by the tth tap
  • the linear matrix corresponding to the phase shifter is P
  • the shift value of the shift register included in the ring generator at time t can be expressed by the following formula (2):
  • b ts represents the shift value of the shift register, or b ts represents the background vector obtained after the combined fault detection stimulus, r ts represents the value of the shift register at time ts, s represents the number of initialization taps when the compressed test vector (i.e., compressed solution) is input into the decompression circuit beat by beat, or s represents the number of initialization taps before the effective tap when the compressed test vector is input into the decompression circuit.
  • the following formula decompression mapping formula (3) can be obtained.
  • the first matrix on the right side of the formula (3) is the decompression matrix.
  • the corresponding relationship between the matrix b and the matrix x can be obtained, that is, the corresponding relationship between the value in the background vector and the compressed value of the background vector can be obtained.
  • the decompression matrix E can be defined as the following formula (4):
  • the decompressed matrix can be decomposed into a first linear correlation matrix and a first maximally independent group.
  • the first linear correlation matrix and the first maximally independent group can be hierarchically constructed.
  • the first linear correlation matrix can also be called a first linear correlation table.
  • the product of the first linear correlation matrix and the first maximally irrelevant group corresponds to the matrix block row of the decompressed matrix. It should be understood that the product of the two corresponding to the matrix block row of the decompressed matrix may mean that the product is the same as the matrix block row, or that the deviation of the product from the matrix block row is within a preset range, or that the product is the same as the matrix block row after being multiplied by a certain coefficient, and the present application does not limit this.
  • a matrix block row of a decompressed matrix corresponds to a column vector of a background vector, such as bi , and a column vector can also be called a test cycle. That is, the maximally irrelevant group and the linear correlation matrix within a test cycle can be obtained.
  • the product of the first linear correlation matrix and the first maximally irrelevant group corresponds to the decompression matrix.
  • the product of the two corresponding to the decompression matrix may mean that the product is the same as the decompression matrix, or that the deviation between the product and the decompression matrix is within a preset range, or that the product is the same as the decompression matrix after being multiplied by a certain coefficient, and the present application does not limit this.
  • the maximally irrelevant group of the test cycle set that is, the first maximally irrelevant group
  • the maximally irrelevant group M is calculated for ⁇ i ⁇ 1 ⁇ i ⁇ m
  • the linear correlation matrix of the test cycle set that is, the first linear correlation matrix, such as D
  • the first background vector may be any background vector in Fig. 2.
  • the first background vector may be any background vector in a static compaction process and a dynamic compaction process.
  • the first background vector may be a background vector obtained after the ATPG tool merges at least one fault detection stimulus.
  • the first background vector includes fixed bits and irrelevant bits, and the irrelevant bits include irrelevant bits determined by the compression operation, that is, when the first background vector is compressed, some or all of the irrelevant bits in the first background vector will be determined.
  • the positions and determined values of some or all of the irrelevant bits that have been determined, that is, implicit values it is necessary to determine the positions and determined values of some or all of the irrelevant bits that have been determined, that is, implicit values, and then fill the implicit values into the first target bit.
  • the first target bit in the first background vector with an implicit value according to the first linear correlation matrix and/or the first maximally independent group to obtain the second background vector may be any one of the following ways 1 and 2.
  • way 1 can be called a dynamic filling algorithm
  • way 2 can be called a static filling algorithm.
  • multiple background vectors will be generated.
  • way 1 and way 2 can be used alone.
  • the embodiment of the present application does not limit the number of times way 1 or way 2 is used; way 1 and way 2 can also be used in combination.
  • the embodiment of the present application does not limit the order of their use and the number of times they are used.
  • S304 Determine first target bit information indicating the first target bit according to the first linear correlation matrix and the first maximally independent group, where the first target bit information is the second linear correlation matrix.
  • the first target bit information can be used to indicate the first target bit, or in other words, the first target bit information can be used to indicate the position of the first target bit, that is, the first target bit information can be used to indicate which irrelevant bits need to be filled with implicit values.
  • the first target bit information is a matrix, namely, a second linear correlation matrix.
  • the second linear correlation matrix can also be called a second linear correlation table.
  • the method for determining the first target bit information may be, that is, the method for determining the second linear correlation matrix may be, based on the decompression matrix, obtaining the second maximally irrelevant group of the coefficient matrix of the first linear equation group corresponding to the first background vector, the first linear equation group including the decompression equation corresponding to the first background vector; based on the first maximally irrelevant group, adding the orthogonal complement of the second maximally irrelevant group to the second maximally irrelevant group to obtain a third maximally irrelevant group; and determining the second linear correlation matrix based on the third maximally irrelevant group, the first maximally irrelevant group and the first linear correlation matrix.
  • the second linear correlation matrix can be called the updated first linear correlation matrix, which is not limited in this application.
  • the second background vector is a vector obtained by updating the first background vector, that is, a background vector obtained by filling the irrelevant bits of the first background vector with implicit values.
  • a fault detection stimulus can be generated according to the updated first background vector, and the generated fault detection stimulus can avoid conflicts when merging and compressing.
  • the first target bit information is the second linear correlation matrix.
  • the position of the first target bit can be determined based on whether the elements in the second linear correlation matrix are 1, and then the implicit value is filled into the determined position of the first target bit based on the decompression matrix and the first background vector, wherein the irrelevant bits in the first target bit correspond one-to-one to the elements in the second linear correlation matrix.
  • each row vector in the updated decompressed matrix linear correlation table corresponds to a bit in the first background vector, and each row vector includes one or more elements, and the value of the element can be 0 or 1.
  • the element is 1, it means that the corresponding bit can be linearly represented by the linear independent equation group in the second maximal independent group. Therefore, the position of the first target bit can be determined according to the value of the element in the updated decompressed matrix linear correlation table. After determining the position of the first target bit, the value determined on the independent bit, that is, the implicit value, is determined by calculation.
  • Method 2 includes steps S306-S307:
  • S306 Determine first target bit information indicating a first target bit according to the first maximally irrelevant group, where the first target bit information is a target column vector interval in the first background vector.
  • the first background vector includes at least one column vector.
  • bi in the above formula (3) represents a column vector.
  • a column vector can be called a test cycle.
  • the first maximally irrelevant group may be a maximally irrelevant group within a test cycle, such as C i in the above step S301.
  • the first maximally irrelevant group corresponds to a test cycle, that is, the first maximally irrelevant group corresponds to the column vector of the first background vector one-to-one
  • the target column vector interval may be determined according to the ranks of the plurality of first maximally irrelevant groups, and the target column vector interval includes at least one column vector.
  • the target column vector interval is determined according to the ranks of multiple first maximal independent groups as follows: at least one second linear equation group is obtained according to the decompression matrix and the first background vector, the second linear equation group includes the decompression equation of the first background vector, and the second linear equation group corresponds one-to-one to the continuous column vector intervals in the first background vector; at least one first column vector interval is determined according to at least one second linear equation group, and the number of linear independent equations of the second linear equation group corresponding to the first column vector interval is greater than a first threshold; a second column vector interval is determined according to at least one first column vector interval, and the second column vector interval is the column vector interval with the largest number of column vectors included in at least one first column vector interval; a target column vector interval is determined according to the second column vector interval, and the target column vector interval includes the second column vector interval.
  • the first threshold may be determined in the following manner: in the process of generating each test vector, the first threshold may adopt different artificial experience values, or may be dynamically adjusted through learning;
  • a method for determining a target column vector interval based on the second column vector interval may be: determining that the rank of at least one first maximally irrelevant group corresponding to the second column vector interval is a first numerical value; determining whether the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is equal to the first numerical value; based on the judgment result, updating the second column vector interval to a third column vector interval; determining that the rank of at least one first maximally irrelevant group corresponding to the fourth column vector interval is equal to the number of linearly independent equations of the second linear equation group corresponding to the fourth column vector interval, and the fourth column vector interval is an adjacent column vector interval of the third column vector interval; determining the target column vector interval to be the union of the third column vector interval and the fourth column vector interval.
  • the method of updating the second column vector interval to the third column vector interval can be: when the number of linearly independent equations corresponding to the second column vector interval is not equal to the first value, determine the value of some constant terms in the linearly independent equations, so that the second column vector interval is updated to the third column vector interval, and the number of linearly independent equations of the second linearly independent equation group corresponding to the third column vector interval is equal to the first value.
  • the second column vector interval includes the same number of column vectors as the third column vector interval, and the difference is that the values on some irrelevant bits in the third column vector interval are determined, that is, the value of the constant term is determined.
  • the above method of determining the value of the constant term may be to randomly assign the value according to the probability of occurrence of the value of the constant term.
  • a specific method for determining a target column vector interval may be: 1) obtaining, according to the decompression matrix, a linear equation of the irrelevant value in each column vector in the first background vector with respect to the compressed value, that is, a linear equation of the element in each test cycle with respect to the compressed value; 2) then calculating the linearly independent equations in each test cycle; 3) then obtaining a test cycle region in which the number of linearly independent equations in the test cycle region is greater than a first threshold, or in other words, obtaining a column vector interval greater than or equal to the first threshold; 4) selecting a first test cycle region from the obtained test cycle region, the first test cycle region being the region with the largest length in the obtained test cycle region, that is, the first column vector interval including the most column vectors, for example (b i , b j ); 5) randomly filling values into irrelevant bits in the first test cycle region so that the first test cycle region is full rank, that is, the number of linearly independent equations in the first column
  • full rank means that the number of linearly independent equations in the decompression equation group of a certain column vector interval in the background vector is equal to the rank of the maximal independent group of the decompression matrix corresponding to the column vector interval, or in other words, the number of vectors included in the maximal independent group of the decompression matrix corresponding to the column vector interval is equal.
  • the implicit value of the irrelevant bit in the target column vector interval can be calculated according to the target column vector interval and the decompression matrix; the implicit value is filled into the first target bit to obtain the second background vector.
  • the second background vector can be obtained by determining part of the value in the first background vector, that is, updating the first background vector, so that after the first background vector is updated, the subsequent conflict problem caused by the partially determined irrelevant bit can be avoided, and the efficiency of generating the compressed test vector can be improved.
  • the second background vector can be directly compressed to generate a compressed test vector, or a fault detection stimulus can be generated based on the second background vector.
  • a compressed test vector is generated.
  • a compressed test vector can be generated after repeating one or more operations similar to the above steps S301-S302. The present application does not limit this.
  • the above method fills the first background vector with implicit values, generates the second background vector, and then generates the compressed test vector, that is, updates the first background vector, thereby avoiding the problem of subsequent merging and compression conflicts caused by the fact that the value that should be determined by the compression operation in the first background vector is not determined, thereby improving the efficiency of generating compressed test vectors.
  • FIG4 is a schematic diagram of an exemplary method for generating a compressed test vector provided by an embodiment of the present application. Specifically, the method 400 includes:
  • the first background vector may be a background vector obtained after a static compaction process, or may be a background vector obtained during a dynamic compaction process, and the present application does not impose any limitation on this.
  • the maximal independent group B1 is a maximal independent group of the coefficient matrix of the linear equation group corresponding to the first background vector, and the linear equation group includes the compression equation of the first background vector.
  • the linear correlation matrix of the decompressed matrix is updated from D to Q.
  • FIG5 shows a schematic diagram of an exemplary method for generating a compressed test vector provided by an embodiment of the present application.
  • the method 500 includes:
  • the first background vector may be a background vector obtained after a static compaction process, or may be a background vector obtained during a dynamic compaction process, and the present application does not impose any limitation on this.
  • the linear equation group corresponding to multiple column vector intervals includes the decompression equation of the background vector, and the rank of the linear equation group corresponding to each column vector interval in the multiple column vector intervals can be called the interval rank, that is, the above step S502 is to obtain multiple interval ranks.
  • S503 Determine whether the rank is greater than a first threshold.
  • S504 Fill in the rank of a column vector interval with the largest number of consecutive column vectors among multiple column vector intervals whose ranks are greater than a first threshold, to be full rank.
  • the full rank interval is updated to be the set of the full rank interval determined in step S504 and its adjacent intervals.
  • the implicit value of the updated full rank interval is calculated and filled into the first background vector to obtain the second background vector.
  • Fig. 6 shows a schematic block diagram of an apparatus 600 for generating a compressed test vector according to an embodiment of the present application.
  • the apparatus 600 can execute the method for generating a compressed test vector according to the embodiment of the present application.
  • the device includes a processing module 601 .
  • the processing module 601 is used to: obtain a first linear correlation matrix and a first maximally irrelevant group according to the decompression matrix corresponding to the chip under test, wherein the decompression matrix is a matrix corresponding to the decompression circuit structure of the chip under test; fill an implicit value into a first target bit in a first background vector according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector, wherein the first target bit includes all or part of the irrelevant bits in the first background vector; and generate a compressed test vector according to the second background vector.
  • FIG7 is a schematic diagram of the hardware structure of a device for compressing test vectors according to an embodiment of the present application.
  • the device 700 for compressing test vectors shown in FIG7 includes a memory 701, a processor 702, a communication interface 703, and a bus 704.
  • the memory 701, the processor 702, and the communication interface 703 are connected to each other through the bus 704.
  • the memory 701 may be a read-only memory (ROM), a static storage device, and a random access memory (RAM).
  • the memory 701 may store a program. When the program stored in the memory 701 is executed by the processor 702, the processor 702 and the communication interface 703 are used to execute the various steps of the method for compressing the test vector of the embodiment of the present application.
  • Processor 702 can adopt a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit (GPU) or one or more integrated circuits to execute relevant programs to implement the functions required to be performed by the units in the device for compressing the test vector of the embodiment of the present application, or to execute the method for compressing the test vector of the embodiment of the present application.
  • CPU central processing unit
  • ASIC application specific integrated circuit
  • GPU graphics processing unit
  • the processor 702 may also be an integrated circuit chip with signal processing capability.
  • each step of the method for compressing test vectors in the embodiment of the present application may be completed by hardware integrated logic circuits in the processor 702 or software instructions.
  • the processor 702 may also be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, or discrete hardware components.
  • DSP digital signal processor
  • FPGA field programmable gate array
  • the methods, steps, and logic diagrams disclosed in the embodiments of the present application may be implemented or executed.
  • the general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.
  • the steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.
  • the software module may be located in a mature storage medium in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc.
  • the storage medium is located in the memory 701, and the processor 702 reads the information in the memory 701, and combines its hardware to complete the functions required to be performed by the units included in the device for compressing the test vector of the embodiment of the present application, or executes the method for compressing the test vector of the embodiment of the present application.
  • the communication interface 703 uses a transceiver such as, but not limited to, a transceiver to implement communication between the device 700 and other devices or a communication network. For example, the traffic data of an unknown device can be obtained through the communication interface 703.
  • a transceiver such as, but not limited to, a transceiver to implement communication between the device 700 and other devices or a communication network. For example, the traffic data of an unknown device can be obtained through the communication interface 703.
  • the bus 704 may include a path for transmitting information between various components of the device 700 (eg, the memory 701 , the processor 702 , and the communication interface 703 ).
  • the device 700 may also include other devices necessary for normal operation. At the same time, according to specific needs, those skilled in the art should understand that the device 700 may also include hardware devices for implementing other additional functions. In addition, those skilled in the art should understand that the device 700 may also only include the devices necessary for implementing the embodiments of the present application, and does not necessarily include all the devices shown in FIG. 7.
  • An embodiment of the present application also provides a computer-readable storage medium that stores program code for execution by a device, wherein the program code includes instructions for executing the steps in the above-mentioned method for compressing test vectors.
  • An embodiment of the present application also provides a computer program product, which includes a computer program stored on a computer-readable storage medium, and the computer program includes program instructions.
  • the program instructions When the program instructions are executed by a computer, the computer executes the above-mentioned method of compressing test vectors.
  • the computer-readable storage medium mentioned above may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.
  • the disclosed systems, devices and methods can be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.
  • Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art.
  • the computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

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Abstract

L'invention concerne un procédé de génération d'un motif de test de compression, comprenant : selon une matrice de décompression correspondant à une puce sous test, l'acquisition d'une première matrice de corrélation linéaire et d'un premier système linéairement indépendant maximal, la matrice de décompression étant une matrice correspondant à une structure de circuit de décompression de ladite puce (S301) ; selon la première matrice de corrélation linéaire et/ou le premier système linéairement indépendant maximal, le remplissage de premiers bits cibles dans un premier motif d'arrière-plan avec une valeur implicite pour obtenir un second motif d'arrière-plan, les premiers bits cibles comprenant la totalité ou certains des bits indépendants dans le premier motif d'arrière-plan (S302) ; et la génération d'un motif de test de compression selon le second motif d'arrière-plan (S303).
PCT/CN2022/123320 2022-09-30 2022-09-30 Procédé et dispositif de génération de motif de test de compression WO2024065693A1 (fr)

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