WO2024065693A1

WO2024065693A1 - Method and device for generating compression test pattern

Info

Publication number: WO2024065693A1
Application number: PCT/CN2022/123320
Authority: WO
Inventors: 王泽中; 王幸; 王乃行; 黄宇; 张威威
Original assignee: 华为技术有限公司
Priority date: 2022-09-30
Filing date: 2022-09-30
Publication date: 2024-04-04

Abstract

A method for generating a compression test pattern, comprising: according to a decompression matrix corresponding to a chip under test, acquiring a first linear correlation matrix and a first maximal linearly independent system, wherein the decompression matrix is a matrix corresponding to a decompression circuit structure of said chip (S301); according to the first linear correlation matrix and/or the first maximal linearly independent system, filling first target bits in a first background pattern with an implicit value to obtain a second background pattern, the first target bits comprising all or some of independent bits in the first background pattern (S302); and generating a compression test pattern according to the second background pattern (S303).

Description

A method and device for generating compressed test vectors

Technical Field

Embodiments of the present application relate to the field of integrated circuits, and more specifically, to a method and apparatus for generating a compressed test vector.

Background technique

During the chip testing process, test vectors are needed to test the chip. With the continuous improvement of chip integration and complexity, a technology for generating compressed test vectors, namely test compression technology, has been derived.

However, the use of test compression technology in the test vector generation process will bring many additional software solution power consumption and automatic test pattern generation (ATPG) tool performance issues. In the test vector generation process, vector compaction technology is usually basically used, that is, the ATPG tool first generates fault detection stimuli and then uses the compressed increment solution solution. For a linear compressor-decompressor, as the vector compaction proceeds, according to the linear correlation, the implicit values in the compressor increase, which will lead to a decrease in the success rate of vector compaction and a large number of test vectors; at the same time, the unsuccessful fault detection stimuli need to be regenerated in the subsequent vector compaction process, which also introduces a lot of software power consumption. The commonly used Gaussian elimination technology calculates the compressed implicit values on the irrelevant bits and updates them to the background of vector compaction to improve the success rate of vector compaction. However, the Gaussian elimination technology consumes a lot of power, resulting in a low efficiency in the process of generating compressed test vectors.

Summary of the invention

The embodiments of the present application provide a method and device for generating compressed test vectors, which can greatly reduce the power consumption of test vector generation and improve the efficiency of generating compressed test vectors while increasing the success rate of test vector merging.

In a first aspect, a method for generating a compressed test vector is provided, comprising: obtaining a first linear correlation matrix and a first maximally irrelevant group according to a decompression matrix corresponding to a chip under test, wherein the decompression matrix is a matrix corresponding to a decompression circuit structure of the chip under test; filling a first target bit in a first background vector with an implicit value according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector, wherein the first target bit includes all or part of the irrelevant bits in the first background vector; and generating a compressed test vector according to the second background vector.

The above method generates a compressed test vector after filling the first background vector with an implicit value, that is, updates the first background vector, thereby avoiding the problem of subsequent merging and compression conflicts caused by the fact that the value that should be determined by the compression operation in the first background vector is not determined. While increasing the success rate of test vector merging, it can greatly reduce the power consumption of test vector generation and improve the efficiency of generating compressed test vectors.

In combination with the first aspect, in certain implementations of the first aspect, filling the first target bit in the first background vector with an implicit value according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector includes: determining first target bit information indicating the first target bit according to the first linear correlation matrix and the first maximally irrelevant group, the first target bit information being the second linear correlation matrix; and filling the first target bit with an implicit value according to the first target bit information to obtain a second background vector.

By using a linear correlation matrix to determine which irrelevant bits need to be filled with implicit values, and the linear correlation matrix can be updated according to the original linear correlation matrix of the decompressed matrix, the filling of implicit values can be flexibly implemented dynamically, thereby improving the efficiency of generating compressed test vectors.

In combination with the first aspect, in certain implementations of the first aspect, the first target bit information indicating the first target bit is determined based on the first linear correlation matrix and the first maximally irrelevant group, and the first target bit information is a second linear correlation matrix, including: according to the decompression matrix, obtaining the second maximally irrelevant group of the coefficient matrix of the first linear equation group corresponding to the first background vector, the first linear equation group including the decompression equation corresponding to the first background vector; according to the first maximally irrelevant group, adding the orthogonal complement of the second maximally irrelevant group to the second maximally irrelevant group to obtain a third maximally irrelevant group; determining the second linear correlation matrix based on the third maximally irrelevant group, the first maximally irrelevant group and the first linear correlation matrix.

By using a linear correlation matrix to determine which irrelevant bits need to be filled with implicit values, and the linear correlation matrix can be updated according to the original linear correlation matrix of the decompressed matrix and the background vector that needs to be filled, the filling of implicit values can be flexibly implemented dynamically, thereby improving the efficiency of generating compressed test vectors.

In combination with the first aspect, in certain implementations of the first aspect, filling the first target bit with an implicit value based on the first target bit information includes: determining the position of the first target bit based on whether the elements in the second linear correlation matrix are 1, the irrelevant bits in the first target bit corresponding one-to-one to the elements in the second linear correlation matrix; and filling the implicit value into the determined position of the first target bit based on the decompression matrix and the first background vector.

In combination with the first aspect, in certain implementations of the first aspect, filling an implicit value into the first target bit in the first background vector according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector includes: determining first target bit information indicating the first target bit according to the first maximally irrelevant group, the first target bit information being a target column vector interval in the first background vector; and filling an implicit value in the first target bit according to the first target bit information to obtain a second background vector.

By determining the target column vector interval and filling some column vectors in the background vector, the background vector is updated, and subsequent partial conflict problems are avoided. While taking into account the software power consumption, the efficiency of generating compressed test vectors is improved.

In combination with the first aspect, in certain implementations of the first aspect, the first background vector includes at least one column vector, the first maximally irrelevant group corresponds one-to-one to the column vector, and determining the first target bit information indicating the first target bit based on the first maximally irrelevant group includes: determining the target column vector interval based on the ranks of multiple of the first maximally irrelevant groups, the target column vector interval including at least one continuous column vector.

In combination with the first aspect, in certain implementations of the first aspect, determining the target column vector interval based on the ranks of multiple first maximal independent groups includes: obtaining at least one second linear equation group based on the decompression matrix and the first background vector, the second linear equation group including the decompression equations of the first background vector, and the second linear equation group corresponding one-to-one to continuous column vector intervals in the first background vector; determining at least one first column vector interval based on the at least one second linear equation group, the number of linear independent equations of the second linear equation group corresponding to the first column vector interval being greater than a first threshold; determining a second column vector interval based on the at least one first column vector interval, the second column vector interval being the column vector interval with the largest number of column vectors included in the at least one first column vector interval; determining the target column vector interval based on the second column vector interval, the target column vector interval including the second column vector interval.

By selecting a column vector space with a large number of corresponding linearly independent equations, as many implicit values as possible can be filled, avoiding large-scale conflict problems and improving the efficiency of generating compressed test vectors.

In combination with the first aspect, in certain implementations of the first aspect, determining the target column vector interval based on the second column vector interval includes: determining that the rank of at least one of the first maximally irrelevant groups corresponding to the second column vector interval is a first value; judging whether the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is equal to the first value; updating the second column vector interval to a third column vector interval based on the judgment result; determining that the rank of at least one of the first maximally irrelevant groups corresponding to a fourth column vector interval is equal to the number of linearly independent equations of the second linear equation group corresponding to the fourth column vector interval, and the fourth column vector interval is an adjacent column vector interval of the third column vector interval; and determining the target column vector interval to be the union of the third column vector interval and the fourth column vector interval.

In combination with the first aspect, in certain implementations of the first aspect, updating the second column vector interval to a third column vector interval based on the judgment result includes: when the judgment result is that the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is not equal to the first numerical value, determining the values of some constant terms in the linearly independent equations so that the second column vector interval is updated to the third column vector interval, and the number of linearly independent equations of the second linear equation group corresponding to the third column vector interval is equal to the first numerical value.

In combination with the first aspect, in certain implementations of the first aspect, filling the first target bit with an implicit value based on the first target bit information includes: calculating the implicit value of the irrelevant bits in the target column vector interval based on the target column vector interval and the decompression matrix; and filling the implicit value into the first target bit.

In combination with the first aspect, in certain implementations of the first aspect, the product of the first linear correlation matrix and the first maximally independent group corresponds to a matrix block row of the decompressed matrix; or, the product of the first linear correlation matrix and the first maximally independent group corresponds to the decompressed matrix.

In a second aspect, a device for generating a compressed test vector is provided, the device comprising a processing module, the processing module being used to: obtain a first linear correlation matrix and a first maximally irrelevant group according to a decompression matrix corresponding to a chip under test, wherein the decompression matrix is a matrix corresponding to a decompression circuit structure of the chip under test; fill a first target bit in a first background vector with an implicit value according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector, the first target bit including all or part of the irrelevant bits in the first background vector; and generate a compressed test vector according to the second background vector.

In combination with the second aspect, in certain implementations of the second aspect, the processing module is specifically used to: determine first target bit information indicating a first target bit based on the first linear correlation matrix and the first maximally irrelevant group, the first target bit information being a second linear correlation matrix; and fill an implicit value in the first target bit based on the first target bit information to obtain a second background vector.

In combination with the second aspect, in certain implementations of the second aspect, the processing unit is further specifically used to: obtain a second maximally irrelevant group of the coefficient matrix of the first linear equation group corresponding to the first background vector according to the decompression matrix, the first linear equation group including the decompression equation corresponding to the first background vector; add the orthogonal complement of the second maximally irrelevant group to the second maximally irrelevant group according to the first maximally irrelevant group to obtain a third maximally irrelevant group; determine the second linear correlation matrix according to the third maximally irrelevant group, the first maximally irrelevant group and the first linear correlation matrix.

In combination with the second aspect, in certain implementations of the second aspect, the processing unit is further specifically used to: determine the position of the first target bit according to whether the elements in the second linear correlation matrix are 1, and the irrelevant bits in the first target bit correspond one-to-one to the elements in the second linear correlation matrix; fill the determined position of the first target bit with an implicit value according to the decompression matrix and the first background vector.

In combination with the second aspect, in certain implementations of the second aspect, the processing unit is specifically used to: determine first target bit information indicating a first target bit based on the first maximally irrelevant group, the first target bit information being a target column vector interval in the first background vector; and fill an implicit value in the first target bit based on the first target bit information to obtain a second background vector.

In combination with the second aspect, in certain implementations of the second aspect, the first background vector includes at least one column vector, the first maximally irrelevant group corresponds one-to-one to the column vector, and the processing unit is further specifically used to: determine the target column vector interval based on the ranks of multiple first maximally irrelevant groups, and the target column vector interval includes at least one continuous column vector.

In combination with the second aspect, in certain implementations of the second aspect, the processing unit is further specifically used to: obtain at least one second linear equation group based on the decompression matrix and the first background vector, the second linear equation group including the decompression equation of the first background vector, and the second linear equation group corresponding one-to-one to the continuous column vector interval in the first background vector; determine at least one first column vector interval based on the at least one second linear equation group, the number of linearly independent equations of the second linear equation group corresponding to the first column vector interval is greater than a first threshold; determine a second column vector interval based on the at least one first column vector interval, the second column vector interval being the column vector interval with the largest number of column vectors included in the at least one first column vector interval; determine the target column vector interval based on the second column vector interval, the target column vector interval including the second column vector interval.

In combination with the second aspect, in certain implementations of the second aspect, the processing unit is further specifically used to: determine that the rank of at least one of the first maximally irrelevant groups corresponding to the second column vector interval is a first value; determine whether the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is equal to the first value; based on the judgment result, update the second column vector interval to the third column vector interval; determine that the rank of at least one of the first maximally irrelevant groups corresponding to the fourth column vector interval is equal to the number of linearly independent equations of the second linear equation group corresponding to the fourth column vector interval, and the fourth column vector interval is an adjacent column vector interval of the third column vector interval; determine that the target column vector interval is the union of the third column vector interval and the fourth column vector interval.

In combination with the second aspect, in certain implementations of the second aspect, the processing unit is also used to: when the judgment result is that the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is not equal to the first numerical value, determine the values of some constant terms in the linearly independent equations so that the second column vector interval is updated to the third column vector interval, and the number of linearly independent equations of the second linear equation group corresponding to the third column vector interval is equal to the first numerical value.

In combination with the second aspect, in certain implementations of the second aspect, the processing unit is also used to: calculate the implicit value of the irrelevant bits in the target column vector interval based on the target column vector interval and the decompression matrix; and fill the implicit value into the first target bit.

In combination with the second aspect, in certain implementations of the second aspect, the product of the first linear correlation matrix and the first maximally independent group corresponds to a matrix block row of the decompressed matrix; or, the product of the first linear correlation matrix and the first maximally independent group corresponds to the decompressed matrix.

In a third aspect, a computer program product is provided, which includes instructions. When the instructions are executed on a computer, the computer executes the method described in the first aspect or any implementation of the first aspect.

In a fourth aspect, a device for generating a compressed test vector is provided, comprising a processor and a memory, wherein the memory is used to store a program, and the processor is used to call and run the program from the memory to execute the method in the above-mentioned first aspect or any possible implementation manner of the first aspect.

In a fifth aspect, a computer-readable storage medium is provided, comprising a computer program, which, when executed on a computer, enables the computer to execute the method for testing control software in the first aspect or any possible implementation of the first aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram of a chip design and manufacturing process applicable to an embodiment of the present application.

FIG. 2 is a schematic block diagram of a process for generating a compressed test vector applicable to an embodiment of the present application.

FIG3 is a schematic diagram of a method for generating a compressed test vector provided in an embodiment of the present application.

FIG. 4 is a schematic diagram of another exemplary method for generating a compressed test vector provided in an embodiment of the present application.

FIG. 5 is a schematic diagram of another exemplary method for generating a compressed test vector provided in an embodiment of the present application.

FIG. 6 is a schematic block diagram of an apparatus for generating a compressed test vector according to an embodiment of the present application.

FIG. 7 is a schematic diagram of the hardware structure of an apparatus for compressing test vectors according to an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings.

Chips, which can also be called integrated circuits (ICs), or can be understood as the carrier of integrated circuits, are usually a way to miniaturize circuits and are often manufactured on the surface of semiconductor wafers. As shown in FIG1 , the process 100 of chip design and manufacturing can usually be divided into three parts: design part 101, manufacturing part 102, and packaging and testing part 103. Among them, in the process of chip design, manufacturing and packaging, it is inevitable that the chip will have defects due to various reasons (such as process, materials, etc.), and such defects will cause the chip to fail to work properly. At this time, chip testing is required.

The main task of chip testing is to pick out defective chips. Usually, design for testability (DFT) structures can be added to the chip, such as scan chains, etc. It can be understood as implanting some special structures into the circuit during the design stage so that testing can be performed after the design is completed. By adding scan chains, the internal timing units of the chip can be more conveniently controlled by the outside.

The specific chip testing process mainly includes: first, generate test patterns through automatic test pattern generation (ATPG) tools; then input the test patterns into the chip under test through automatic test equipment (ATE); finally, compare the test response of the chip under test with the expected response to see if it is consistent, to know whether the chip has defects.

However, as the integration and complexity of chips continue to increase, the data size of the required test vectors also grows rapidly, resulting in a rapid increase in chip testing time and cost. In order to reduce chip testing costs and reduce chip testing time, the test vectors can be compressed, that is, test compression technology. As shown in Figure 1, test compression technology is used in the packaging test part of the chip.

In the test compression technology, the generation process of the compressed test vector can be: (1) The ATPG tool models the possible faults of the chip (such as the faults in the fault list) and generates a fault detection stimulus. The fault detection stimulus includes one or more bits, which include fixed bits and don't care bits. The value filled with the fixed bit is a valid value (specified bit), and the value filled with the don't care bit is a don't care value (don't care bit). The valid value can be understood as a fixed value in the fault detection stimulus, which is used to detect the corresponding fault. The don't care value can be understood as a value that can be arbitrarily set in the fault detection stimulus, for example, it can be any value between 0 and 1. For example, as shown in FIG2, first, in step S201, n fault detection stimuli ( _a1 , _a2 , ..., _an ) are generated, wherein each box represents a bit, and a box filled with a pattern indicates that the bit is a fixed bit, and a box without a pattern fill indicates that the bit is a don't care bit. For ease of understanding, each fault detection stimulus shown in FIG2 includes only 10 bits. In the actual generated fault detection stimulus, the bits included can be in the millions, and the data scale is relatively large. It should be understood that one fault detection stimulus corresponds to one fault;

(2) Performing a static compaction process: After generating a certain number of fault detection stimuli, all or part of the fault detection stimuli in the certain number of fault detection stimuli are merged and compressed to obtain a compressed background vector. For example, as shown in FIG2 , in step S202 , n fault detection stimuli (a ₁ , a ₂ , ..., a _n ) are merged and compressed one by one, that is, two fault detection stimuli in the n fault detection stimuli are merged to obtain a background vector (background merged cube), and then compressed to obtain a compressed background vector, ensuring that the merged fault detection stimuli can be compressed successfully, and then adding another fault detection stimuli to the background vector obtained by merging the two fault detection stimuli, that is, merging and compressing the three fault detection stimuli, and so on. After multiple merging and compression, the n fault detection stimuli can finally be merged to obtain a background vector A, and then the background vector is compressed to obtain a compressed background vector A'. It should be understood that the number of elements included in the background vector A is the same as the number of elements included in a fault detection stimuli, and the number of elements included in the compressed background vector A' is less than the number of elements included in the background vector A. It should also be understood that merging is to merge multiple fault detection stimuli into one, that is, merging is to reduce the number of fault detection stimuli, and compression is to shorten the length of the fault detection stimuli, that is, compression is to reduce the number of elements in the fault detection stimuli, and the merging process is accompanied by compression, or it can be called incremental compression during the merging process, that is, each time a fault detection stimulus is merged, it is necessary to check whether incremental compression can be successfully performed to ensure that the merged state can be compressed successfully;

(3) Performing a dynamic compaction process: Based on the compressed background vector, a fault detection stimulus is generated, and then the generated fault detection stimulus increments are merged and compressed into the compressed background vector to generate a compressed test pattern. For example, as shown in FIG2 , based on the background vector A, a fault detection stimulus _b1 is generated, and then A and _b1 are merged and compressed. After the compression is successful, a fault detection stimulus _b2 is generated based on the background vector generated by merging A and _b1 . Then the background vector generated by merging A and _b1 and _b2 are merged and compressed. After the compression is successful, a fault detection stimulus _b3 is generated based on the background vector generated by merging _b2 . This process is repeated until a fault detection stimulus bm is generated. Finally, a background vector B is obtained by merging A and m fault detection stimuli ( _b1 , _b2 , ..., _bm ). After the background vector B is compressed, a compressed test vector B' is obtained. Subsequently, the compressed test vector may be stored in ATE. After ATE injects the compressed test vector into the chip under test, the compressed test vector is decompressed by a decompression circuit on the chip under test and then input into the circuit under test in the chip under test. For example, the compressed test vector B' may be injected into the chip under test and then input into the circuit under test through a decompression circuit to be restored to a merged vector of the n fault detection stimuli ( _a1 , _a2 , ..., _an ) and the m fault detection stimuli ( _b1 , _b2 , ..., _bm ), that is, a merged background vector B.

It should be understood that the compressed test vector may also be referred to as a compressed seed. It should also be understood that the generation process of the compressed test vector may be performed by an ATPG tool. It should also be understood that in the generation process of the compressed test vector, the vector obtained by merging the fault detection stimulus may be referred to as a background vector, and after further compression, the vector obtained may be referred to as a compressed background vector, and the vector finally obtained may be referred to as a compressed test vector, that is, after merging the compressed background vector and compressing the last fault detection stimulus, the vector obtained may be referred to as a compressed test vector.

It is worth noting that in the static compaction process and dynamic compaction process of the above steps (2) and (3), when the generated fault detection stimuli are merged and compressed to generate a compressed background vector or a compressed test vector, due to the compression operation, the fault detection stimuli used for merging and compression need to meet the compression conditions, otherwise the generated fault detection stimuli cannot be merged and compressed into the background vector.

In other words, in the dynamic compaction process of step (3) above, the fixed bits in the fault detection stimulus generated by the ATPG tool correspond to the don't care bits before the background vector is compressed, that is, they correspond to the don't care bits of the background vector obtained by merging the fault detection stimulus. The fill value of the don't care bits before the background vector is compressed may be determined due to the compression operation. At this time, the fill value of the don't care bits before the background vector is compressed can be called an implied value. When the fill value of the don't care bits is different from the fill value of the fixed bits in the fault detection stimulus, the generated fault detection stimulus cannot be merged and compressed into the background vector, that is, a conflict occurs at this time.

Or in other words, in the dynamic compaction process of step (3) above, the fault detection stimulus generated by the ATPG tool may not satisfy the compression operation and therefore cannot be incrementally merged into the background vector, thereby causing a conflict and increasing the power consumption of dynamic compaction.

Specifically, the background vector B restored in the above-mentioned circuit under test corresponds to a scan chain in the circuit under test. A scan chain includes at least one scan cell. The value of each scan cell is a value in the background vector B, that is, an element in the vector. The vector input to the circuit under test is the compressed test vector B'. If each compressed value in the compressed test vector B' is regarded as a free variable, each value in the background vector B can be linearly represented by part of the compressed value or all of the compressed value in the compressed test vector B' due to the compression operation, that is, the value of each scan cell can be linearly represented by the input free variable, and the number of scan cells is much larger than the number of free variables. Therefore, there are a lot of linear correlations between the multiple equations corresponding to the multiple scan cells, that is, the values on many scan cells can be linearly represented by the values on other scan cells.

In the background vector generated by the dynamic compaction process, only a small number of values are valid values, and most of the remaining values are irrelevant values. However, as the number of valid values in the background vector increases, more and more irrelevant values are determined. When generating fault detection stimuli based on the current background vector, if the ATPG tool does not know which irrelevant values have been determined, the fault detection stimuli cannot be compressed into the background vector, that is, the compression increment solution is unsuccessful, and conflicts occur at this time, which increases the power consumption of dynamic compaction. In high compression ratio scenarios, as the fault detection stimuli are merged and compressed, more and more irrelevant values are determined, that is, the number of implicit values also increases. At this time, conflicts between the valid values in the fault detection stimuli generated by the ATPG tool and the implicit values generated by compression will occur in large numbers.

Usually, in order to reduce the generation of conflicts in the above-mentioned dynamic compaction process, after the above-mentioned step (2) and before step (3), Gaussian elimination calculation is performed on the equation corresponding to the irrelevant bit filling value of the entire background vector, that is, the linear equation of the input free variable corresponding to the irrelevant value filled by the scanning unit, to check which irrelevant values in the current background vector are implicit values and calculate the value. However, this method has a large calculation scale and is only performed once between the static compaction process and the dynamic compaction process. The conflicts generated in the dynamic compaction process cannot be eliminated. Therefore, the efficiency of generating compressed test vectors in this way is low. In view of this, an embodiment of the present application proposes a method for generating test vectors, which can greatly reduce the power consumption of test vector generation while increasing the success rate of test vector merging.

First, to facilitate understanding of the present application, some terms involved in the embodiments of the present application are explained.

Matrix: A set of complex or real numbers arranged in a rectangular array. For example, a table of m×n numbers with m rows and n columns is called a matrix of m rows and n columns, or m×n matrix for short. A matrix with n rows and columns is called an n-order matrix, or an n-order square matrix. In the embodiments of the present application, when the test vectors involved are represented by matrices, the matrix elements mainly include 0 and 1.

Vector group: A set of column vectors or row vectors of the same dimension. A matrix can be understood as consisting of vector groups.

Maximal independent group: generally refers to the maximal linearly independent group, which is the linearly independent vector group with the largest number of vectors in the linear space. For example, its definition can be: suppose there is a vector group A: α1, α2, α3, …, αs, if r vectors α1, α2, …, αr can be selected from A, satisfying the vector group A0: α1, α2, …, αr are linearly independent, and any vector in the vector group A can be linearly represented by several vectors in the vector group A0, then the vector group A0 is called a maximal linearly independent group of the vector group A, abbreviated as the maximal independent group.

Rank: The rank of a matrix is the highest order of its non-zero minors, and the rank of a vector group is the number of vectors contained in its maximal independent group. For a matrix, when the highest order of its non-zero minors is equal to the order of the matrix, the matrix is said to be full rank. For a vector group, when the number of vectors contained in the maximal independent group is equal to the number of vector groups, the vector group is said to be full rank.

FIG3 shows a schematic diagram of a method for generating a compressed test vector provided in an embodiment of the present application. Specifically, the method 300 includes:

S301, obtaining a first linear correlation matrix and a first maximally independent group according to a decompression matrix corresponding to the chip under test, wherein the decompression matrix is a matrix corresponding to the decompression circuit structure of the chip under test.

In the embodiment of the present application, the chip under test is a chip for testing with compressed test vectors, and the chip under test includes a decompression circuit, which can decompress the compressed test vectors. The above step S301 can be performed by an ATPG tool, which can obtain the decompression circuit structure of the chip under test, and then model according to the decompression circuit structure to extract the decompression matrix.

It is worth noting that the decompression circuit structure is the decompression circuit structure of the test circuit of the chip to be tested. Therefore, when the ATPG tool generates fault detection stimuli, and merges and compresses the fault detection stimuli, the fault detection stimuli are merged and compressed according to the relevant characteristics of the decompression circuit structure, so that the decompression circuit can subsequently completely decompress the merged and compressed fault detection stimuli, thereby improving the test efficiency of the chip.

In an embodiment of the present application, the decompression circuit structure is a linear-based decompression circuit structure. For example, the decompression circuit structure includes a ring generator and a phase shifter, so that a decompression matrix can be constructed according to the mapping relationship between the ring generator and the phase shifter.

Optionally, the ring generator includes a plurality of shift registers, and the mapping relationship corresponding to the ring generator can be expressed by the following formula (1):

r _t = R _fr _t-1 + R _v x _t (1)

Among them, r _t represents the value of the shift register at time t, R _f represents the linear matrix corresponding to the feedback connection structure of the shift register itself, r _t-1 represents the value of the shift register in the ring generator at time t-1, R _v represents the linear matrix corresponding to the connection structure between the input pin and the shift register, x _t represents the compressed value injected by the tth tap,

Optionally, the linear matrix corresponding to the phase shifter is P, and the shift value of the shift register included in the ring generator at time t can be expressed by the following formula (2):

b _ts = Pr _ts , t>s (2)

Among them, b _ts represents the shift value of the shift register, or b _ts represents the background vector obtained after the combined fault detection stimulus, r _ts represents the value of the shift register at time ts, s represents the number of initialization taps when the compressed test vector (i.e., compressed solution) is input into the decompression circuit beat by beat, or s represents the number of initialization taps before the effective tap when the compressed test vector is input into the decompression circuit.

In a possible implementation, according to the above formulas (1), (2) and r ₀ = 0, the following formula decompression mapping formula (3) can be obtained. The first matrix on the right side of the formula (3) is the decompression matrix. According to the formula (3), the corresponding relationship between the matrix b and the matrix x can be obtained, that is, the corresponding relationship between the value in the background vector and the compressed value of the background vector can be obtained.

That is, the decompression matrix E can be defined as the following formula (4):

In an embodiment of the present application, the decompressed matrix can be decomposed into a first linear correlation matrix and a first maximally independent group. For example, according to the properties of the decompressed matrix, the first linear correlation matrix and the first maximally independent group can be hierarchically constructed. The first linear correlation matrix can also be called a first linear correlation table.

In a possible implementation, the product of the first linear correlation matrix and the first maximally irrelevant group corresponds to the matrix block row of the decompressed matrix. It should be understood that the product of the two corresponding to the matrix block row of the decompressed matrix may mean that the product is the same as the matrix block row, or that the deviation of the product from the matrix block row is within a preset range, or that the product is the same as the matrix block row after being multiplied by a certain coefficient, and the present application does not limit this. Optionally, the first linear correlation matrix and the first maximally irrelevant group, such as _Di and _Ci , can be calculated based on the matrix block row of the decompressed matrix, such as _Ei , and the first linear correlation matrix multiplied by the first maximally irrelevant group is equal to the matrix block row of the decompressed matrix, that is, there is an equation _Ei = _Di · _Ci . It is worth noting that a matrix block row of a decompressed matrix corresponds to a column vector of a background vector, such as _bi , and a column vector can also be called a test cycle. That is, the maximally irrelevant group and the linear correlation matrix within a test cycle can be obtained.

In another possible implementation, the product of the first linear correlation matrix and the first maximally irrelevant group corresponds to the decompression matrix. It should be understood that the product of the two corresponding to the decompression matrix may mean that the product is the same as the decompression matrix, or that the deviation between the product and the decompression matrix is within a preset range, or that the product is the same as the decompression matrix after being multiplied by a certain coefficient, and the present application does not limit this. Optionally, the first linear correlation matrix and the first maximally irrelevant group, such as D and M, may also be calculated based on the decompression matrix, such as E, and the first linear correlation matrix multiplied by the first maximally irrelevant group is equal to the decompression matrix, that is, there is an equation E=D·M. Specifically, for each maximally irrelevant group in a test cycle set, the maximally irrelevant group of the test cycle set, that is, the first maximally irrelevant group, may be calculated, for example, the maximally irrelevant group M is calculated for { _i } _1≤i≤m , and the linear correlation matrix of the test cycle set, that is, the first linear correlation matrix, such as D, is calculated.

S302, filling an implicit value into a first target bit in a first background vector according to a first linear correlation matrix and/or a first maximal irrelevant group to obtain a second background vector, wherein the first target bit includes all or part of the irrelevant bits in the first background vector.

In the embodiment of the present application, the first background vector may be any background vector in Fig. 2. In other words, the first background vector may be any background vector in a static compaction process and a dynamic compaction process.

In an embodiment of the present application, the first background vector may be a background vector obtained after the ATPG tool merges at least one fault detection stimulus. The first background vector includes fixed bits and irrelevant bits, and the irrelevant bits include irrelevant bits determined by the compression operation, that is, when the first background vector is compressed, some or all of the irrelevant bits in the first background vector will be determined. In order to avoid the occurrence of subsequent conflicts, it is necessary to determine the positions and determined values of some or all of the irrelevant bits that have been determined, that is, implicit values, and then fill the implicit values into the first target bit.

In an embodiment of the present application, there may be multiple ways to fill the first target bit in the first background vector with an implicit value according to the first linear correlation matrix and/or the first maximally independent group to obtain the second background vector, for example, it may be any one of the following ways 1 and 2. It should be understood that way 1 can be called a dynamic filling algorithm, and way 2 can be called a static filling algorithm. It is worth noting that in generating a compressed test vector, multiple background vectors will be generated. For the filling method of implicit values in multiple background vectors, way 1 and way 2 can be used alone. When used alone, the embodiment of the present application does not limit the number of times way 1 or way 2 is used; way 1 and way 2 can also be used in combination. When used in combination, the embodiment of the present application does not limit the order of their use and the number of times they are used.

Method 1, including steps S304-S305:

S304: Determine first target bit information indicating the first target bit according to the first linear correlation matrix and the first maximally independent group, where the first target bit information is the second linear correlation matrix.

In an embodiment of the present application, the first target bit information can be used to indicate the first target bit, or in other words, the first target bit information can be used to indicate the position of the first target bit, that is, the first target bit information can be used to indicate which irrelevant bits need to be filled with implicit values. In addition, the first target bit information is a matrix, namely, a second linear correlation matrix. The second linear correlation matrix can also be called a second linear correlation table.

In one possible implementation, the method for determining the first target bit information may be, that is, the method for determining the second linear correlation matrix may be, based on the decompression matrix, obtaining the second maximally irrelevant group of the coefficient matrix of the first linear equation group corresponding to the first background vector, the first linear equation group including the decompression equation corresponding to the first background vector; based on the first maximally irrelevant group, adding the orthogonal complement of the second maximally irrelevant group to the second maximally irrelevant group to obtain a third maximally irrelevant group; and determining the second linear correlation matrix based on the third maximally irrelevant group, the first maximally irrelevant group and the first linear correlation matrix.

In an embodiment of the present application, the above-mentioned method for determining the second linear correlation matrix can be specifically: 1) according to the decompression matrix, obtain the first maximally independent group of the coefficient matrix of the first linear equation corresponding to the first background vector, for example, the first maximally independent group is _B1 ; 2) according to the decompression matrix, obtain the decompression matrix linear correlation table and the maximally independent group, for example, when the decompression matrix is E, there is an equation E=D·M, where the matrix D is the decompression matrix linear correlation table, and M is the maximally independent group of E; 3) according to the maximally independent group of the decompression matrix, add orthogonal complement to the first maximally independent group to obtain the second maximally independent group, for example, select a linear independent equation _B2 orthogonal to the first maximally independent group from M, and add _B2 to _B1 to obtain the second maximally independent group

Thus, M=T·B; 4) According to the second maximally irrelevant group and the decompression matrix, the decompression matrix linear correlation table is updated, that is, the second linear correlation matrix is determined. For example, according to the equation E=D·M and the equation M=T·B, E=D·T·B can be obtained. If Q=D·T is set, then E=Q·B, that is, Q is the decompression matrix linear correlation table obtained after the update, that is, Q is the second linear correlation matrix. Optionally, the second linear correlation matrix can be called the updated first linear correlation matrix, which is not limited in this application.

S305 , filling an implicit value in the first target bit according to the first target bit information to obtain a second background vector.

In the embodiment of the present application, the second background vector is a vector obtained by updating the first background vector, that is, a background vector obtained by filling the irrelevant bits of the first background vector with implicit values. Thus, a fault detection stimulus can be generated according to the updated first background vector, and the generated fault detection stimulus can avoid conflicts when merging and compressing.

In an embodiment of the present application, the first target bit information is the second linear correlation matrix. The position of the first target bit can be determined based on whether the elements in the second linear correlation matrix are 1, and then the implicit value is filled into the determined position of the first target bit based on the decompression matrix and the first background vector, wherein the irrelevant bits in the first target bit correspond one-to-one to the elements in the second linear correlation matrix.

In a possible implementation, when the second linear correlation matrix is an updated decompressed matrix linear correlation table, each row vector in the updated decompressed matrix linear correlation table corresponds to a bit in the first background vector, and each row vector includes one or more elements, and the value of the element can be 0 or 1. When the element is 1, it means that the corresponding bit can be linearly represented by the linear independent equation group in the second maximal independent group. Therefore, the position of the first target bit can be determined according to the value of the element in the updated decompressed matrix linear correlation table. After determining the position of the first target bit, the value determined on the independent bit, that is, the implicit value, is determined by calculation.

For the specific implementation of the above steps S304-S305, please refer to the relevant description of Figure 4 below.

Method 2 includes steps S306-S307:

S306: Determine first target bit information indicating a first target bit according to the first maximally irrelevant group, where the first target bit information is a target column vector interval in the first background vector.

In the embodiment of the present application, the first background vector includes at least one column vector. For example, _bi in the above formula (3) represents a column vector. A column vector can be called a test cycle.

In the embodiment of the present application, the first maximally irrelevant group may be a maximally irrelevant group within a test cycle, such as C _i in the above step S301. At this time, the first maximally irrelevant group corresponds to a test cycle, that is, the first maximally irrelevant group corresponds to the column vector of the first background vector one-to-one, and the target column vector interval may be determined according to the ranks of the plurality of first maximally irrelevant groups, and the target column vector interval includes at least one column vector.

In one possible implementation, the target column vector interval is determined according to the ranks of multiple first maximal independent groups as follows: at least one second linear equation group is obtained according to the decompression matrix and the first background vector, the second linear equation group includes the decompression equation of the first background vector, and the second linear equation group corresponds one-to-one to the continuous column vector intervals in the first background vector; at least one first column vector interval is determined according to at least one second linear equation group, and the number of linear independent equations of the second linear equation group corresponding to the first column vector interval is greater than a first threshold; a second column vector interval is determined according to at least one first column vector interval, and the second column vector interval is the column vector interval with the largest number of column vectors included in at least one first column vector interval; a target column vector interval is determined according to the second column vector interval, and the target column vector interval includes the second column vector interval.

Optionally, the first threshold may be determined in the following manner: in the process of generating each test vector, the first threshold may adopt different artificial experience values, or may be dynamically adjusted through learning;

In an embodiment of the present application, a method for determining a target column vector interval based on the second column vector interval may be: determining that the rank of at least one first maximally irrelevant group corresponding to the second column vector interval is a first numerical value; determining whether the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is equal to the first numerical value; based on the judgment result, updating the second column vector interval to a third column vector interval; determining that the rank of at least one first maximally irrelevant group corresponding to the fourth column vector interval is equal to the number of linearly independent equations of the second linear equation group corresponding to the fourth column vector interval, and the fourth column vector interval is an adjacent column vector interval of the third column vector interval; determining the target column vector interval to be the union of the third column vector interval and the fourth column vector interval.

In an embodiment of the present application, according to the judgment result, the method of updating the second column vector interval to the third column vector interval can be: when the number of linearly independent equations corresponding to the second column vector interval is not equal to the first value, determine the value of some constant terms in the linearly independent equations, so that the second column vector interval is updated to the third column vector interval, and the number of linearly independent equations of the second linearly independent equation group corresponding to the third column vector interval is equal to the first value. It should be understood that the second column vector interval includes the same number of column vectors as the third column vector interval, and the difference is that the values on some irrelevant bits in the third column vector interval are determined, that is, the value of the constant term is determined.

Optionally, the above method of determining the value of the constant term may be to randomly assign the value according to the probability of occurrence of the value of the constant term.

In an embodiment of the present application, a specific method for determining a target column vector interval may be: 1) obtaining, according to the decompression matrix, a linear equation of the irrelevant value in each column vector in the first background vector with respect to the compressed value, that is, a linear equation of the element in each test cycle with respect to the compressed value; 2) then calculating the linearly independent equations in each test cycle; 3) then obtaining a test cycle region in which the number of linearly independent equations in the test cycle region is greater than a first threshold, or in other words, obtaining a column vector interval greater than or equal to the first threshold; 4) selecting a first test cycle region from the obtained test cycle region, the first test cycle region being the region with the largest length in the obtained test cycle region, that is, the first column vector interval including the most column vectors, for example (b _i , b _j ); 5) randomly filling values into irrelevant bits in the first test cycle region so that the first test cycle region is full rank, that is, the number of linearly independent equations in the first column vector interval is equal to the rank of the multiple first maximally irrelevant groups corresponding to the column vector interval; 6) expanding the first test cycle region to obtain a second test cycle region of full rank, that is, the number of linearly independent equations in the second column vector interval is equal to the rank of the multiple first maximally irrelevant groups corresponding to the column vector interval.

It is worth noting that the above-mentioned "full rank" means that the number of linearly independent equations in the decompression equation group of a certain column vector interval in the background vector is equal to the rank of the maximal independent group of the decompression matrix corresponding to the column vector interval, or in other words, the number of vectors included in the maximal independent group of the decompression matrix corresponding to the column vector interval is equal.

S307 , filling an implicit value in the first target bit according to the first target bit information to obtain a second background vector.

In the embodiment of the present application, the implicit value of the irrelevant bit in the target column vector interval can be calculated according to the target column vector interval and the decompression matrix; the implicit value is filled into the first target bit to obtain the second background vector. In other words, the second background vector can be obtained by determining part of the value in the first background vector, that is, updating the first background vector, so that after the first background vector is updated, the subsequent conflict problem caused by the partially determined irrelevant bit can be avoided, and the efficiency of generating the compressed test vector can be improved.

For the specific implementation of the above steps S306-S307, please refer to the relevant description of Figure 5 below.

S303: Generate a compressed test vector according to the second background vector.

In an embodiment of the present application, the second background vector can be directly compressed to generate a compressed test vector, or a fault detection stimulus can be generated based on the second background vector. After a series of merging and compression, a compressed test vector is generated. Alternatively, a compressed test vector can be generated after repeating one or more operations similar to the above steps S301-S302. The present application does not limit this.

Therefore, the above method fills the first background vector with implicit values, generates the second background vector, and then generates the compressed test vector, that is, updates the first background vector, thereby avoiding the problem of subsequent merging and compression conflicts caused by the fact that the value that should be determined by the compression operation in the first background vector is not determined, thereby improving the efficiency of generating compressed test vectors.

FIG4 is a schematic diagram of an exemplary method for generating a compressed test vector provided by an embodiment of the present application. Specifically, the method 400 includes:

S401, obtaining a first background vector.

In an embodiment of the present application, the first background vector may be a background vector obtained after a static compaction process, or may be a background vector obtained during a dynamic compaction process, and the present application does not impose any limitation on this.

S402, obtaining a maximally irrelevant group B ₁ corresponding to a first background vector.

In the embodiment of the present application, the maximal independent group _B1 is a maximal independent group of the coefficient matrix of the linear equation group corresponding to the first background vector, and the linear equation group includes the compression equation of the first background vector.

S403: Based on the maximally irrelevant group M of the decompressed matrix, the maximally irrelevant group _B1 corresponding to the first background vector is completed into the maximally irrelevant group B, and a mapping relationship M=T·B is established.

In the embodiment of the present application, the equation group B ₂ is selected from the maximally independent group M, and B ₂ is added to B ₁ to obtain the maximally independent group B, so that M=T·B.

S404, updating the linear correlation matrix corresponding to the decompression matrix to Q=D·T.

In the embodiment of the present application, the linear correlation matrix of the decompressed matrix is updated from D to Q.

S405, calculating and filling implicit values according to the updated linear correlation matrix Q.

For the specific implementation of the above steps S401-S405, please refer to the above steps S304-S305, which will not be repeated here.

FIG5 shows a schematic diagram of an exemplary method for generating a compressed test vector provided by an embodiment of the present application. Specifically, the method 500 includes:

S501, obtaining a first background vector.

S502, obtaining the rank of a linear equation group corresponding to multiple column vector intervals in the first background vector.

In an embodiment of the present application, the linear equation group corresponding to multiple column vector intervals includes the decompression equation of the background vector, and the rank of the linear equation group corresponding to each column vector interval in the multiple column vector intervals can be called the interval rank, that is, the above step S502 is to obtain multiple interval ranks.

S503: Determine whether the rank is greater than a first threshold.

In the embodiment of the present application, it is determined whether there is an interval rank greater than a first threshold among multiple interval ranks.

If not, stop the subsequent steps.

If yes, continue with the following steps:

S504: Fill in the rank of a column vector interval with the largest number of consecutive column vectors among multiple column vector intervals whose ranks are greater than a first threshold, to be full rank.

In the embodiment of the present application, first, it is necessary to select a column vector interval with the largest number of consecutive column vectors from multiple column vector intervals, and then determine the values of some irrelevant bits in the column vector interval so that the column vector interval is full rank. For the meaning of full rank in the present application, please refer to the relevant description in the above step S306, which will not be repeated here.

S506, check whether the adjacent column vector interval is full rank, and update the full rank interval.

In an embodiment of the present application, it is possible to check whether the adjacent interval of the full rank interval determined in the above step S504 is full rank. If so, the full rank interval is updated to be the set of the full rank interval determined in step S504 and its adjacent intervals.

S507, calculating the updated implicit value of the full rank interval.

In the embodiment of the present application, the implicit value of the updated full rank interval is calculated and filled into the first background vector to obtain the second background vector.

For the specific implementation of the above steps S501-S506, please refer to the above steps S306-S307, which will not be repeated here.

The above describes in detail the method embodiment of the embodiment of the present application, and the following describes the device embodiment of the embodiment of the present application. The device embodiment and the method embodiment correspond to each other, so the parts that are not described in detail can refer to the previous method embodiment, and the device can implement any possible implementation method of the above method.

Fig. 6 shows a schematic block diagram of an apparatus 600 for generating a compressed test vector according to an embodiment of the present application. The apparatus 600 can execute the method for generating a compressed test vector according to the embodiment of the present application.

As shown in FIG. 6 , the device includes a processing module 601 .

When the device 600 executes the above method 300, the processing module 601 is used to: obtain a first linear correlation matrix and a first maximally irrelevant group according to the decompression matrix corresponding to the chip under test, wherein the decompression matrix is a matrix corresponding to the decompression circuit structure of the chip under test; fill an implicit value into a first target bit in a first background vector according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector, wherein the first target bit includes all or part of the irrelevant bits in the first background vector; and generate a compressed test vector according to the second background vector.

For more detailed functions of the above-mentioned device 600, please refer to the relevant description in the implementation of the above-mentioned method, which will not be repeated here.

FIG7 is a schematic diagram of the hardware structure of a device for compressing test vectors according to an embodiment of the present application. The device 700 for compressing test vectors shown in FIG7 includes a memory 701, a processor 702, a communication interface 703, and a bus 704. The memory 701, the processor 702, and the communication interface 703 are connected to each other through the bus 704.

The memory 701 may be a read-only memory (ROM), a static storage device, and a random access memory (RAM). The memory 701 may store a program. When the program stored in the memory 701 is executed by the processor 702, the processor 702 and the communication interface 703 are used to execute the various steps of the method for compressing the test vector of the embodiment of the present application.

Processor 702 can adopt a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit (GPU) or one or more integrated circuits to execute relevant programs to implement the functions required to be performed by the units in the device for compressing the test vector of the embodiment of the present application, or to execute the method for compressing the test vector of the embodiment of the present application.

The processor 702 may also be an integrated circuit chip with signal processing capability. In the implementation process, each step of the method for compressing test vectors in the embodiment of the present application may be completed by hardware integrated logic circuits in the processor 702 or software instructions.

The processor 702 may also be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, or discrete hardware components. The methods, steps, and logic diagrams disclosed in the embodiments of the present application may be implemented or executed. The general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor. The software module may be located in a mature storage medium in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 701, and the processor 702 reads the information in the memory 701, and combines its hardware to complete the functions required to be performed by the units included in the device for compressing the test vector of the embodiment of the present application, or executes the method for compressing the test vector of the embodiment of the present application.

The communication interface 703 uses a transceiver such as, but not limited to, a transceiver to implement communication between the device 700 and other devices or a communication network. For example, the traffic data of an unknown device can be obtained through the communication interface 703.

The bus 704 may include a path for transmitting information between various components of the device 700 (eg, the memory 701 , the processor 702 , and the communication interface 703 ).

It should be noted that although the above device 700 only shows a memory, a processor, and a communication interface, in the specific implementation process, those skilled in the art should understand that the device 700 may also include other devices necessary for normal operation. At the same time, according to specific needs, those skilled in the art should understand that the device 700 may also include hardware devices for implementing other additional functions. In addition, those skilled in the art should understand that the device 700 may also only include the devices necessary for implementing the embodiments of the present application, and does not necessarily include all the devices shown in FIG. 7.

An embodiment of the present application also provides a computer-readable storage medium that stores program code for execution by a device, wherein the program code includes instructions for executing the steps in the above-mentioned method for compressing test vectors.

An embodiment of the present application also provides a computer program product, which includes a computer program stored on a computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer executes the above-mentioned method of compressing test vectors.

The computer-readable storage medium mentioned above may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

A method for generating a compressed test vector, comprising:

According to the decompression matrix corresponding to the chip under test, a first linear correlation matrix and a first maximally independent group are obtained, wherein the decompression matrix is a matrix corresponding to the decompression circuit structure of the chip under test;

Filling an implicit value into a first target bit in a first background vector according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector, wherein the first target bit includes all or part of the irrelevant bits in the first background vector;

A compressed test vector is generated according to the second background vector.
The method according to claim 1, characterized in that the step of filling the first target bit in the first background vector with an implicit value according to the first linear correlation matrix and/or the first maximally independent group to obtain the second background vector comprises:

Determine, according to the first linear correlation matrix and the first maximally independent group, first target bit information for indicating a first target bit, wherein the first target bit information is a second linear correlation matrix;

According to the first target bit information, an implicit value is filled in the first target bit to obtain a second background vector.
The method according to claim 2 is characterized in that the determining, according to the first linear correlation matrix and the first maximally independent group, first target bit information indicating the first target bit, the first target bit information being a second linear correlation matrix, comprises:

According to the decompression matrix, obtaining a second maximal independent group of coefficient matrices of a first linear equation group corresponding to the first background vector, wherein the first linear equation group includes a decompression equation corresponding to the first background vector;

According to the first maximally irrelevant group, adding the orthogonal complement of the second maximally irrelevant group to the second maximally irrelevant group to obtain a third maximally irrelevant group;

The second linear correlation matrix is determined according to the third maximally irrelevant group, the first maximally irrelevant group and the first linear correlation matrix.
The method according to claim 2 or 3, characterized in that filling the first target bit with an implicit value according to the first target bit information comprises:

Determine the position of the first target bit according to whether the element in the second linear correlation matrix is 1, and the don't care bits in the first target bit correspond to the elements in the second linear correlation matrix one by one;

Fill the determined position of the first target bit with an implicit value according to the decompression matrix and the first background vector.
The method according to claim 1, characterized in that the step of filling an implicit value into a first target bit in a first background vector according to the first linear correlation matrix and/or the first maximally independent group to obtain a second background vector comprises:

Determine, according to the first maximally irrelevant group, first target bit information for indicating a first target bit, wherein the first target bit information is a target column vector interval in the first background vector;

According to the first target bit information, an implicit value is filled in the first target bit to obtain a second background vector.
The method according to claim 5, characterized in that the first background vector includes at least one column vector, the first maximally irrelevant group corresponds to the column vector one-to-one, and determining the first target bit information indicating the first target bit according to the first maximally irrelevant group comprises:

The target column vector interval is determined according to the ranks of the plurality of the first maximally unrelated groups, and the target column vector interval includes at least one continuous column vector.
The method according to claim 6, characterized in that the step of determining the target column vector interval according to the ranks of the plurality of first maximally unrelated groups comprises:

According to the decompression matrix and the first background vector, obtaining at least one second linear equation group, the second linear equation group includes a decompression equation of the first background vector, and the second linear equation group has a one-to-one correspondence with a continuous column vector interval in the first background vector;

Determine at least one first column vector interval according to the at least one second linear equation group, wherein the number of linearly independent equations of the second linear equation group corresponding to the first column vector interval is greater than a first threshold;

Determine a second column vector interval according to the at least one first column vector interval, where the second column vector interval is a column vector interval including the largest number of column vectors in the at least one first column vector interval;

The target column vector interval is determined according to the second column vector interval, and the target column vector interval includes the second column vector interval.
The method according to claim 7, characterized in that the step of determining the target column vector interval according to the second column vector interval comprises:

Determine that the rank of at least one of the first maximally unrelated groups corresponding to the second column vector interval is a first value;

Determine whether the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is equal to the first value;

According to the judgment result, the second column vector interval is updated to the third column vector interval;

Determine that the rank of at least one of the first maximally independent groups corresponding to a fourth column vector interval is equal to the number of linearly independent equations of the second linear equation group corresponding to the fourth column vector interval, and the fourth column vector interval is an adjacent column vector interval of the third column vector interval;

The target column vector interval is determined to be a union of the third column vector interval and the fourth column vector interval.
The method according to claim 8, characterized in that the updating of the second column vector interval to a third column vector interval according to the judgment result comprises:

When the judgment result is that the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is not equal to the first numerical value, the values of some constant terms in the linearly independent equations are determined so that the second column vector interval is updated to the third column vector interval, and the number of linearly independent equations of the second linear equation group corresponding to the third column vector interval is equal to the first numerical value.
The method according to any one of claims 5 to 9, characterized in that filling the first target bit with an implicit value according to the first target bit information comprises:

Calculate the implicit value of the don't care bits in the target column vector interval according to the target column vector interval and the decompression matrix;

The first target bit is filled with the implicit value.
The method according to any one of claims 1 to 10, characterized in that the product of the first linear correlation matrix and the first maximal independent group corresponds to a matrix block row of the decompressed matrix; or

The product of the first linear dependence matrix and the first maximally independent group corresponds to the decompressed matrix.
A device for generating a compressed test vector, characterized in that the device comprises a processing module, wherein the processing module is used to:

According to the decompression matrix corresponding to the chip under test, a first linear correlation matrix and a first maximally independent group are obtained, wherein the decompression matrix is a matrix corresponding to the decompression circuit structure of the chip under test;

Filling an implicit value into a first target bit in a first background vector according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector, wherein the first target bit includes all or part of the irrelevant bits in the first background vector;

A compressed test vector is generated according to the second background vector.
The device according to claim 12, characterized in that the processing module is specifically used to:

Determine, according to the first linear correlation matrix and the first maximally independent group, first target bit information for indicating a first target bit, wherein the first target bit information is a second linear correlation matrix;

According to the first target bit information, an implicit value is filled in the first target bit to obtain a second background vector.
The device according to claim 13, characterized in that the processing unit is further specifically used for:

According to the decompression matrix, obtaining a second maximal independent group of coefficient matrices of a first linear equation group corresponding to the first background vector, wherein the first linear equation group includes a decompression equation corresponding to the first background vector;

According to the first maximally irrelevant group, adding the orthogonal complement of the second maximally irrelevant group to the second maximally irrelevant group to obtain a third maximally irrelevant group;

The second linear correlation matrix is determined according to the third maximally irrelevant group, the first maximally irrelevant group and the first linear correlation matrix.
The device according to claim 13 or 14, characterized in that the processing unit is further specifically used for:

Determine the position of the first target bit according to whether the element in the second linear correlation matrix is 1, and the don't care bits in the first target bit correspond to the elements in the second linear correlation matrix one by one;

Fill the determined position of the first target bit with an implicit value according to the decompression matrix and the first background vector.
The device according to claim 12, characterized in that the processing unit is specifically used for:

Determine, according to the first maximally irrelevant group, first target bit information for indicating a first target bit, wherein the first target bit information is a target column vector interval in the first background vector;

According to the first target bit information, an implicit value is filled in the first target bit to obtain a second background vector.
The device according to claim 16, characterized in that the first background vector includes at least one column vector, the first maximally irrelevant group corresponds to the column vector one by one, and the processing unit is further specifically used for:

The target column vector interval is determined according to the ranks of the plurality of the first maximally unrelated groups, and the target column vector interval includes at least one continuous column vector.
The device according to claim 17, characterized in that the processing unit is further specifically used for:

According to the decompression matrix and the first background vector, obtaining at least one second linear equation group, the second linear equation group includes a decompression equation of the first background vector, and the second linear equation group has a one-to-one correspondence with a continuous column vector interval in the first background vector;

Determine at least one first column vector interval according to the at least one second linear equation group, wherein the number of linearly independent equations of the second linear equation group corresponding to the first column vector interval is greater than a first threshold;

Determine a second column vector interval according to the at least one first column vector interval, where the second column vector interval is a column vector interval including the largest number of column vectors in the at least one first column vector interval;

The target column vector interval is determined according to the second column vector interval, and the target column vector interval includes the second column vector interval.
The device according to claim 18, characterized in that the processing unit is further specifically used for:

Determine that the rank of at least one of the first maximally unrelated groups corresponding to the second column vector interval is a first value;

Determine whether the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is equal to the first value;

According to the judgment result, the second column vector interval is updated to the third column vector interval;

Determine that the rank of at least one of the first maximally independent groups corresponding to a fourth column vector interval is equal to the number of linearly independent equations of the second linear equation group corresponding to the fourth column vector interval, and the fourth column vector interval is an adjacent column vector interval of the third column vector interval;

The target column vector interval is determined to be a union of the third column vector interval and the fourth column vector interval.
The device according to claim 19, characterized in that the processing unit is further used for:

When the judgment result is that the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is not equal to the first numerical value, the values of some constant terms in the linearly independent equations are determined so that the second column vector interval is updated to the third column vector interval, and the number of linearly independent equations of the second linear equation group corresponding to the third column vector interval is equal to the first numerical value.
The device according to any one of claims 16 to 20, characterized in that the processing unit is further used for:

Calculate the implicit value of the don't care bits in the target column vector interval according to the target column vector interval and the decompression matrix;

The first target bit is filled with the implicit value.
The device according to any one of claims 12 to 21, characterized in that the product of the first linear correlation matrix and the first maximal independent group corresponds to a matrix block row of the decompressed matrix; or

The product of the first linear dependence matrix and the first maximally independent group corresponds to the decompressed matrix.
A device for generating a compressed test vector, characterized in that it comprises a processor and a memory, wherein the memory is used to store a program, and the processor is used to call and run the program from the memory to execute the method described in any one of claims 1 to 11.
A computer-readable storage medium, characterized in that it includes a computer program, and when the computer program is run on a computer, the computer is caused to execute the method according to any one of claims 1 to 11.