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WO2023137786A1 - 驱动扫描电路及显示面板 - Google Patents

驱动扫描电路及显示面板 Download PDF

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Publication number
WO2023137786A1
WO2023137786A1 PCT/CN2022/074186 CN2022074186W WO2023137786A1 WO 2023137786 A1 WO2023137786 A1 WO 2023137786A1 CN 2022074186 W CN2022074186 W CN 2022074186W WO 2023137786 A1 WO2023137786 A1 WO 2023137786A1
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WO
WIPO (PCT)
Prior art keywords
pull
register
signal lines
coupled
signal
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Application number
PCT/CN2022/074186
Other languages
English (en)
French (fr)
Inventor
刘毅
周颖
Original Assignee
惠州华星光电显示有限公司
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 惠州华星光电显示有限公司, Tcl华星光电技术有限公司 filed Critical 惠州华星光电显示有限公司
Priority to US17/636,879 priority Critical patent/US11756499B2/en
Priority to JP2022509677A priority patent/JP2024516751A/ja
Publication of WO2023137786A1 publication Critical patent/WO2023137786A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays

Definitions

  • the invention relates to the field of display technology, in particular to a driving scanning circuit and a display panel.
  • the GOA (gate driver array) units on the left and right sides jointly drive the horizontal scanning lines, and the scanning lines are connected with multiple pixels in series, and the scanning lines have resistive and capacitive loads.
  • the same number of clock (CK) traces are arranged symmetrically on both sides of the circuit, and an even number (such as 2N) of clock traces needs to be arranged on a single-sided bezel, resulting in a large wiring area required for a single-sided bezel, which does not meet the requirements of a narrow bezel panel.
  • the invention provides a driving scanning circuit and a display panel, which are used to improve the problem of realizing a narrow border panel in the prior art.
  • a first aspect of the present invention provides a driving scanning circuit, which includes: an even number of signal lines, which are divided into odd groups of signal lines and even groups of signal lines; and multi-level scanning subcircuits, each level of scanning subcircuits includes a component, the component is coupled between the odd group of signal lines and the even group of signal lines, the component includes a register and a pull-down part, and a load is coupled between the register and the pull-down part; Any two of the register parts separated by N stages are cascaded with each other, and N is half of the total number of the even-numbered signal lines; wherein the register parts and the pull-down parts adjacent to one side of the load are coupled to different signal lines in the same group of signal lines; and the register parts and the pull-down parts adjacent to the same side of the load are integrated and configured.
  • the wiring occupied area of the adjacent register part and the pull-down part on one side of the load can be reduced, and the frame width can be greatly reduced; the register part and the pull-down part can also be mixed and drawn on the layout, so that the border width can be greatly compressed.
  • the signal lines are effectively distributed to both sides of the load, and the number of signal lines on one side is halved, which can greatly reduce the width of the frame, so that the single-drive configuration can be used to drive the scanning circuit.
  • one of the register portion and the pull-down portion is coupled between the load and a signal line of the odd set of signal lines
  • the other of the register portion and the pull-down portion is coupled between the load and a signal line of the even set of signal lines. Therefore, the signal lines are effectively distributed to both sides of the load, and the register part and the pull-down part in the same component are respectively coupled to the odd group signal lines and the even group signal lines on different sides, which can greatly reduce the frame width.
  • the number of the even numbered signal lines is 2N, and N is a positive integer;
  • the number of the even-numbered signal lines is 2N, and N is a positive integer;
  • the multi-level scanning sub-circuit includes an n-th scanning sub-circuit, and n is a positive integer; if n ⁇ N, the register section in the n-th scanning sub-circuit inputs a preset enabling signal; if n>N, the registering section in the n-th scanning sub-circuit outputs an enabling signal to the registering section in the (n+N)th scanning sub-circuit. Therefore, it is beneficial to apply different driving and scanning circuits, and realize the improvement of the driving and scanning circuits without affecting the charging of the panel pixels.
  • the number of transistors included in the register section is greater than the number of transistors included in the pull-down section. Therefore, the number of transistors included in the pull-down part is less than the number of transistors included in the register part, the circuit structure of the pull-down part can be effectively simplified, and the driving and scanning circuit can be improved without affecting the charging of the panel pixels.
  • the pull-down part includes a pull-down transistor, a control end of the pull-down transistor is coupled to a pulse port, a first end of the pull-down transistor is coupled to a scan-in port, a second end of the pull-down transistor is coupled to a low-order port, and the load is coupled between the scan-in port of the pull-down part and a scan-out port of the register part. Therefore, the circuit structure of the pull-down part is effectively simplified, and the scan output port of the register part and the scan input port of the pull-down part are used to jointly drive the load, so as to realize the improvement of the drive scan circuit without affecting the charging of the panel pixels.
  • the number of the even-numbered signal lines is 2N, and N is a positive integer; the even-numbered signal lines transmit an even-numbered pulse signal, and in a transmission configuration, the subsequent pulse signal of two sequentially adjacent pulse signals is delayed by one time unit from the preceding pulse signal, and each of the pulse signals is configured as a pulse width modulation signal with a duty ratio of (N-1)/2N. Therefore, in accordance with this signal timing, the registers connected to the pull-down cascade are all odd-numbered or even-numbered, so the registers cascaded with each other can be placed on the same side of the load, and provide half the number of signal line configurations on the same side of the panel, which is conducive to the realization of narrow-frame panels.
  • a second aspect of the present invention provides a driving scanning circuit, comprising: an even number of signal lines configured to be divided into an odd group of signal lines and an even group of signal lines; Any two register units on one side of the load that are separated by N stages are cascaded with each other, and N is half of the total number of the even-numbered signal lines. Therefore, through separate and alternately arranged register parts and pull-down parts, the signal lines are effectively distributed to both sides of the load, the number of signal lines on one side is halved, and the width of the frame can be greatly reduced, so as to realize the driving and scanning circuit with a single-drive configuration.
  • one of the register portion and the pull-down portion is coupled between the load and a signal line of the odd set of signal lines
  • the other of the register portion and the pull-down portion is coupled between the load and a signal line of the even set of signal lines. Therefore, the signal lines are effectively distributed to both sides of the load, and the register part and the pull-down part in the same component are respectively coupled to the odd group signal lines and the even group signal lines on different sides, which can greatly reduce the frame width.
  • the register part and the pull-down part adjacent to one side of the load are coupled to different signal lines in the same group of signal lines. Therefore, the area occupied by the wiring of the register part and the pull-down part adjacent to one side of the load can be reduced, and the frame width can be greatly reduced.
  • the number of the even signal lines is 2N, and N is a positive integer;
  • the number of the even-numbered signal lines is 2N, and N is a positive integer;
  • the multi-level scanning sub-circuit includes an n-th scanning sub-circuit, and n is a positive integer; if n ⁇ N, the register section in the n-th scanning sub-circuit inputs a preset enabling signal; if n>N, the registering section in the n-th scanning sub-circuit outputs an enabling signal to the registering section in the (n+N)th scanning sub-circuit. Therefore, it is beneficial to apply different driving and scanning circuits, and realize the improvement of the driving and scanning circuits without affecting the charging of the panel pixels.
  • the number of transistors included in the register section is greater than the number of transistors included in the pull-down section. Therefore, the number of transistors included in the pull-down part is less than the number of transistors included in the register part, the circuit structure of the pull-down part can be effectively simplified, and the driving and scanning circuit can be improved without affecting the charging of the panel pixels.
  • the pull-down part includes a pull-down transistor, a control terminal of the pull-down transistor is coupled to a pulse port, a first terminal of the pull-down transistor is coupled to a scan-in port, a second terminal of the pull-down transistor is coupled to a low-order port, and the load is coupled between the scan-in port of the pull-down part and a scan-out port of the register part. Therefore, the circuit structure of the pull-down part is effectively simplified, and the scan output port of the register part and the scan input port of the pull-down part are used to jointly drive the load, so as to realize the improvement of the drive scan circuit without affecting the charging of the panel pixels.
  • the number of the even-numbered signal lines is 2N, and N is a positive integer; the even-numbered signal lines transmit an even-numbered pulse signal, and in a transmission configuration, the subsequent pulse signal of two sequentially adjacent pulse signals is delayed by one time unit from the preceding pulse signal, and each of the pulse signals is configured as a pulse width modulation signal with a duty ratio of (N-1)/2N. Therefore, in accordance with this signal timing, the registers connected to the pull-down cascade are all odd-numbered or even-numbered, so the registers cascaded with each other can be placed on the same side of the load, and provide half the number of signal line configurations on the same side of the panel, which is conducive to the realization of narrow-frame panels.
  • the register part and the pull-down part adjacent to the same side of the load are integrated and configured. Therefore, the registration part and the pull-down part can be mixed and drawn on the layout, so that the width of the frame can be greatly reduced. After the mixed typesetting, the width of the registration part can be reduced. In addition to the reduction in the number of signal lines on one side, the width of the reduced registration part can be saved by 30% of the original width of the registration part, which can be applied to liquid crystal display panels.
  • a third aspect of the present invention provides a display panel, including the above driving and scanning circuit.
  • each level of scanning sub-circuit includes the component, the component is coupled between the odd group of signal lines and the even group of signal lines, the component includes the register part and the pull-down part, and the load is coupled between the register part and the pull-down part; the register parts and the pull-down parts arranged on the same side of the load are alternately arranged, and any two register parts separated by N stages on one side of the load are cascaded with each other, and N is half of the total number of the even-numbered signal lines.
  • the signal lines are effectively distributed to both sides of the load, the number of signal lines on one side is halved, and the area required for wiring on one side is reduced, which can greatly reduce the width of the frame, reduce power consumption, and reduce delay.
  • the single-drive configuration is used to drive and scan the circuit, and the circuit is improved without affecting the charging of the panel pixels.
  • FIG. 1 is a schematic circuit diagram of a driving scanning circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic circuit diagram of a register unit according to an embodiment of the present invention.
  • FIG. 3 is a schematic circuit diagram of the pull-down part of the embodiment of the present invention.
  • FIG. 4 is a timing schematic diagram of the pulse waveform and cascading relationship of the 8CK architecture.
  • FIG. 5 is a block diagram of an exemplary shift register.
  • FIG. 6 is a waveform correspondence diagram between start and restart (start-reset) of a single-stage shift register.
  • Fig. 7 is a schematic diagram of saving space in the mixed typesetting of the register part and the pull-down part on the same side according to the embodiment of the present invention.
  • first and second are used for description purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, features defined as “first” and “second” may explicitly or implicitly include one or more of said features.
  • “plurality” means two or more, unless otherwise specifically defined.
  • a first aspect of the present invention provides a driving and scanning circuit, which is applicable to a liquid crystal display panel, such as a narrow frame liquid crystal display panel, but not limited thereto.
  • the driving scanning circuit includes: an even number of signal (CK) lines and a multi-level scanning sub-circuit D for driving a plurality of horizontal scanning lines in a display panel.
  • the scanning lines can be regarded as a plurality of pixels connected in series (such as a plurality of pixels arranged horizontally in a display panel), and the scanning lines carry resistive-capacitive loads.
  • CKn (n is a positive integer) is used to represent different signal lines and the signals they transmit.
  • CK1 may be used to represent signal line CK1 or signal CK1 in a paragraph.
  • the even signal lines (such as CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8) can be configured into odd groups of signal lines (such as CK1, CK3, CK5, CK7) and even groups of signal lines (such as CK2, CK4, CK6, CK8).
  • the multi-level scanning sub-circuit D includes 10-level scanning sub-circuit D
  • each level of scanning sub-circuit D includes an assembly (assembly) A
  • the assembly A is coupled between the odd set of signal lines (such as CK1, CK3, CK5, CK7) and the even set of signal lines (such as CK2, CK4, CK6, CK8), and the assembly A includes a register part 1 and a pull-down part 2.
  • the register unit 1 can be configured as a shift register (also marked as GOA), for example, the pull-down unit 2 can be configured as a pull-down unit (also marked as PDU), and a load B is coupled between the register unit 1 and the pull-down unit 2.
  • the load B can be configured to include a plurality of pixels connected in series, and the load B has a resistive-capacitive load.
  • component A of the scanning sub-circuit D of the first level includes a register part 1 (such as GOA1) and a pull-down part 2 (such as PDU1)
  • component A of the scanning sub-circuit D of the second level includes a register part 1 (such as GOA2) and a pull-down part 2 (such as PDU2)
  • component A of the scanning sub-circuit D of the third level includes a register part 1 (such as GOA3) and a pull-down part 2 (such as PDU3)
  • component A of the fifth-level scanning subcircuit D includes a register part 1 (such as GOA5) and a pull-down part 2 (such as PDU5)
  • component A of the sixth-level scanning sub-circuit D includes a register part 1 (such as GOA6) and a pull-down part 2 (such as PDU6)
  • component A of the seventh-level scanning sub-circuit D includes a register part 1
  • the register part 1 and the pull-down part 2 in the multi-level scanning subcircuit D can be configured to be alternately arranged on both sides of the load B step by step.
  • the registration part 1 (such as GOA2) of the second-level scanning subcircuit D is on the other side of the load B (such as the right side);
  • the registration part 1 (such as GOA3) of the third-level scanning sub-circuit D is on the side of the load B (such as the left side), and the pull-down part 2 (such as PDU3) of the third-level scanning sub-circuit D is on the other side of the load B (such as the right side);
  • the register unit 1 (such as GOA10 ) of the tenth-level scanning subcircuit D is on the other side of the load B (such as the right side).
  • the register parts 1 and the pull-down parts 2 arranged on the same side of the load B are alternately arranged, for example, the register parts 1 of the odd-numbered scanning sub-circuit D (such as GOA1, GOA3, GOA5, GOA7, GOA9) and the pull-down parts 2 of the even-numbered scanning sub-circuit D (such as PDU2, PDU4, PDU6, PDU8, PDU10) are alternately arranged on the side of the load B (such as the left side), such as from top to bottom arranged as GOA1, PDU2, GOA3, PDU4, GOA5, PDU6, GOA7, PDU8, GOA9, PDU10, etc.; (As on the right side) are arranged alternately step by step, for example, they are arranged as PDU1, GOA2, PDU3, GOA4, PDU5, GOA6, PDU7, GOA8, PDU9, GOA10, etc. from top to bottom.
  • the register parts 1 of the odd-numbered scanning sub-circuit D such as GOA1, GOA3,
  • one of the register part 1 and the pull-down part 2 is coupled between the load B and a signal line in the odd group signal lines (such as CK1, CK3, CK5, CK7), and the other of the register part 1 and the pull-down part 2 is coupled between the load B and a signal line in the even group signal lines (such as CK2, CK4, CK6, CK8);
  • the part 1 and the pull-down part 2 are coupled to different signal lines in the same group of signal lines (eg odd groups of signal lines CK1 , CK3 , CK5 , CK7 or even groups of signal lines CK2 , CK4 , CK6 , CK8 ).
  • 8CK with 8-level scanning sub-circuits is used as an example as a module M, and there may be multiple modules M in a driving scanning circuit.
  • odd-level scanning sub-circuit D registers 1 (such as GOA1, GOA3, GOA5, GOA7) are respectively coupled to odd groups of signal lines (such as CK1, CK3, CK5, CK7); They are respectively coupled to even groups of signal lines (such as CK2, CK4, CK6, CK8).
  • the signal line numbers are sequentially incremented from 1 to 8 and used repeatedly, such as CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8, CK1, CK2, CK3, ..., CK7, CK8, CK1, CK2, CK3, ..., CK7, CK8, etc. 1) The number gap.
  • Line CK2 the pull-down part 2 (such as PDU2) of the second-level scanning sub-circuit D is coupled to the signal line CK5;
  • the register part 1 (such as GOA3) of the third-level scanning sub-circuit D is coupled to the signal line CK3, and the pull-down part 2 (such as PDU3) of the third-level scanning sub-circuit D is coupled to the signal line CK6; CK7;
  • the registration part 1 (such as GOA5) of the fifth-level scanning subcircuit D is coupled to the signal line CK5, and the pull-down part 2 (such as PDU5) of the fifth-level scanning sub-circuit D is coupled to the signal line CK8;
  • the sixth-level scanning sub-circuit D The registration part 1 (such as GOA6) is coupled to the signal line CK6, and the pull-down
  • the signal line number of the Stock 1 and the Drawing 2 coupling can be configured according to one rule.
  • the registration unit 1 may include a first pulse (Sync) port 11, a start input (Start1) port 12, a restart (Reset) port 13 and a scan output (Output1) port 14, but not limited thereto.
  • the registration unit 1 may also include other start input ports and/or scan output ports, etc.;
  • the pull-down part 2 may also include other ports, such as low-order ports; the load B is coupled between the scan-out port 14 and the scan-in port 22 .
  • the register unit 1 can be configured as a GOA (gate driver on array) circuit, including a plurality of transistors and a capacitor, the transistor includes a control terminal, a first terminal and a second terminal, and the transistor can be, for example, a thin film transistor (TFT) with a gate, a source and a drain; for example, the register unit 1 includes an input unit 1A, an output unit 1B, a maintenance unit 1C, a first control unit 1D, a second control unit 1E and a reset Unit 1F.
  • GOA gate driver on array
  • the input unit 1A includes a first transistor T11, the control terminal of the first transistor T11 is coupled to the enable input port 12 for inputting an initial enable signal STV or a previous stage enable signal ST(n-N), and the first end of the first transistor T11 is coupled to a previous stage scan port 15 for inputting a previous stage scan signal G(n-N).
  • the output unit 1B includes a second transistor T21, a third transistor T22, and a capacitor Cbt.
  • the control terminal of the second transistor T21 and the control terminal of the third transistor T22 are coupled to the second terminal of the first transistor T11 to form a first contact Q.
  • the first terminal of the second transistor T21 and the first terminal of the third transistor T22 are coupled to a pulse port, such as a first pulse port 11, for inputting a first pulse signal CK(i), and the second transistor T2
  • the second end of 1 is coupled to the scan output port 14 for outputting an nth level scanning signal G(n)
  • the second end of the third transistor T22 is coupled to a restart port 13 for outputting an nth level start signal ST(n)
  • the capacitor Cbt is coupled between the control end and the second end of the second transistor T21.
  • the sustain unit 1C includes a fourth transistor T31 and a fifth transistor T41, the control terminal of the fourth transistor T31 and the control terminal of the fifth transistor T41 are coupled to a subsequent scan port 16 for inputting a subsequent scan signal G(n+N), the first terminal of the fourth transistor T31 is coupled to the scan output port 14, and the second terminal of the fourth transistor T31 is coupled to a first low port 19 for inputting a first low signal VSSG.
  • a first end of the fifth transistor T41 is coupled to the first node Q, and a second end of the fifth transistor T41 is coupled to a second low port 1 a for inputting a second low signal VSSQ.
  • the first control unit 1D includes a sixth transistor T51, a seventh transistor T52, an eighth transistor T53, a ninth transistor T54, a tenth transistor T32, and an eleventh transistor T42.
  • the control terminal and the first terminal of the sixth transistor T51 and the first terminal of the eighth transistor T53 are coupled to a first control port 17 for inputting a first control signal LC1.
  • the second terminal of the sixth transistor T51 is coupled to the first terminal of the seventh transistor T52 and the first terminal of the eighth transistor T53.
  • the control terminal of the eighth transistor T53, the control terminal of the seventh transistor T52 and the control terminal of the ninth transistor T54 are coupled to the second terminal of the first transistor T11, the second terminal of the seventh transistor T52, the second terminal of the ninth transistor T54, the second terminal of the tenth transistor T32 and the second terminal of the eleventh transistor T42 are coupled to the second low port 1a, and the second terminal of the eighth transistor T53 is coupled to the first terminal of the ninth transistor T54, the control terminal of the tenth transistor T32 and the tenth transistor T42.
  • a control terminal of a transistor T42 , the first terminal of the tenth transistor T32 is coupled to the scan output port 14 , and the first terminal of the eleventh transistor T42 is coupled to the first node Q.
  • the second control unit 1E includes a twelfth transistor T61, a thirteenth transistor T62, a fourteenth transistor T63, a fifteenth transistor T64, a sixteenth transistor T33, and a seventeenth transistor T43.
  • the control terminal and the first terminal of the twelfth transistor T61 and the first terminal of the fourteenth transistor T63 are coupled to a second control port 18 for inputting a second control signal LC2.
  • the second terminal of the twelfth transistor T61 is coupled to the thirteenth transistor T.
  • the first terminal of 62 and the control terminal of the fourteenth transistor T63, the control terminal of the thirteenth transistor T62 and the control terminal of the fifteenth transistor T64 are coupled to the second terminal of the first transistor T11, the second terminal of the thirteenth transistor T62, the second terminal of the fifteenth transistor T64, the second terminal of the sixteenth transistor T33 and the second terminal of the seventeenth transistor T43 are coupled to the second low port 1a, and the second terminal of the fourteenth transistor T63 is coupled to the fifteenth transistor T64.
  • the first terminal, the control terminal of the sixteenth transistor T33 and the control terminal of the seventeenth transistor T43, the first terminal of the sixteenth transistor T33 is coupled to the scan output port 14, the first terminal of the seventeenth transistor T43 is coupled to the first node Q.
  • the reset unit 1F includes an eighteenth transistor T44, a control terminal of the eighteenth transistor T44 is coupled to a reset (Re-setup) port 10 for inputting a reset signal RST, a first terminal of the eighteenth transistor T44 is coupled to the first node Q, and a second terminal of the eighteenth transistor T44 is coupled to the second low port 1a.
  • the first pulse port 11 can be used to input the first pulse signal CK(i), such as a pulse signal from one of the even signal lines (such as CK1-CK8); in addition, the initial start signal STV can be input to the opening input port 12 of the registration part 1 of the first to fourth-level scanning sub-circuit D, and the opening input port 12 of the registration part 1 of the nth (n>4) scanning sub-circuit D can input a first
  • the (n-4) level start signal ST(n-4) is the start signal from the registration part 1 of the (n-4) level scan sub-circuit D;
  • the restart port 13 can output the n-level start signal ST(n);
  • the scan output port 14 can output the n-level scan signal G(n), and the n-level scan signal G(n) is output to the load B to drive the load B of the n-level scan sub-circuit D, such as a plurality of serially connected pixels in the n-
  • any two registers 1 (such as GOA1 , GOA5 , GOA9 , .
  • the register section 1 in the circuit D inputs the preset enable signal STV; if n>N, the register section 1 in the nth-level scanning subcircuit D outputs the enable signal ST(n) to the enable input port 12 of the register section 1 in the (n+N)th level scanning subcircuit D.
  • the pull-down part 2 includes a pull-down transistor T, but it is not limited thereto.
  • the pull-down part 2 may also include other components (such as other transistors, etc.); the control terminal of the pull-down transistor T is coupled to a pulse port, such as a second pulse port 21, for inputting a second pulse signal CK(j), such as a pulse signal from one of the even-numbered signal lines CK1-CK8.
  • a pulse port such as a second pulse port 21
  • CK(j) such as a pulse signal from one of the even-numbered signal lines CK1-CK8.
  • the second end of the pull-down transistor T is coupled to a low port 23 for inputting the first low signal VSSG.
  • the nth-level scanning signal G(n) passing through the load B of the n-th-level scanning sub-circuit D can be guided to the low-order port 23 through the second pulse signal CK(j).
  • the drive scan circuit belongs to a single-drive pull-down GOA architecture.
  • the odd sets of signal lines CK1, CK3, CK5, and CK7 are arranged on one side of the load B, and the even sets of signal lines CK2, CK4, CK6, and CK8 are arranged on the other side of the load B, so that the number of signal lines on one side is halved, which is beneficial for narrow bezel panels.
  • the register part 1 and the pull-down part 2 of the component A are alternately arranged row by row on both sides of the load B. The register part 1 can output the scan signal for driving the scan line.
  • the pull-down part 2 is a single thin film transistor, which is controlled by a periodic square wave signal as a pulse signal. When the pulse signal is at a high level, the drain and the source are turned on to pull down the potential of the scan line.
  • the register part 1 and the pull-down part 2 are alternately arranged vertically on one side of the load B.
  • the rising edge (rising edge) is only driven by the register part 1, and the falling edge (falling edge) is jointly driven by the register part 1 and the pull-down part 2.
  • the speed of the falling edge is the key factor affecting the in-plane charging.
  • the high-level period of CK is marked by a long box (for example, G1, G2, G3, ..., G5, ..., G9, ..., G26, G27, ..., but not limited to this), and its rising delay time is indicated by the digital scale in the upper digital square.
  • the gate signal of each stage will be synchronized with a CK high-level square wave, and then remain in a low-level state.
  • the signal synchronous with G1 is shown as the waveform of G1 in the figure.
  • the high-level pulses synchronized with each gate signal are marked in the high-level box of CK.
  • start cascades are marked with the same kind of box.
  • the start signal STV turns on the first-level to n-th level registers 1 (such as GOA1 to GOA(n)), such as the 8CK system, then the first four levels of registers 1 (such as GOA1 to GOA4)) use the start signal STV as the start signal.
  • n-th level registers 1 such as GOA1 to GOA(n)
  • the first four levels of registers 1 such as GOA1 to GOA4
  • GOA1 provides an open signal to GOA5 (as shown in Figure 4, the frame lines of G1 and G5 are both thin lines)
  • GOA5 provides an open signal to GOA9 (as shown in Figure 4, the frame lines of G5 and G9 are both thin lines)
  • GOA13, GOA17, GOA21, GOA25 are both thin lines
  • the rest have the same The same is true between the signals of the frame lines, and will not be repeated here.
  • the pull-down action of the gate of each stage is initiated by the pull-down part 2 on the opposite side of the register part 1, that is, a pull-down restart (reset) is provided, and its cascade relationship is indicated by the vertical line in the figure.
  • the PDU1 on the opposite side of GOA1 is driven by the square wave pulse provided by the signal line CK4 to GOA4, so at time 4, GOA1 loses synchronization with the signal CK1.
  • Other drop-down relationships are consistent with this.
  • the latter pulse signal in the two adjacent pulse signals is delayed by one time unit than the previous pulse signal.
  • the high level time period (such as G2) of the pulse signal CK2 is delayed by one time unit compared to the high level time period (such as G1) of the pulse signal CK1
  • the high level time period (such as G3) of the pulse signal CK3 is delayed by one time unit than the high level time period (such as G2) of the pulse signal CK2.
  • the duty cycle of (N-1)/(2N) is an important factor to realize the driving function of this single-drive GOA-PDU. Therefore, relying on this timing coordination, the GOAs connected to the pull-down cascade are all odd-numbered or even-numbered. Therefore, the cascaded GOAs can be placed on one side of the load (such as the pixels of the panel), and half the number of CK signal lines can be provided on the same side of the panel. This is conducive to the realization of narrow-frame panels. The number of CKs required for the pull-down PDU of each level will undergo a parity change.
  • the CK connected to the PDU of the odd-numbered GOA is an even-numbered CK
  • the even-numbered CK is on the opposite side of the odd-numbered CK.
  • the odd CK on one side (such as the left side) provides the drive for the odd-numbered GOA and the drive for the even-numbered PDU
  • an exemplary shift register 1' includes a plurality of ports 11', 12', 13', 14', 15', 16', 17', 18', 19' and 1a', and the port 11' is used to input signals CK (1) to CK (2N) as a synchronization (Sync) signal; t) signal; port 13' is used for output signal ST(n); port 14' is used for output signal G(n); port 15' is used for input signal G(n-N); port 16' is used for input signal G(n+N), as restart (Reset) signal; port 17', 18' are used for input signal LC1, LC2; port 19', 1a' are used for input signal VSSG, VSSQ.
  • signals LC1 and LC2 are high-level signals; signals VSSG and VSSQ are low-level direct current signals, and these two signals are pull-down maintenance power signal lines of the shift register; signals LC1, LC2 and signals VSSG, VSSQ may also be simplified into signals LC and signal VSS; the two open signals are synchronous open signals, and when the two open signals are both high level, the shift register 1' is activated.
  • the ports 13' and 14' start synchronizing the signal connected to the port 11', assuming a GOA
  • the circuit is driven by 2N CK lines, and the signals G(n-N) and ST(n-N) are the two open connection signals of the shift register 1' of the nth stage, and the signal G(n+N) or ST(n+N) is the restart signal of the shift register 1'.
  • a separate start (STV) line can be used to provide the start (start) signal to the ports 12', 15'.
  • Figure 6 is the GOA timing sequence driven by 8CK, wherein ST(n-4) and G(n-4) are square wave pulse signals half a cycle ahead of CK, and G(N+4) is a square wave pulse signal delayed half a cycle.
  • the nth stage shift register synchronous CK signal starts from the rising delay time of ST(n-4) (STV(n-4) as shown in the figure) and G(n-4), and the time of losing synchronization is the rising delay time of G(n+4).
  • the shift register 1' outputs the signal are ST(n) and G(n), and the signal of the first contact in the shift register 1' is Q(n).
  • a single scanning subcircuit of a dual-drive scanning circuit includes two shift registers 1' on both sides of a load, and there is one shift register 1' on both sides of the load.
  • the shift register 1' includes the GOA circuit of the first transistor to the eighteenth transistor.
  • the pull-down part 2 the load B has only the register part 1 or the pull-down part 2 on one side, and the pull-down part 2 has only one transistor.
  • the number of elements (such as transistors) of the pull-down part 2 on the load side and the shift register 1' is very different.
  • the cascade relationship of the plurality of pull-down parts is consistent with the cascade relationship of the multiple register parts.
  • the reset signal of a certain pull-down part 2 (such as PDU1) is the output (output) signal of the pull-down part 2 (such as PDU5)
  • the restart signal of another pull-down part 2 (such as PDU3) is the output signal of the pull-down part (such as PDU7).
  • the left side shows the GOA width W1 of the non-integrated configuration of the adjacent register part and the pull-down part on the same side
  • the right side shows the GOA width W2 of the integrated configuration of the adjacent register part and the pull-down part on the same side.
  • the GOA width can be reduced from W1 to W2. With the reduction of the number of CK lines on one side, the reduced GOA width savings can reach 30% of the original GOA width.
  • Table 1 is the waveform comparison data of the shift register 1' of the above-mentioned comparative example and the component A of the above-mentioned embodiment using a liquid crystal panel.
  • the high and low levels of the signal CK are 30V and -10V, by measuring the rising edge (referred to as rising, rising) and falling edge (referred to as falling, falling) time of the gate (Gate) square wave at 9 points (left, middle, right - upper, middle and lower). It can be found that the lower right (right-down) has the largest rise and fall time, which is the maximum load point.
  • the rise time of the GOA width W2 in Figure 7 is larger, about twice, but the fall time (this is an important indicator that affects the charging of pixels in the plane) is not much different. Therefore, the original fall time can be realized by optimizing the size of the TFTs of the register part and the pull-down part in the component.
  • One aspect of the present invention provides a driving scanning circuit, comprising: even signal lines configured to be divided into odd groups of signal lines and even groups of signal lines; and multi-level scanning subcircuits, each scanning subcircuit includes a component, the component is coupled between the odd group of signal lines and the even group of signal lines, the component includes a register part and a pull-down part, and a load is coupled between the register part and the pull-down part; the register parts and the pull-down parts on the same side of the load are alternately arranged, and any two on one side of the load are separated by N
  • the register parts are cascaded with each other, and N is half of the total number of the even-numbered signal lines.
  • the signal lines are effectively distributed to both sides of the load, the number of signal lines on one side is halved, and the width of the frame can be greatly reduced, so as to realize the driving and scanning circuit with a single-drive configuration.
  • one of the register portion and the pull-down portion is coupled between the load and a signal line in the odd set of signal lines, and the other of the register portion and the pull-down portion is coupled between the load and a signal line in the even set of signal lines. Therefore, the signal lines are effectively distributed to both sides of the load, and the register part and the pull-down part in the same component are respectively coupled to the odd group signal lines and the even group signal lines on different sides, which can greatly reduce the frame width.
  • the adjacent register part and the pull-down part on one side of the load are coupled to different signal lines in the same group of signal lines. Therefore, the area occupied by the wiring of the register part and the pull-down part adjacent to one side of the load can be reduced, and the frame width can be greatly reduced.
  • the number of the even-numbered signal lines is 2N, and N is a positive integer;
  • the number of the even-numbered signal lines is 2N, and N is a positive integer;
  • the multi-level scanning subcircuit includes an nth-level scanning subcircuit, and n is a positive integer; if n ⁇ N, the register part in the n-th level scanning subcircuit inputs a preset enable signal; if n>N, the register part in the n-th level scanning subcircuit outputs an enable signal to the register part in the (n+N)th level scanning subcircuit. Therefore, it is beneficial to apply different driving and scanning circuits, and realize the improvement of the driving and scanning circuits without affecting the charging of the panel pixels.
  • the number of transistors included in the register section is greater than the number of transistors included in the pull-down section. Therefore, the number of transistors included in the pull-down part is less than that of the register part, effectively simplifying the circuit structure of the pull-down part, and realizing the improvement of the driving and scanning circuit without affecting the charging of the panel pixels.
  • the pull-down part includes a pull-down transistor, a control end of the pull-down transistor is coupled to a pulse port, a first end of the pull-down transistor is coupled to a scan-in port, a second end of the pull-down transistor is coupled to a low-bit port, and the load is coupled between the scan-in port of the pull-down part and a scan-out port of the register part. Therefore, the circuit structure of the pull-down part is effectively simplified, and the scan output port of the register part and the scan input port of the pull-down part are used to jointly drive the load, so as to realize the improvement of the drive scan circuit without affecting the charging of the panel pixels.
  • the number of the even-numbered signal lines is 2N, and N is a positive integer; the even-numbered signal lines transmit an even-numbered pulse signal, and in a transmission configuration, the subsequent pulse signal of two sequentially adjacent pulse signals is delayed by one time unit from the preceding pulse signal, and each of the pulse signals is configured as a pulse width modulation signal with a duty ratio of (N-1)/2N. Therefore, in accordance with this signal timing, the registers connected to the pull-down cascade are all odd-numbered or even-numbered, so the registers cascaded with each other can be placed on the same side of the load, and provide half the number of signal line configurations on the same side of the panel, which is conducive to the realization of narrow-frame panels.
  • the register part and the pull-down part adjacent to the same side of the load are integrated and configured. Therefore, the registration part and the pull-down part can be mixed and drawn on the layout, so that the width of the frame can be greatly reduced. After the mixed typesetting, the width of the registration part can be reduced. In addition to the reduction in the number of signal lines on one side, the width of the reduced registration part can be saved by 30% of the original width of the registration part, which can be applied to liquid crystal display panels.
  • a display panel such as a liquid crystal display panel.
  • the display panel includes the driving and scanning circuit described above, and its implementation content and beneficial effects are described above, and will not be repeated here.
  • each scanning sub-circuit includes the component, the component is coupled between the odd group signal lines and the even group signal lines, the component includes the register part and the pull-down part, and the load is coupled between the register part and the pull-down part; the register parts and the pull-down parts arranged on the same side of the load are alternately arranged, and any two register parts separated by N stages on one side of the load are cascaded with each other, and N is half of the total number of the even-numbered signal lines.
  • the signal lines are effectively distributed to both sides of the load, the number of signal lines on one side is halved, and the area required for wiring on one side is reduced, which can greatly reduce the width of the frame, reduce power consumption, and reduce delay.
  • the single-drive configuration is used to drive and scan the circuit, and the circuit is improved without affecting the charging of the panel pixels.

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Abstract

一种驱动扫描电路及显示面板，所述驱动扫描电路包括：偶数条信号线，被配置分成奇数组信号线及偶数组信号线；及多级扫描子电路，每级扫描子电路包括一组件，所述组件耦接于所述奇数组信号线与所述偶数组信号线之间，所述组件包括一寄存部及一下拉部，所述寄存部与所述下拉部之间耦接一负载；设于所述负载的同侧的所述寄存部和所述下拉部交替排列，在所述负载的一侧的任意两个相隔N级的所述寄存部相互级联，N为所述偶数条信号线的总数的一半。

Description

驱动扫描电路及显示面板 技术领域
本发明涉及显示技术领域，具体涉及一种驱动扫描电路及显示面板。
背景技术
对于常见的显示面板来说，由左右两侧的GOA(gate driveron array)单元共同驱动横向的扫描线，所述扫描线串接多个像素，所述扫描线上带有电阻电容的负载。举例来说，在双侧驱动架构中，为了驱动所有的GOA，电路两侧对称布置相同数量的时钟(CK)走线，其中单侧边框需要布置偶数条(如2N)条时钟走线，致使单侧边框需要的布线面积较大，不符合窄边框面板的要求。
技术问题
本发明提供一种驱动扫描电路及显示面板，用于改善现有技术实现窄边框面板的问题。
技术解决方案
为解决上述问题，本发明的一第一方面提供一种驱动扫描电路，其包括：偶数条信号线，分为奇数组信号线及偶数组信号线；及多级扫描子电路，每级扫描子电路包括一组件，所述组件耦接于所述奇数组信号线与所述偶数组信号线之间，所述组件包括一寄存部及一下拉部，所述寄存部与所述下拉部之间耦接一负载；设于所述负载的同侧的所述寄存部和所述下拉部交替排列，在所述负载的一侧 的任意两个相隔N级的所述寄存部相互级联，N为所述偶数条信号线的总数的一半；其中在所述负载的一侧相邻的所述寄存部及所述下拉部耦接同一组信号线中的不同信号线；及在所述负载同侧相邻的寄存部和下拉部集成配置。从而，可降低在所述负载的一侧相邻的所述寄存部及所述下拉部的接线占用面积，可大幅缩减边框宽度；还可以把所述寄存部和下拉部在版图上混合绘制，这样可以大幅压缩边框宽度，经混合排版后，所述寄存部的宽度可缩小，加上单侧信号走线数量的减少，缩小后的寄存部宽度的节省量可以达到原本寄存部宽度的30％，可适用于液晶显示面板；还可通过分开且交替设置的寄存部及下拉部，将信号线有效分散到负载两侧，单侧信号线数量减半，可大幅缩减边框宽度，以便利用单驱的配置实现驱动扫描电路。
根据本发明的一实施例，在同一个所述组件中，所述寄存部及所述下拉部中的一者耦接于所述负载与所述奇数组信号线中的一信号线之间，所述寄存部及所述下拉部中的另一者耦接于所述负载与所述偶数组信号线中的一信号线之间。从而，将信号线有效分散到负载两侧，同一个所述组件中的所述寄存部及所述下拉部各自耦接位于不同侧的所述奇数组信号线及所述偶数组信号线，可大幅缩减边框宽度。
根据本发明的一实施例，所述偶数条信号线的数量为 2N，N为正整数；所述多级扫描子电路包括第n级扫描子电路，n为正整数，所述第n级扫描子电路中的所述寄存部耦接第i条信号线，所述第n级扫描子电路中的所述下拉部耦接第j条信号线；若n为2N的整数倍，i＝2N，否则，i＝mod(n,2N)；若(n+N-1)为2N的整数倍，j＝2N，否则，j＝mod(n+N-1,2N)。从而，有利于适用不同驱动扫描电路，在不影响面板像素充电的情况下实现驱动扫描电路的改进。
根据本发明的一实施例，所述偶数条信号线的数量为2N，N为正整数；所述多级扫描子电路包括第n级扫描子电路，n为正整数；若n≤N，则所述第n级扫描子电路中的所述寄存部输入一预设开启信号；若n>N，则所述第n级扫描子电路中的所述寄存部输出一开启信号到第(n+N)级扫描子电路中的所述寄存部。从而，有利于适用不同驱动扫描电路，在不影响面板像素充电的情况下实现驱动扫描电路的改进。
根据本发明的一实施例，所述寄存部包括的晶体管数量大于所述下拉部包括的晶体管数量。从而，所述下拉部包括的晶体管数量少于所述寄存部包括的晶体管数量，有效精简所述下拉部的电路架构，在不影响面板像素充电的情况下实现驱动扫描电路的改进。
根据本发明的一实施例，所述下拉部包括一下拉晶体 管，所述下拉晶体管的一控制端耦接一脉冲端口，所述下拉晶体管的一第一端耦接一扫描输入端口，所述下拉晶体管的一第二端耦接一低位端口，所述负载耦接于所述下拉部的所述扫描输入端口与所述寄存部的一扫描输出端口之间。从而，有效精简所述下拉部的电路架构，利用所述寄存部的所述扫描输出端口与所述下拉部的所述扫描输入端口共同驱动所述负载，在不影响面板像素充电的情况下实现驱动扫描电路的改进。
根据本发明的一实施例，所述偶数条信号线的数量为2N，N为正整数；所述偶数条信号线输送偶数个脉冲信号，在一输送配置中，依序相邻的两个脉冲信号中的在后一个所述脉冲信号比在前一个所述脉冲信号延迟一个时间单位，每个所述脉冲信号被配置成占空比为(N-1)/2N的脉冲宽度调制信号。从而，配合此种信号时序，下拉级联所连接的寄存部都是奇数级或者偶数级，因此相互级联的寄存部可以放在所述负载的同一侧，并在面板的同一侧提供一半数量的信号线配置，有利于实现窄边框面板。
为解决上述问题，本发明的一第二方面提供一种驱动扫描电路，包括：偶数条信号线，被配置分成奇数组信号线及偶数组信号线；及多级扫描子电路，每级扫描子电路包括一组件，所述组件耦接于所述奇数组信号线与所述偶数组信号线之间，所述组件包括一寄存部及一下拉部，所 述寄存部与所述下拉部之间耦接一负载；设于所述负载的同侧的所述寄存部和所述下拉部交替排列，在所述负载的一侧的任意两个相隔N级的所述寄存部相互级联，N为所述偶数条信号线的总数的一半。从而，通过分开且交替设置的寄存部及下拉部，将信号线有效分散到负载两侧，单侧信号线数量减半，可大幅缩减边框宽度，以便利用单驱的配置实现驱动扫描电路。
根据本发明的一实施例，在同一个所述组件中，所述寄存部及所述下拉部中的一者耦接于所述负载与所述奇数组信号线中的一信号线之间，所述寄存部及所述下拉部中的另一者耦接于所述负载与所述偶数组信号线中的一信号线之间。从而，将信号线有效分散到负载两侧，同一个所述组件中的所述寄存部及所述下拉部各自耦接位于不同侧的所述奇数组信号线及所述偶数组信号线，可大幅缩减边框宽度。
根据本发明的一实施例，在所述负载的一侧相邻的所述寄存部及所述下拉部耦接同一组信号线中的不同信号线。从而，可降低在所述负载的一侧相邻的所述寄存部及所述下拉部的接线占用面积，可大幅缩减边框宽度。
根据本发明的一实施例，所述偶数条信号线的数量为2N，N为正整数；所述多级扫描子电路包括第n级扫描子电路，n为正整数，所述第n级扫描子电路中的所述寄存 部耦接第i条信号线，所述第n级扫描子电路中的所述下拉部耦接第j条信号线；若n为2N的整数倍，i＝2N，否则，i＝mod(n,2N)；若(n+N-1)为2N的整数倍，j＝2N，否则，j＝mod(n+N-1,2N)。从而，有利于适用不同驱动扫描电路，在不影响面板像素充电的情况下实现驱动扫描电路的改进。
根据本发明的一实施例，所述偶数条信号线的数量为2N，N为正整数；所述多级扫描子电路包括第n级扫描子电路，n为正整数；若n≤N，则所述第n级扫描子电路中的所述寄存部输入一预设开启信号；若n>N，则所述第n级扫描子电路中的所述寄存部输出一开启信号到第(n+N)级扫描子电路中的所述寄存部。从而，有利于适用不同驱动扫描电路，在不影响面板像素充电的情况下实现驱动扫描电路的改进。
根据本发明的一实施例，所述寄存部包括的晶体管数量大于所述下拉部包括的晶体管数量。从而，所述下拉部包括的晶体管数量少于所述寄存部包括的晶体管数量，有效精简所述下拉部的电路架构，在不影响面板像素充电的情况下实现驱动扫描电路的改进。
根据本发明的一实施例，所述下拉部包括一下拉晶体管，所述下拉晶体管的一控制端耦接一脉冲端口，所述下拉晶体管的一第一端耦接一扫描输入端口，所述下拉晶体 管的一第二端耦接一低位端口，所述负载耦接于所述下拉部的所述扫描输入端口与所述寄存部的一扫描输出端口之间。从而，有效精简所述下拉部的电路架构，利用所述寄存部的所述扫描输出端口与所述下拉部的所述扫描输入端口共同驱动所述负载，在不影响面板像素充电的情况下实现驱动扫描电路的改进。
根据本发明的一实施例，所述偶数条信号线的数量为2N，N为正整数；所述偶数条信号线输送偶数个脉冲信号，在一输送配置中，依序相邻的两个脉冲信号中的在后一个所述脉冲信号比在前一个所述脉冲信号延迟一个时间单位，每个所述脉冲信号被配置成占空比为(N-1)/2N的脉冲宽度调制信号。从而，配合此种信号时序，下拉级联所连接的寄存部都是奇数级或者偶数级，因此相互级联的寄存部可以放在所述负载的同一侧，并在面板的同一侧提供一半数量的信号线配置，有利于实现窄边框面板。
根据本发明的一实施例，在所述负载同侧相邻的寄存部和下拉部集成配置。从而，可以把所述寄存部和下拉部在版图上混合绘制，这样可以大幅压缩边框宽度，经混合排版后，所述寄存部的宽度可缩小，加上单侧信号走线数量的减少，缩小后的寄存部宽度的节省量可以达到原本寄存部宽度的30％，可适用于液晶显示面板。
为解决上述问题，本发明的一第三方面提供一种显示 面板，包括如上所述的驱动扫描电路。
有益效果
本发明的驱动扫描电路及显示面板，每级扫描子电路包括所述组件，所述组件耦接于所述奇数组信号线与所述偶数组信号线之间，所述组件包括所述寄存部及所述下拉部，所述寄存部与所述下拉部之间耦接所述负载；设于所述负载的同侧的所述寄存部和所述下拉部交替排列，在所述负载的一侧的任意两个相隔N级的所述寄存部相互级联，N为所述偶数条信号线的总数的一半。从而，信号线有效分散到负载两侧，单侧信号线数量减半，单侧布线所需面积缩小，可大幅缩减边框宽度、降低功率消耗及降低延迟，利用单驱的配置实现驱动扫描电路，在不影响面板像素充电的情况下实现电路的改进。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例的驱动扫描电路的电路示意图。
图2为本发明实施例的寄存部的电路示意图。
图3为本发明实施例的下拉部的电路示意图。
图4为8CK架构的脉冲波形与级联关系的时序示意图。
图5为一示例性的移位寄存器的框图。
图6为单级移位寄存器的启动与重启(start-reset)的波形对应关系图。
图7为本发明实施例同侧的寄存部与下拉部混合排版的空间节省示意图。
本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本文的描述中，应被理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本文的描述中，应被理解的是，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有 “第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本文中提供许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开内容，下文中对特定示例的部件和设置进行描述。当然，它们仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同示例中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本文提供的各种特定的工艺和材料的示例，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
对于液晶或发光二极管(LED)显示面板来说，找出更好的窄边框解决方案一直是研发重点方向。举例说明如下，但不以此为限。
本发明的一第一方面提供一种驱动扫描电路，所述驱动扫描电路可适用于液晶显示面板，譬如窄边框的液晶显示面板，但不以此为限。
以下举例说明所述驱动扫描电路的实施方式，但不以此为限。
举例来说，如图1所示，所述驱动扫描电路包括：偶数条信号(CK)线及多级扫描子电路D，用于驱动一显示面 板中的多条横向的扫描线，所述扫描线可视为串接多个像素(譬如一显示面板中的横向排列的多个像素)，所述扫描线上带有电阻-电容性负载。譬如所述偶数条信号线的数量为2N，N为正整数，例如2N＝2或4或6(譬如4CK或6CK可用于小尺寸电竞屏)，或2N＝8(譬如8CK可用于中等尺寸电视等)，或2N＝12或16(譬如12CK或16CK可用于具备高分辨率的8K显示器)。
应被理解的是，如果CK线数过少，则面板内可能存在充电率不佳的情况，如果CK线数过多，则面板的边框会比较大(不适用于窄边框面板)。譬如针对8K显示器来说，采用12CK或16CK的充电率已足够，没有必要再增加更多的CK线数。以下仅以10行扫描线采用8CK为例进行说明，也可适用于其余CK线数及扫描线数，不另赘述。在本文中，为了方便说明及避免标号过于复杂，采用CKn(n为正整数)来表示不同信号线及其输送的信号，譬如，CK1可能在段落中用于表示信号线CK1或信号CK1。
举例来说，如图1所示，以8CK为例，即2N＝8，所述偶数条信号线(诸如CK1、CK2、CK3、CK4、CK5、CK6、CK7、CK8)可被配置分成奇数组信号线(诸如CK1、CK3、CK5、CK7)及偶数组信号线(诸如CK2、CK4、CK6、CK8)。
在此例中，以10行扫描线为例说明，即n＝1、2、3、…、10，所述多级扫描子电路D包括10级扫描子电路D，每 级扫描子电路D包括一组件(assembly)A，所述组件A耦接于所述奇数组信号线(诸如CK1、CK3、CK5、CK7)与所述偶数组信号线(诸如CK2、CK4、CK6、CK8)之间，所述组件A包括一寄存部1及一下拉部2，所述寄存部1譬如可被配置为一移位寄存器(shift register，又被标记为GOA)，所述下拉部2譬如可被配置为一下拉单元(pull-down unit，又被标记为PDU)，所述寄存部1与所述下拉部2之间耦接一负载B，譬如所述负载B可被配置为包括多个串接的像素，所述负载B上带有电阻-电容性负载。
为了便于说明，在此例中，第1级扫描子电路D的组件A包括一寄存部1(如GOA1)及一下拉部2(如PDU1)；第2级扫描子电路D的组件A包括一寄存部1(如GOA2)及一下拉部2(如PDU2)；第3级扫描子电路D的组件A包括一寄存部1(如GOA3)及一下拉部2(如PDU3)；第4级扫描子电路D的组件A包括一寄存部1(如GOA4)及一下拉部2(如PDU4)；第5级扫描子电路D的组件A包括一寄存部1(如GOA5)及一下拉部2(如PDU5)；第6级扫描子电路D的组件A包括一寄存部1(如GOA6)及一下拉部2(如PDU6)；第7级扫描子电路D的组件A包括一寄存部1(如GOA7)及一下拉部2(如PDU7)；第8级扫描子电路D的组件A包括一寄存部1(如GOA8)及一下拉部2(如PDU8)；第9级扫描子电路D的组件A包括一寄存部1(如GOA9)及一下拉部2(如 PDU9)；第10级扫描子电路D的组件A包括一寄存部1(如GOA10)及一下拉部2(如PDU10)。
应被注意的是，如图1所示，所述多级扫描子电路D中的所述寄存部1及所述下拉部2譬如可以配置成在所述负载B两侧逐级交替排列，譬如第1级扫描子电路D的寄存部1(如GOA1)在所述负载B一侧(如左侧)，第1级扫描子电路D的下拉部2(如PDU1)在所述负载B另一侧(如右侧)；第2级扫描子电路D的下拉部2(如PDU2)在所述负载B一侧(如左侧)，第2级扫描子电路D的寄存部1(如GOA2)在所述负载B另一侧(如右侧)；第3级扫描子电路D的寄存部1(如GOA3)在所述负载B一侧(如左侧)，第3级扫描子电路D的下拉部2(如PDU3)在所述负载B另一侧(如右侧)；依此类推，第10级扫描子电路D的下拉部2(如PDU10)在所述负载B一侧(如左侧)，第10级扫描子电路D的寄存部1(如GOA10)在所述负载B另一侧(如右侧)。
示例地，如图1所示，设于所述负载B的同侧的所述寄存部1和所述下拉部2交替排列，例如奇数级扫描子电路D的所述寄存部1(诸如GOA1、GOA3、GOA5、GOA7、GOA9)及偶数级扫描子电路D的所述下拉部2(诸如PDU2、PDU4、PDU6、PDU8、PDU10)在所述负载B一侧(如左侧)逐级交替排列，譬如从上到下被排列为GOA1、PDU2、GOA3、PDU4、GOA5、PDU6、GOA7、PDU8、GOA9、PDU10等； 奇数级扫描子电路D的所述下拉部2(诸如PDU1、PDU3、PDU5、PDU7、PDU9)及偶数级扫描子电路D的所述寄存部1(诸如GOA2、GOA4、GOA6、GOA8、GOA10)在所述负载B另一侧(如右侧)逐级交替排列，譬如从上到下被排列为PDU1、GOA2、PDU3、GOA4、PDU5、GOA6、PDU7、GOA8、PDU9、GOA10等。
示例地，如图1所示，在同一个所述组件A中，所述寄存部1及所述下拉部2中的一者耦接于所述负载B与所述奇数组信号线(譬如CK1、CK3、CK5、CK7)中的一信号线之间，所述寄存部1及所述下拉部2中的另一者耦接于所述负载B与所述偶数组信号线(诸如CK2、CK4、CK6、CK8)中的一信号线之间；在所述负载B的一侧相邻的所述寄存部1及所述下拉部2耦接同一组信号线(譬如奇数组信号线CK1、CK3、CK5、CK7或偶数组信号线CK2、CK4、CK6、CK8)中的不同信号线。
为了便于说明，在此例中，以8CK配合8级扫描子电路为例作为一模块M，在一驱动扫描电路中，可以有多个模块M。
举例来说，如图1所示，在单一模块M中，奇数级(诸如第1、3、5、7级)扫描子电路D的寄存部1(诸如GOA1、GOA3、GOA5、GOA7)分别耦接奇数组信号线(诸如CK1、CK3、CK5、CK7)；偶数级(诸如第2、4、6、8级)扫描子电 路D的寄存部1(诸如GOA2、GOA4、GOA6、GOA8)分别耦接偶数组信号线(诸如CK2、CK4、CK6、CK8)。另，对同一个驱动扫描电路的不同模块来说，所述信号线编号以1至8依序递增且循环使用，譬如CK1、CK2、CK3、CK4、CK5、CK6、CK7、CK8、CK1、CK2、CK3、…、CK7、CK8、CK1、CK2、CK3、…、CK7、CK8等，譬如在同一个所述组件A中，所述下拉部2的信号线与所述寄存部1的信号线可维持(N-1)的编号差距。
示例地，如图1所示，以2N＝8(N＝4)为例，所述下拉部2的信号线与所述寄存部1的信号线可维持(N-1＝3)的编号差值，譬如第1级扫描子电路D的寄存部1(如GOA1)耦接信号线CK1，第1级扫描子电路D的下拉部2(如PDU1)耦接信号线CK4；第2级扫描子电路D的寄存部1(如GOA2)耦接信号线CK2，第2级扫描子电路D的下拉部2(如PDU2)耦接信号线CK5；第3级扫描子电路D的寄存部1(如GOA3)耦接信号线CK3，第3级扫描子电路D的下拉部2(如PDU3)耦接信号线CK6；第4级扫描子电路D的寄存部1(如GOA4)耦接信号线CK4，第4级扫描子电路D的下拉部2(如PDU4)耦接信号线CK7；第5级扫描子电路D的寄存部1(如GOA5)耦接信号线CK5，第5级扫描子电路D的下拉部2(如PDU5)耦接信号线CK8；第6级扫描子电路D的寄存部1(如GOA6)耦接信号线CK6，第6级扫描子电路D的下拉部2(如PDU6) 耦接信号线CK1(6+3＝9，基于CK1至CK8，使用CK1)；第7级扫描子电路D的寄存部1(如GOA7)耦接信号线CK7，第7级扫描子电路D的下拉部2(如PDU7)耦接信号线CK2(7+3＝10，基于CK1至CK8，使用CK2)；第8级扫描子电路D的寄存部1(如GOA8)耦接信号线CK8，第8级扫描子电路D的下拉部2(如PDU8)耦接信号线CK3(8+3＝11，基于CK1至CK8，使用CK3)；第9级扫描子电路D的寄存部1(如GOA9)耦接信号线CK1，第9级扫描子电路D的下拉部2(如PDU8)耦接信号线CK4；…；第13级扫描子电路的寄存部(未绘出)耦接信号线CK5，第13级扫描子电路的下拉部(未绘出)耦接信号线CK8；…；第16级扫描子电路的寄存部(未绘出)耦接信号线CK8，第16级扫描子电路的下拉部(未绘出)耦接信号线CK3；其余连接方式，是依此说明可被理解的。
示例地，如图1所示，在一示例配置中，所述寄存部1及所述下拉部2耦接的信号线编号可譬如按一规则被配置，例如所述偶数条信号线的数量为2N，N为正整数；所述多级扫描子电路包括第n级扫描子电路，n为正整数，所述第n级扫描子电路中的所述寄存部耦接第i条信号线，所述第n级扫描子电路中的所述下拉部耦接第j条信号线；若n为2N的整数倍(诸如n＝2N、4N、6N、…；即mod(n,2N)＝0)，i＝2N，否则，i＝mod(n,2N)；若(n+N-1)为2N的整数倍(诸如 (n+N-1)＝2N、4N、6N、…；即mod((n+N-1),2N)＝0)，j＝2N，否则，j＝mod((n+N-1),2N)。
在本例中，如图1所示，为了方便说明，所述寄存部1可包括一第一脉冲(Sync)端口11、一开启输入(Start1)端口12、一重启(Reset)端口13及一扫描输出(Output1)端口14，但不以此为限，在其他配置中，所述寄存部1还可包括其他开启输入端口及/或扫描输出端口等；所述下拉部2可包括一第二脉冲端口21及一扫描输入端口22，但不以此为限，在其他配置中，所述下拉部2还可包括其他端口，譬如低位端口等；所述负载B耦接于所述扫描输出端口14与所述扫描输入端口22之间。
示例地，如图2所示，譬如所述寄存部1可以被配置为一GOA(gate driver on array)电路，包括多个晶体管及一电容器，所述晶体管包括一控制端、一第一端及一第二端，所述晶体管可譬如为具备栅极、源极和漏极的薄膜晶体管(TFT)；例如所述寄存部1包括一输入单元1A、一输出单元1B、一维持单元1C、一第一控制单元1D、一第二控制单元1E及一重置单元1F。
示例地，如图2所示，所述输入单元1A包括一第一晶体管T11，所述第一晶体管T11的控制端耦接所述开启输入端口12，用以输入一初始开启信号STV或一前级开启信号ST(n-N)，所述第一晶体管T11的第一端耦接一前 级扫描端口15，用以输入一前级扫描信号G(n-N)。
示例地，如图2所示，所述输出单元1B包括一第二晶体管T21、一第三晶体管T22及一电容器Cbt，所述第二晶体管T21的控制端及所述第三晶体管T22的控制端耦接所述第一晶体管T11的第二端而形成一第一接点Q，所述第二晶体管T21的第一端及所述第三晶体管T22的第一端耦接一脉冲端口，例如一第一脉冲端口11，用以输入一第一脉冲信号CK(i)，所述第二晶体管T21的第二端耦接所述扫描输出端口14，用以输出一第n级扫描信号G(n)，所述第三晶体管T22的第二端耦接一重启端口13，用以输出一第n级开启信号ST(n)，所述电容器Cbt耦接于所述第二晶体管T21的控制端与第二端之间。
示例地，如图2所示，所述维持单元1C包括一第四晶体管T31及一第五晶体管T41，所述第四晶体管T31的控制端及所述第五晶体管T41的控制端耦接一后级扫描端口16，用以输入一后级扫描信号G(n+N)，所述第四晶体管T31的第一端耦接所述扫描输出端口14，所述第四晶体管T31的第二端耦接一第一低位端口19，用以输入一第一低位信号VSSG，所述第五晶体管T41的第一端耦接所述第一接点Q，所述第五晶体管T41的第二端耦接一第二低位端口1a，用以输入一第二低位信号VSSQ。
示例地，如图2所示，所述第一控制单元1D包括一 第六晶体管T51、一第七晶体管T52、一第八晶体管T53、一第九晶体管T54、一第十晶体管T32及一第十一晶体管T42，所述第六晶体管T51的控制端与第一端及所述第八晶体管T53的第一端耦接一第一控制端口17，用以输入一第一控制信号LC1，所述第六晶体管T51的第二端耦接所述第七晶体管T52的第一端及所述第八晶体管T53的控制端，所述第七晶体管T52的控制端及所述第九晶体管T54的控制端耦接所述第一晶体管T11的第二端，所述第七晶体管T52的第二端、所述第九晶体管T54的第二端、所述第十晶体管T32的第二端及所述第十一晶体管T42的第二端耦接所述第二低位端口1a，所述第八晶体管T53的第二端耦接所述第九晶体管T54的第一端、所述第十晶体管T32的控制端及所述第十一晶体管T42的控制端，所述第十晶体管T32的第一端耦接所述扫描输出端口14，所述第十一晶体管T42的第一端耦接所述第一接点Q。
示例地，如图2所示，所述第二控制单元1E包括一第十二晶体管T61、一第十三晶体管T62、一第十四晶体管T63、一第十五晶体管T64、一第十六晶体管T33及一第十七晶体管T43，所述十二晶体管T61的控制端与第一端及所述第十四晶体管T63的第一端耦接一第二控制端口18，用以输入一第二控制信号LC2，所述第十二晶体管T61的第二端耦接所述第十三晶体管T62的第一端及所述 第十四晶体管T63的控制端，所述第十三晶体管T62的控制端及所述第十五晶体管T64的控制端耦接所述第一晶体管T11的第二端，所述第十三晶体管T62的第二端、所述第十五晶体管T64的第二端、所述第十六晶体管T33的第二端及所述第十七晶体管T43的第二端耦接所述第二低位端口1a，所述第十四晶体管T63的第二端耦接所述第十五晶体管T64的第一端、所述第十六晶体管T33的控制端及所述第十七晶体管T43的控制端，所述第十六晶体管T33的第一端耦接所述扫描输出端口14，所述第十七晶体管T43的第一端耦接所述第一接点Q。
示例地，如图2所示，所述重置单元1F包括一第十八晶体管T44，所述第十八晶体管T44的控制端耦接一重置(Re-setup)端口10，用以输入一重置信号RST，所述第十八晶体管T44的第一端耦接所述第一接点Q，所述第十八晶体管T44的第二端耦接所述第二低位端口1a。
在此例中，如图1及图2所示，以N＝4为例，所述第一脉冲端口11可用于输入所述第一脉冲信号CK(i)，譬如来自所述偶数条信号线(诸如CK1～CK8)中的一条信号线的脉冲信号；另，第1至4级扫描子电路D的寄存部1的所述开启输入端口12可输入所述初始开启信号STV，第n(n>4)级扫描子电路D的寄存部1的所述开启输入端口12可输入一第(n-4)级开启信号ST(n-4)，即为来自第(n-4)级 扫描子电路D的寄存部1的开启信号；所述重启端口13可输出第n级开启信号ST(n)；所述扫描输出端口14可输出第n级扫描信号G(n)，所述第n级扫描信号G(n)被输出到所述负载B，用以驱动第n级扫描子电路D的负载B，譬如第n行扫描线中的多个串接的像素。
示例地，如图1所示，在所述驱动扫描电路中，在所述负载B的一侧的任意两个相隔N级的所述寄存部1(譬如GOA1、GOA5、GOA9、…，但不以此为限)相互级联，譬如所述偶数条信号线的数量为2N，N为正整数(在此例中，N＝4)，所述多级扫描子电路D包括第n级扫描子电路D，n为正整数；若n≤N，则所述第n级扫描子电路D中的所述寄存部1输入所述预设开启信号STV；若n>N，则所述第n级扫描子电路D中的所述寄存部1输出所述开启信号ST(n)到第(n+N)级扫描子电路D中的所述寄存部1的所述开启输入端口12。
示例地，如图1及图3所示，所述下拉部2包括一下拉晶体管T，但不以此为限，所述下拉部2还可包括其他构件(如其他晶体管等)；所述下拉晶体管T的控制端耦接一脉冲端口，例如一第二脉冲端口21，用以输入一第二脉冲信号CK(j)，譬如来自所述偶数条信号线CK1～CK8中的一条信号线的脉冲信号，所述下拉晶体管T的第一端耦接一扫描输入端口22，用以输入经过第n级扫描子电路D 的负载B的第n级扫描信号G(n)，所述下拉晶体管T的第二端耦接一低位端口23，用以输入所述第一低位信号VSSG。在此例中，可通过所述第二脉冲信号CK(j)将经过第n级扫描子电路D的负载B的第n级扫描信号G(n)导引至所述低位端口23。
以下举例说明本发明实施例的驱动扫描电路的运作，如图1所示，所述驱动扫描电路属于一种单驱下拉GOA架构，以2N＝8为例，在所述负载B的一侧配置所述奇数组信号线CK1、CK3、CK5、CK7，在所述负载B的另一侧配置所述偶数组信号线CK2、CK4、CK6、CK8，使得单侧的信号线数量减半，有利适用于窄边框面板。另，在所述负载B的两侧横向逐行交替配置所述组件A的所述寄存部1及所述下拉部2，所述寄存部1可输出所述扫描信号，用于驱动扫描线，在此例中，所述下拉部2为单个薄膜晶体管，由作为一脉冲信号的一周期性方波信号控制，在脉冲信号为高电平时，导通漏极与源极，对扫描线的电位进行下拉。另，所述寄存部1及所述下拉部2在所述负载B的一侧纵向交替排列，对于一级栅极的方波信号而言，上升缘(rising edge)只有所述寄存部1驱动，下降缘(falling edge)由所述寄存部1及所述下拉部2共同驱动，对于有预充的栅极波形而言，下降缘的快慢是影响面内充电的关键因素。
如图4所示，以2N＝8为例，通过8CK架构的时序解释上述架构的工作原理，为了简化起见，以下采用G1、G2、G3、…至G27来表示第1、2、3、…至27级扫描子电路中的寄存部的栅极时序，同时，使用GOA1、GOA2、…表示图1中的不同扫描子电路中的寄存部1。对于所有的脉冲信号CK(如CK1至CK8)，其波形是周期性的方波信号，方波脉冲信号的高电平电压为CKH，低电平电压为CKL。对2N个CK系统而言，脉冲信号CK的占空比设置为(N-1)/2N。
在图4所示的时序图中，CK的高电平时间段被长条方框标注(例如G1、G2、G3、…、G5、…、G9、…、G26、G27、…，但不以此为限)，其上升延的时刻由上方的数字方格中的数字标尺表示。在扫描运转时，每一级的栅极信号将会同步一个CK的高电平方波，然后保持在低电平状态。例如对于信号线CK1驱动的G1而言，与G1同步的信号如图中G1波形所示。为了简化表示，每个栅极信号所同步的高电平脉冲被标注在CK的高电平方框内。在此架构中，开启(start)级联用同种方框标识。
譬如在图1及图4中，开启信号STV开启第1级到第n级的寄存部1(诸如GOA1至GOA(n))，如8CK系统，则前四级寄存部1(诸如GOA1至GOA4))由开启信号STV作为开启信号。其后，如方框所示，GOA1给GOA5提供开启 信号(如图4，G1与G5的框线同为细线)，GOA5给GOA9提供开启信号(如图4，G5与G9的框线同为细线),再往后顺次为GOA13、GOA17、GOA21、GOA25(如图4，G13、G17、G21与G25的框线同为细线)，其余具备相同框线的信号之间也是如此，不再赘述。然而，每一级栅极的下拉动作由所述寄存部1对侧的所述下拉部2发起，即提供下拉重启(reset)，其级联关系由图中的竖线标识。比如，GOA1对侧的PDU1由信号线CK4给GOA4提供的方波脉冲驱动，因此在时刻4，GOA1失去与信号CK1的同步。其他的下拉关系与此一致。
由图4可以看出，在一输送配置中，依序相邻的两个脉冲信号中的在后一个所述脉冲信号比在前一个所述脉冲信号延迟一个时间单位，譬如脉冲信号CK2的高电平时间段(如G2)比脉冲信号CK1的高电平时间段(如G1)延迟一时间单位，脉冲信号CK3的高电平时间段(如G3)比脉冲信号CK2的高电平时间段(如G2)延迟一时间单位，其余信号依此类推；每个所述脉冲信号被配置成占空比为(N-1)/2N的脉冲宽度调制信号。
应被注意的是，(N-1)/(2N)的占空比是实现此种单驱GOA-PDU的驱动功能的重要因素，因此靠此种时序配合，下拉级联所连接的GOA都是奇数级或者偶数级，因此级联的GOA可以放在所述负载(如面板的像素)的一侧，并在 面板的同一侧提供一半数量的CK信号线配置即可，有利于实现窄边框面板。而每一级的下拉PDU所需要的CK数会发生一个奇偶转变，比如奇数级的GOA的PDU所连CK是偶数CK，而偶数CK又在奇数CK的对侧。例如，如图1，在一侧(如左侧)的奇数CK提供奇数级GOA的驱动，同时提供偶数级PDU的驱动，而另一侧(如右侧)的偶数CK驱动偶数级GOA，并对奇数级的PDU提供下拉驱动。因此，每侧CK走线可相较于传统面板节省一半。对于2N＝12或2N＝16等其他CK数的架构，本发明的方法实施例仍然适用。
在一特定示例中，如图5所示，譬如一示例性的移位寄存器1’包括多个端口11’、12’、13’、14’、15’、16’、17’、18’、19’及1a’，端口11’用于输入信号CK(1)至CK(2N)，作为同步(Sync)信号；端口12’、15’用于输入信号ST(n-N)、信号G(n-N)，作为两开启(Start)信号；端口13’用于输出信号ST(n)；端口14’用于输出信号G(n)；端口15’用于输入信号G(n-N)；端口16’用于输入信号G(n+N)，作为重启(Reset)信号；端口17’、18’用于输入信号LC1、LC2；端口19’、1a’用于输入信号VSSG、VSSQ。
其中，信号LC1和LC2为高电平信号；信号VSSG和VSSQ为低电平直流信号，此二信号为移位寄存器的下拉维持电源信号线；信号LC1、LC2和信号VSSG、VSSQ也可 能被简化成信号LC和信号VSS；所述二开启信号为同步开启信号，在所述二开启信号同为高电平时，所述移位寄存器1’被激活，此时端口13’、14’开始同步端口11’连接的信号,假设一GOA电路为2N个CK线驱动，则信号G(n-N)和ST(n-N)为第n级移位寄存器1’的两个开启连接信号，信号G(n+N)或ST(n+N)为移位寄存器1’的重启信号。
对于第一级移位寄存器1’，在没有更前级的输出作为开启信号时，可用单独的开启(STV)线提供开启(start)信号到端口12’、15’。图6是以8CK驱动的GOA时序，其中ST(n-4)和G(n-4)为提前半个CK周期的方波脉冲信号，而G(N+4)为延后半个周期的方波脉冲信号，第n级移位寄存器同步CK信号是从ST(n-4)(如图所示STV(n-4))和G(n-4)的上升延时刻开始，失去同步时刻为是G(n+4)的上升延时刻，所述移位寄存器1’输出信号为ST(n)和G(n)，所述移位寄存器1’中的第一接点的信号为Q(n)。
应被注意的是，在一比较例中，譬如一双驱扫描电路的单个扫描子电路包括在一负载两侧的两个所述移位寄存器1’，所述负载两侧各有一个所述移位寄存器1’，例如所述移位寄存器1’包括上述第一晶体管至第十八晶体管的GOA电路，在比较例中，所述移位寄存器1’包括十八个晶体管及一电容器；对比地，上述实施例的单驱扫描电路的单个扫描子电路D包括所述负载B两侧的所述寄存部 1及所述下拉部2，所述负载B单侧只有所述寄存部1或所述下拉部2，所述下拉部2仅有一个晶体管。两者相较之下，在所述负载一侧的所述下拉部2与所述移位寄存器1’的元件(譬如晶体管)数量差异甚巨。对于同侧的下拉部来说，所述多个下拉部的级联关系与所述多个寄存部的级联关系一致，譬如某一下拉部2(如PDU1)的重启(reset)信号为下拉部2(如PDU5)的输出(output)信号，另一下拉部2(如PDU3)的重启信号为下拉部(如PDU7)的输出信号等；如果将同侧相邻的寄存部和下拉部集成配置，譬如通过在布局上进行混合绘制，如图7所示，左方示出同侧相邻的寄存部和下拉部非集成配置的GOA宽度W1，右方示出同侧相邻的寄存部和下拉部为集成配置的GOA宽度W2，由图可知，通过将同侧相邻的寄存部和下拉部集成配置，GOA宽度可由W1缩小为W2，加上单侧CK走线数量的减少，缩小后的GOA宽度节省量可以达到原本GOA宽度的30％。
如下所示，表1是采用一液晶面板进行上述比较例的移位寄存器1’及上述实施例的组件A的波形对比数据。其中，信号CK的高低电平为30V和-10V，通过测量9点(左中右-上中下)的栅极(Gate)方波的上升缘(简称为上升，rising)和下降缘(简称为下降，falling)时间。可以发现右下(right-down)的上升和下降时间最大，是最大负载点。相 比于图7中的GOA宽度W1(同侧相邻的下拉部和寄存部非集成配置)，图7中的GOA宽度W2(同侧相邻的下拉部和寄存部为集成配置)的上升时间较大，约为两倍，但是下降时间(此为影响面内像素充电的重要指标)差别不大。因此通过优化所述组件中的寄存部与下拉部的薄膜晶体管大小，可以实现原有的下降时间。
表1 不同架构的负载波形比对
Figure PCTCN2022074186-appb-000001
以下例示所述驱动扫描电路的一些实施例，但不以此为限。
本发明的一方面提供一种驱动扫描电路，包括：偶数条信号线，被配置分成奇数组信号线及偶数组信号线；及多级扫描子电路，每级扫描子电路包括一组件，所述组件耦接于所述奇数组信号线与所述偶数组信号线之间，所述组件包括一寄存部及一下拉部，所述寄存部与所述下拉部之间耦接一负载；设于所述负载的同侧的所述寄存部和所述下拉部交替排列，在所述负载的一侧的任意两个相隔N级的所述寄存部相互级联，N为所述偶数条信号线的总数的一半。从而，通过分开且交替设置的寄存部及下拉部， 将信号线有效分散到负载两侧，单侧信号线数量减半，可大幅缩减边框宽度，以便利用单驱的配置实现驱动扫描电路。
可选地，在一实施例中，在同一个所述组件中，所述寄存部及所述下拉部中的一者耦接于所述负载与所述奇数组信号线中的一信号线之间，所述寄存部及所述下拉部中的另一者耦接于所述负载与所述偶数组信号线中的一信号线之间。从而，将信号线有效分散到负载两侧，同一个所述组件中的所述寄存部及所述下拉部各自耦接位于不同侧的所述奇数组信号线及所述偶数组信号线，可大幅缩减边框宽度。
可选地，在一实施例中，在所述负载的一侧相邻的所述寄存部及所述下拉部耦接同一组信号线中的不同信号线。从而，可降低在所述负载的一侧相邻的所述寄存部及所述下拉部的接线占用面积，可大幅缩减边框宽度。
可选地，在一实施例中，所述偶数条信号线的数量为2N，N为正整数；所述多级扫描子电路包括第n级扫描子电路，n为正整数，所述第n级扫描子电路中的所述寄存部耦接第i条信号线，所述第n级扫描子电路中的所述下拉部耦接第j条信号线；若n为2N的整数倍，i＝2N，否则，i＝mod(n,2N)；若(n+N-1)为2N的整数倍，j＝2N，否则，j＝mod(n+N-1,2N)。从而，有利于适用不同驱动扫描电路， 在不影响面板像素充电的情况下实现驱动扫描电路的改进。
可选地，在一实施例中，所述偶数条信号线的数量为2N，N为正整数；所述多级扫描子电路包括第n级扫描子电路，n为正整数；若n≤N，则所述第n级扫描子电路中的所述寄存部输入一预设开启信号；若n>N，则所述第n级扫描子电路中的所述寄存部输出一开启信号到第(n+N)级扫描子电路中的所述寄存部。从而，有利于适用不同驱动扫描电路，在不影响面板像素充电的情况下实现驱动扫描电路的改进。
可选地，在一实施例中，所述寄存部包括的晶体管数量大于所述下拉部包括的晶体管数量。从而，所述下拉部包括的晶体管少于所述寄存部包括的晶体管数量，有效精简所述下拉部的电路架构，在不影响面板像素充电的情况下实现驱动扫描电路的改进。
可选地，在一实施例中，所述下拉部包括一下拉晶体管，所述下拉晶体管的一控制端耦接一脉冲端口，所述下拉晶体管的一第一端耦接一扫描输入端口，所述下拉晶体管的一第二端耦接一低位端口，所述负载耦接于所述下拉部的所述扫描输入端口与所述寄存部的一扫描输出端口之间。从而，有效精简所述下拉部的电路架构，利用所述寄存部的所述扫描输出端口与所述下拉部的所述扫描输 入端口共同驱动所述负载，在不影响面板像素充电的情况下实现驱动扫描电路的改进。
可选地，在一实施例中，所述偶数条信号线的数量为2N，N为正整数；所述偶数条信号线输送偶数个脉冲信号，在一输送配置中，依序相邻的两个脉冲信号中的在后一个所述脉冲信号比在前一个所述脉冲信号延迟一个时间单位，每个所述脉冲信号被配置成占空比为(N-1)/2N的脉冲宽度调制信号。从而，配合此种信号时序，下拉级联所连接的寄存部都是奇数级或者偶数级，因此相互级联的寄存部可以放在所述负载的同一侧，并在面板的同一侧提供一半数量的信号线配置，有利于实现窄边框面板。
可选地，在一实施例中，在所述负载同侧相邻的寄存部和下拉部集成配置。从而，可以把所述寄存部和下拉部在版图上混合绘制，这样可以大幅压缩边框宽度，经混合排版后，所述寄存部的宽度可缩小，加上单侧信号走线数量的减少，缩小后的寄存部宽度的节省量可以达到原本寄存部宽度的30％，可适用于液晶显示面板。
此外，本发明的另一方面提供一种显示面板，譬如液晶显示面板，所述显示面板包括如上所述的驱动扫描电路，其实施内容及有益效果说明如上，不再赘述。
本发明上述实施例的驱动扫描电路及显示面板，每级扫描子电路包括所述组件，所述组件耦接于所述奇数组信 号线与所述偶数组信号线之间，所述组件包括所述寄存部及所述下拉部，所述寄存部与所述下拉部之间耦接所述负载；设于所述负载的同侧的所述寄存部和所述下拉部交替排列，在所述负载的一侧的任意两个相隔N级的所述寄存部相互级联，N为所述偶数条信号线的总数的一半。从而，信号线有效分散到负载两侧，单侧信号线数量减半，单侧布线所需面积缩小，可大幅缩减边框宽度、降低功率消耗及降低延迟，利用单驱的配置实现驱动扫描电路，在不影响面板像素充电的情况下实现电路的改进。
以上对本发明实施例进行详细介绍，本文中应用具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例的技术方案的范围。

Claims (17)

  1. 一种驱动扫描电路，其包括：
    偶数条信号线，分为奇数组信号线及偶数组信号线；及
    多级扫描子电路，每级扫描子电路包括一组件，所述组件耦接于所述奇数组信号线与所述偶数组信号线之间，所述组件包括一寄存部及一下拉部，所述寄存部与所述下拉部之间耦接一负载；
    设于所述负载的同侧的所述寄存部和所述下拉部交替排列，在所述负载的一侧的任意两个相隔N级的所述寄存部相互级联，N为所述偶数条信号线的总数的一半；
    其中在所述负载的一侧相邻的所述寄存部及所述下拉部耦接同一组信号线中的不同信号线；及在所述负载同侧相邻的寄存部和下拉部集成配置。
  2. 根据权利要求1所述的驱动扫描电路，其中在同一个所述组件中，所述寄存部及所述下拉部中的一者耦接于所述负载与所述奇数组信号线中的一信号线之间，所述寄存部及所述下拉部中的另一者耦接于所述负载与所述偶数组信号线中的一信号线之间。
  3. 根据权利要求1所述的驱动扫描电路，其中所述偶数条信号线的数量为2N，N为正整数；所述多级扫描子电路包括第n级扫描子电路，n为正整数，所述第n级 扫描子电路中的所述寄存部耦接第i条信号线，所述第n级扫描子电路中的所述下拉部耦接第j条信号线；若n为2N的整数倍，i＝2N，否则，i＝mod(n,2N)；若(n+N-1)为2N的整数倍，j＝2N，否则，j＝mod(n+N-1,2N)。
  4. 根据权利要求1所述的驱动扫描电路，其中所述偶数条信号线的数量为2N，N为正整数；所述多级扫描子电路包括第n级扫描子电路，n为正整数；若n≤N，则所述第n级扫描子电路中的所述寄存部输入一预设开启信号；若n>N，则所述第n级扫描子电路中的所述寄存部输出一开启信号到第(n+N)级扫描子电路中的所述寄存部。
  5. 根据权利要求1所述的驱动扫描电路，其中所述寄存部包括的晶体管数量大于所述下拉部包括的晶体管数量。
  6. 根据权利要求1所述的驱动扫描电路，其中所述下拉部包括一下拉晶体管，所述下拉晶体管的一控制端耦接一脉冲端口，所述下拉晶体管的一第一端耦接一扫描输入端口，所述下拉晶体管的一第二端耦接一低位端口，所述负载耦接于所述下拉部的所述扫描输入端口与所述寄存部的一扫描输出端口之间。
  7. 根据权利要求1所述的驱动扫描电路，其中所述偶数条信号线的数量为2N，N为正整数；所述偶数条信号线输送偶数个脉冲信号，在一输送配置中，依序相邻的 两个脉冲信号中的在后一个所述脉冲信号比在前一个所述脉冲信号延迟一个时间单位，每个所述脉冲信号被配置成占空比为(N-1)/2N的脉冲宽度调制信号。
  8. 一种驱动扫描电路，其包括：
    偶数条信号线，分为奇数组信号线及偶数组信号线；及
    多级扫描子电路，每级扫描子电路包括一组件，所述组件耦接于所述奇数组信号线与所述偶数组信号线之间，所述组件包括一寄存部及一下拉部，所述寄存部与所述下拉部之间耦接一负载；
    设于所述负载的同侧的所述寄存部和所述下拉部交替排列，在所述负载的一侧的任意两个相隔N级的所述寄存部相互级联，N为所述偶数条信号线的总数的一半。
  9. 根据权利要求8所述的驱动扫描电路，其中在同一个所述组件中，所述寄存部及所述下拉部中的一者耦接于所述负载与所述奇数组信号线中的一信号线之间，所述寄存部及所述下拉部中的另一者耦接于所述负载与所述偶数组信号线中的一信号线之间。
  10. 根据权利要求8所述的驱动扫描电路，其中在所述负载的一侧相邻的所述寄存部及所述下拉部耦接同一组信号线中的不同信号线。
  11. 根据权利要求8所述的驱动扫描电路，其中所述 偶数条信号线的数量为2N，N为正整数；所述多级扫描子电路包括第n级扫描子电路，n为正整数，所述第n级扫描子电路中的所述寄存部耦接第i条信号线，所述第n级扫描子电路中的所述下拉部耦接第j条信号线；若n为2N的整数倍，i＝2N，否则，i＝mod(n,2N)；若(n+N-1)为2N的整数倍，j＝2N，否则，j＝mod(n+N-1,2N)。
  12. 根据权利要求8所述的驱动扫描电路，其中所述偶数条信号线的数量为2N，N为正整数；所述多级扫描子电路包括第n级扫描子电路，n为正整数；若n≤N，则所述第n级扫描子电路中的所述寄存部输入一预设开启信号；若n>N，则所述第n级扫描子电路中的所述寄存部输出一开启信号到第(n+N)级扫描子电路中的所述寄存部。
  13. 根据权利要求8所述的驱动扫描电路，其中所述寄存部包括的晶体管数量大于所述下拉部包括的晶体管数量。
  14. 根据权利要求8所述的驱动扫描电路，其中所述下拉部包括一下拉晶体管，所述下拉晶体管的一控制端耦接一脉冲端口，所述下拉晶体管的一第一端耦接一扫描输入端口，所述下拉晶体管的一第二端耦接一低位端口，所述负载耦接于所述下拉部的所述扫描输入端口与所述寄存部的一扫描输出端口之间。
  15. 根据权利要求8所述的驱动扫描电路，其中所述偶数条信号线的数量为2N，N为正整数；所述偶数条信号线输送偶数个脉冲信号，在一输送配置中，依序相邻的两个脉冲信号中的在后一个所述脉冲信号比在前一个所述脉冲信号延迟一个时间单位，每个所述脉冲信号被配置成占空比为(N-1)/2N的脉冲宽度调制信号。
  16. 根据权利要求8所述的驱动扫描电路，其中在所述负载同侧相邻的寄存部和下拉部集成配置。
  17. 一种显示面板，其包括根据权利要求8所述的驱动扫描电路。
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