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WO2022151721A1 - 纠错系统 - Google Patents

纠错系统 Download PDF

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Publication number
WO2022151721A1
WO2022151721A1 PCT/CN2021/111414 CN2021111414W WO2022151721A1 WO 2022151721 A1 WO2022151721 A1 WO 2022151721A1 CN 2021111414 W CN2021111414 W CN 2021111414W WO 2022151721 A1 WO2022151721 A1 WO 2022151721A1
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WO
WIPO (PCT)
Prior art keywords
signal
codes
code
data
unit
Prior art date
Application number
PCT/CN2021/111414
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English (en)
French (fr)
Inventor
冀康灵
何军
龚园媛
应战
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/582,185 priority Critical patent/US11599417B2/en
Publication of WO2022151721A1 publication Critical patent/WO2022151721A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Definitions

  • the embodiments of the present application relate to, but are not limited to, an error correction system.
  • DRAM Dynamic Random Access Memory
  • ECC Error Correction Code
  • An embodiment of the present application provides an error correction system, which is applied to a storage system.
  • the storage system writes or reads a plurality of data during a read and write operation.
  • the plurality of data is divided into M bytes, and each data is divided into M bytes.
  • the byte has data of N different bits;
  • the storage system has an encoding stage and a decoding stage, and in the decoding stage, the error correction system generates X first operational codes based on the storage system and, Y second operation codes and third operation codes, the X first operation codes, the Y second operation codes and the third operation codes are used to judge the error state of the plurality of data, and when the When multiple pieces of data have a 1-bit error, the Y second operational codes are used to locate the specific byte to which the 1-bit error belongs, and the X first operational codes are used to locate the specific bit to which the 1-bit error belongs.
  • the first operation code is used to detect and/or correct N data
  • the second operation code is used to detect and/or correct M bytes
  • the error correction system Including: an error state judgment unit, used for decoding the X first operation codes, the Y second operation codes and the third operation code to identify the current error state; M decoding unit, each of the decoding units corresponds to one of the bytes, and is used for decoding the X first operation codes and the Y second operation codes to obtain whether the bytes Having erroneous data and locating the bits of the erroneous data.
  • FIG. 1 is a functional block diagram of an error correction system and a storage system provided by an embodiment of the present application;
  • FIG. 2 is a schematic structural diagram of an error correction system provided by an embodiment of the present application.
  • Fig. 3 is the enlarged structural representation of the decoding unit corresponding to each byte in Fig. 2;
  • FIG. 4 is a schematic diagram of classification of a plurality of data and a schematic diagram of a relationship with a first check code, a second check code, and a third check code provided by an embodiment of the present application;
  • Fig. 5 illustrates the enlarged schematic diagram of the first check code corresponding to byte 0;
  • FIG. 6 is a schematic structural diagram of an error correction system provided by an embodiment of the present application.
  • FIG. 7 shows a schematic diagram of the principle of performing the second encoding operation on all bytes
  • FIG. 8 is a functional block diagram of a first comparison circuit or a second comparison circuit in an error correction system provided by an embodiment of the present application;
  • FIG. 9 is a schematic diagram of a circuit structure of a first comparison circuit or a second comparison circuit in an error correction system provided by an embodiment of the present application.
  • FIG. 10 is another schematic structural diagram of a decoding unit corresponding to a byte provided by an embodiment of the application.
  • FIG. 11 is an enlarged schematic structural diagram of a decoding unit corresponding to byte 5 in FIG. 10 .
  • the embodiment of the present application provides an error correction system, which is applied to a storage system, and the storage system writes or reads a plurality of data during a read and write operation, and the plurality of data is divided into M bytes and each byte has N different bits of data, and in the decoding stage, the storage system generates X first operation codes, Y second operation codes and third operation codes.
  • the first operation code, the second operation code and the third operation code are used for judgment Error states of multiple data, and the first operation code is used for error detection and/or error correction on N pieces of data, and the second operation code is used for error detection and/or error correction on M bytes; error correction system It includes an error state judging unit for identifying the current error state and a decoding unit for locating the specific byte and specific bit to which the erroneous data belongs.
  • FIG. 1 is a functional block diagram of an error correction system and a storage system provided by an embodiment of the application
  • FIG. 2 is a schematic structural diagram of an error correction system provided by an embodiment of the application
  • FIG. 3 is a diagram corresponding to each byte in FIG. 2 A schematic diagram of the enlarged structure of the decoding unit.
  • the error correction system 1 is applied to a storage system 101 , and the storage system 101 writes or reads a plurality of data during a read and write operation, and the plurality of data is divided into M bytes , and each byte has data of N different bits;
  • the storage system 101 has an encoding stage and a decoding stage, and in the decoding stage, the error correction system 1 generates X first operation codes based on the storage system 101, and Y is The second operation code and the third operation code, X first operation code, Y second operation code and third operation code are used to judge the error state of multiple data, and when multiple data have 1-bit error, Y
  • the second operation code is used to locate the specific byte to which the 1-bit error belongs, and the X first operation codes are used to locate the specific bit to which the 1-bit error belongs;
  • the error correction system 1 includes: an error state judgment unit 30 for Decoding is performed on the X first operational codes, the Y second operational codes and the third operational codes to identify
  • the current error state includes: 0-bit error, 1-bit error, and 2-bit error.
  • the first operation code is used for error detection and/or error correction for N pieces of data in each byte
  • the second operation code is used for error detection and/or error correction for M bytes.
  • the first operation code in this embodiment is used to perform error detection and/or error correction on N data in each byte
  • the second operation code is used to detect M bytes.
  • the error state judging unit 30 is used for judging the number of bits of data error according to the first operation code, the second operation code and the third operation code, and the error state includes 0-bit error, 1-bit error and 2-bit error.
  • the judgment principle is as follows:
  • the decoding unit 31 performs error detection/correction. The principle of detecting the location of the erroneous data by the decoding unit 31 will be described in detail later, and will not be repeated here.
  • the third operation code is 0, and the first operation code and the second operation code are not all 0, it means that the number of digits in error is 2, and correction cannot be performed at this time.
  • Those skilled in the art can design the error information as needed sent to the control device.
  • the error state judging unit 30 is connected with M decoding units 31. If there is a 1-bit error (that is, the third operation code is 1, and the first operation code and the second operation code are not all 0), M can be used.
  • the decoding unit 31 locates the erroneous data.
  • FIG. 2 shows a schematic structural diagram of a decoding unit corresponding to two bytes.
  • the error correction system provided by this embodiment will be described in detail below with reference to the accompanying drawings.
  • the decoding unit 31 includes: a decoder 301 for receiving X first operational codes and outputting N first decoding signals, each of which is one of the N pieces of data. Corresponding bits, N is greater than X; the first AND gate unit 302 is used to receive Z selected operation codes and perform a logical AND operation, and the selected operation codes are the second operation code corresponding to the byte in the Y second operation codes.
  • NOR gate unit 303 for receiving (Y-Z) unselected operation code, and performing logical OR operation, the unselected operation code is the second operation code outside the selected operation code; N second AND gate units 304 , the input terminal of each second AND gate unit 304 is connected to the output terminal of the first AND gate unit 302, the output terminal of the NOR gate unit 303 and a first decoding signal, based on the output pair of the N second AND gate units 304
  • the storage system 101 performs error detection and/or error correction; wherein X, Y, and N are all positive natural numbers, and Z is an integer greater than or equal to (Y-1)/2 and less than or equal to (Y+1)/2.
  • X is 3 and N is 8
  • the corresponding decoder 301 is a three-eight decoder
  • the decoder 301 has 3 input terminals and 8 output terminals
  • the second AND gate unit 304 has The number is 8, that is, N is 8.
  • Z is an integer greater than or equal to (Y-1)/2 and less than or equal to (Y+1)/2, the sum of the number of input terminals of the first AND gate unit 302 and the number of input terminals of the NOR gate unit 303 is minimized, In addition, the input terminal of the first AND gate unit 302 and the input terminal of the NOR gate unit 303 can be effectively utilized.
  • Y is 5, then 2 ⁇ Z ⁇ 3, if the first AND gate unit gate 302 receives two selected operation codes, that is, the first AND gate unit 302 needs two input terminals, then the NOR gate unit 303 Receive 3 unselected operation codes, that is, the NOR gate unit 303 needs 3 input terminals; if the first AND gate unit 302 receives 3 selected operation codes, that is, the first AND gate unit 302 needs 3 input terminals, then the NOR gate unit 302 needs 3 input terminals. The gate unit 303 receives 2 unselected opcodes, that is, the NOR gate unit 303 needs 2 inputs.
  • the first AND gate unit 302 has three input terminals; the first AND gate unit 302 is further configured to connect an input terminal of the first AND gate unit 302 if the number of selected operation codes is 2 Power supply VDD.
  • the NOR gate unit 303 has three input terminals; the NOR gate unit 303 is also configured to, if the number of unselected operation codes is 2, one input terminal of the NOR gate unit 303 is grounded to Vss.
  • the first operational code is used to perform error detection and/or error correction on N pieces of data, if the storage system has 1-bit erroneous data, the N pieces of first decoded signals output by the decoder 301 can be obtained. It is the data of which bit in the N different bit data is wrong, but it is impossible to know which bit of the data in the byte is wrong through the N first decoding signals.
  • the selected operation code is the second operation code corresponding to the byte among the Y second operation codes, and the term "correspondence" here means that the data of the byte has participated in the encoding operation of the second operation code.
  • each second operation code is obtained by encoding all data in different bytes. It can be understood that for a byte, if the byte in the The second operation code obtained by participating in the encoding operation of all the data of , is defined as the second operation code corresponding to this byte. It is not difficult to find that since the second operational codes obtained by different bytes participating in the encoding operation are not identical, the Y second operational codes can be used to perform error detection and/or error correction on M bytes.
  • the second operation code is used to perform error detection and/or error correction on M bytes, for the first AND gate unit 302, the second operation code corresponding to the byte is the selected operation code as the first AND gate Input to unit 302 . If the storage system has 1-bit erroneous data and the data in the byte is erroneous, the selected operation code will be affected, so that the output result of the first AND gate unit 302 will be affected.
  • the second operation code other than the selected operation code among all the second operation codes is the unselected operation code, and the unselected operation code is used as the input of the NOR gate unit 303 .
  • the unselected operation code will not be affected, and the output result of the NOR gate unit 303 will not be affected; similarly, if the storage system has a 1-bit error If there is no error in the data in the byte, the unselected operation code will be affected, and the output result of the NOR gate unit 303 will be affected.
  • Each second AND gate unit 304 is connected to a first decoded signal and the output terminal of the first AND gate unit 302 and the output terminal of the NOR gate unit 303, so that the output terminal of each second AND gate unit 304 is subjected to the The influence of the data of each bit in the byte, that is, through the output end of the second AND gate unit 304, it can be known whether the data of each corresponding bit of the byte is in error.
  • the byte has 1 bit of erroneous data, and the erroneous data is located in the 1st bit, define the first decoding signal corresponding to the 1st bit as the flag decoding signal, then receive the flag
  • the output result of the second AND gate unit 304 of the decoded signal does not meet expectations and is different from the output results of other second AND gate units 304, so that the data of the first bit is deduced inversely as erroneous data. If the data in this byte are all correct data, the output results of all the second AND gate units 304 are the same and meet expectations, so that it is reversely derived that the erroneous data is not in this byte.
  • the storage system 101 includes a storage chip, and the error state determination unit 30 and the M decoding units 31 can be integrated in the storage chip.
  • the circuit of the decoding unit 31 corresponding to each byte can be set to the same circuit, except that the first operation code and the second operation code connected to the input terminals of the different decoding units 31 Different, it is beneficial to save the line and area of all decoding units in the error correction system, and all bytes can be decoded at the same time for error detection and/or error correction, so the error detection and correction of the error correction system can be improved. wrong speed.
  • the storage system 101 may be DRAM, such as DDR4, LPDDR4, DDR5 or LPDDR5; the storage system 101 may be other types of storage systems, such as NAND, NOR, FeRAM, PcRAM and other non-volatile memories.
  • N is 8, so as to maximize the bits in each byte, thus helping to improve the utilization rate of the circuits required by the comparison system 20 . It can be understood that, in other embodiments, N can also be other suitable positive integers.
  • M 16 and N is 8. It should be noted that, in other embodiments, according to the difference in the number of bits of data transmitted by the storage system during the read and write operations, M can also be other suitable positive integers to satisfy M*N and the bits of the data transmitted during the read and write operations. The numbers are equal.
  • FIG. 4 is a schematic diagram of the classification of multiple data and a schematic diagram of the relationship with the first check code, the second check code, and the third check code provided in this embodiment, and the bits of each data in the N pieces of data are different .
  • N pieces of data have bits from 0th to 7th incremented by natural numbers; for all bytes, M bytes are divided into 0th increments of natural numbers from 0th 16 bytes to the 15th.
  • the N pieces of data in the byte all have 8 bits incremented from the 0th to the 7th.
  • FIG. 5 shows an enlarged schematic diagram of the first check code corresponding to byte 0.
  • FIG. 6 is a schematic structural diagram of an error correction system provided by an embodiment of the present application.
  • the error correction system 1 further includes: a first encoding module 102 configured to generate X first encoding stages based on a number of data in each byte, both during the read operation and during the encoding phase during the write operation Check code, the bits of several data corresponding to the same first check code in different bytes are the same, and Y second check codes are generated based on all the data in several bytes, among which X first check codes are The verification code is used to perform error detection and/or error correction on N data in each byte, Y second verification codes are used to perform error detection and/or error correction on M bytes, X and Y are both is a positive natural number.
  • the first check code is used to perform error detection and/or error correction on N data in each byte
  • the second check code is used to perform error detection and/or error correction on M bytes.
  • the error correction coding method can not only realize ECC, but also can realize ECC with less hardware circuit, which is beneficial to reduce the power consumption of the storage system and optimize the speed and result of ECC.
  • the first check code in this embodiment is used to perform error detection and/or error correction on N pieces of data in each byte, and the second check code is used for M bytes of data.
  • the first check codes and the second check codes are jointly used to perform error detection and/or error correction on all data of M bytes, and the second check code is used for error detection and/or error correction.
  • the code will be used to locate which byte of the M bytes where the data in error is located, and the first check code will be used to locate which bit of the byte where the data where the error is located is located.
  • the first encoding module 102 uses the parity check principle to generate the first check code and the second check code.
  • the first check code and the second check code are both parity check codes. code verification.
  • the first encoding module 102 includes: a first encoding unit 112 configured to, during the writing operation, obtain X first check codes and Y second check codes based on a plurality of written data;
  • the second encoding unit 122 is configured to, during the read operation, obtain X first update check codes and Y second update check codes based on a plurality of data to be read, and the first update check code is
  • the acquisition method is the same as the acquisition method of the first check code
  • the acquisition method of the second update check code is the same as the acquisition method of the second check code; wherein, the first operation code is based on the first check code and the first update check code.
  • the verification code is acquired, and the second operation code is acquired based on the second verification code and the second updated verification code.
  • X first check codes form X-bit first binary numbers; wherein, 2 X ⁇ N, and each first check code is obtained by performing a first encoding operation on a number of data in all bytes, and each Several data corresponding to the first check code correspond to different bit combinations in the byte. That is to say, each first check code selects data of multiple bits in each byte to perform the first encoding operation, and for the same first check code, the selected bits in all bytes are obtained. The combinations are the same, and for different first check codes, the selected bit combinations in the N pieces of data are different.
  • the N pieces of data have bits incremented from 0th to N-1th according to natural numbers, and the first check codes obtained by each bit being selected to perform the first encoding operation are not identical. Specifically, different first check codes are obtained by performing a first encoding operation based on different data in all bytes, so that for different first check codes, the bits that affect the result of the first check code are different . At the same time, since 2 X ⁇ N, the first check codes obtained by each bit selected for the first encoding operation are not identical, so that through analysis, it is possible to obtain the data corresponding to which bit has an error.
  • X is 3, which not only satisfies that errors of data of different bits can be indicated, but also reduces the complexity of the hardware circuit of the first encoding unit 112 .
  • the three first check codes include the 0th first check code, the first first check code and the second first check code according to the order of bits from low to high.
  • the N pieces of data have bits that increase from 0th to N-1th according to natural numbers.
  • the 0th bit it does not participate in the first encoding operation corresponding to any first check code; for the 1st bit bit, it participates in the first encoding operation corresponding to the first check code of the 0th bit; for the second bit, it participates in the first encoding operation corresponding to the first check code of the first bit; for the third bit, It participates in the first encoding operation corresponding to the first check code of the 0th bit and the first bit; for the 4th bit, it participates in the first encoding operation corresponding to the first check code of the second bit; for the 5th bit bit, it participates in the first encoding operation corresponding to the 0th and the second first check code; for the 6th bit, it participates in the first encoding operation corresponding to the 1st and the second first check code ; For the 7th bit, it participates in the first encoding operation corresponding to the 0th, 1st and 2nd bit first check codes.
  • the first encoding operation is XOR; correspondingly, the first encoding unit 112 is configured so that, in the X-bit first binary number, the first check code in the lowest bit is in all bytes
  • the exclusive OR of the data of the 1st, 3rd, 5th and 7th bits, the first check code in the highest bit is the exclusive OR of the data of the 4th, 5th, 6th and 7th bits in all bytes
  • the first check code in the middle bit is the exclusive OR of the data of the 2nd, 3rd, 6th and 7th bits in all bytes.
  • the first encoding operation may also be an XOR; correspondingly, the first encoding unit is configured such that, in the X-bit binary number, the first check code in the lowest bit is all The exclusive OR of the data of the 1st, 3rd, 5th and 7th bits in the byte, the first check code in the highest bit is the 4th, 5th, 6th and 7th bits of all bytes.
  • the first check code in the middle bit is the exclusive OR of the data of the 2nd, 3rd, 6th and 7th bits in all bytes.
  • the generation principle of the first check code will be described below with reference to FIG. 4 and FIG. 5 .
  • "x" indicates that the encoding operation of this line is currently involved, that is, XOR or XOR; and the 128-bit data is divided into 16 bytes from the 0th to the 15th, and each byte is divided into 16 bytes.
  • p10, p11 and p12 represent three first check codes;
  • p13, p14, p15, p16 and p17 represent 5 second check codes;
  • pc0 to pc7 represent the 8 corresponding to p10 to p17 when performing encoding operations an arithmetic formula.
  • all the positions marked with "X" indicate that the data corresponding to this column needs to participate in XOR or XOR in this expression.
  • the first check code and the second check code correspond to pb.
  • the first encoding operation or the second encoding operation is performed by using the eight operational expressions pc0 to pc7, and the results of the operations are stored in p10 to p17 respectively , and p10 to p17 do not participate in the first encoding operation or the second encoding operation; in the decoding stage, the corresponding expressions of each row remain unchanged, and the stored p10 to p17 need to participate in the operation, so p10 to p17 in the table in Figure 4
  • the corresponding marks are marked with "X", which will be explained in detail later.
  • XOR or XOR for each byte, XOR or XOR the data in the 1st, 3rd, 5th, and 7th bits of this byte, and then perform all
  • the XOR result or the XOR result is XOR or XOR, that is, the pc0 operation formula, and the result of the operation is given to p10.
  • XOR or XOR the data of bits 2, 3, 6, and 7 in this byte, and then XOR or XOR all the XOR results or XOR results of the 16 bytes. Or, it is the pc1 operation formula, and the result of the operation is given to p11.
  • p10, p11 and p12 constitute the first binary number, and p10 is the lowest bit and p12 is the highest bit. Under the premise that only one bit of data in the memory is wrong, it is not difficult to find:
  • the first check code p10 is affected, while the first check code p11 and p12 are not affected. influences;
  • both the first check codes p10 and p11 are affected, and the first check code p12 is not affected;
  • the specific first check code is affected after the specific data error occurs here means that after the specific data error occurs, if the specific first check code obtained by the first encoding operation is re-executed, the specific first check code will be changed. It is different from the first check code formed before the data error occurs.
  • the first check code can be used to obtain which bit of data has an error. , but it cannot detect which byte of data in the corresponding bit has an error. Therefore, it is also necessary to use the second check code to obtain the data of the corresponding bit in which byte has an error.
  • the Y second check codes form a Y-bit second binary number, wherein 2 Y ⁇ M, and each second check code is obtained by performing a second encoding operation on several bytes.
  • Y is 5, which not only satisfies that errors of data of different bytes can be indicated, but also reduces the complexity of the hardware circuit of the first encoding unit 112 .
  • the second encoding operation may be XOR.
  • the first encoding unit 112 may be configured to include: a first-level operation unit, configured to perform XOR on all the data of the selected two bytes, and store several an operation result, each first operation result is the XOR result of the selected two bytes; the second-level operation unit is used to XOR at least two first operation results and generate a second check code, And Y second check codes are generated based on different coding requirements.
  • the second-level operation unit can reuse the first operation result of the first-level operation unit, so that the first encoding unit 112 can be implemented by fewer hardware circuits, thereby reducing the storage system. power consumption.
  • the first encoding operation may also be an XOR.
  • the first encoding unit may be configured to include: a first-level operation unit configured to perform an XOR operation on all data of the selected two bytes. Or, and store a number of first operation results, each first operation result is the XOR result of the selected two bytes; the second-level operation unit is used to perform XOR on at least two first operation results, and generate The second check code is generated, and Y second check codes are generated based on different coding requirements.
  • the second check codes pc13 to pc17 do not participate in the encoding operation in the encoding stage, and the second check codes pc13 to pc17 also need to participate in the operation in the subsequent decoding stage (or called the decoding stage). Therefore, in Fig.
  • the second check codes pc13 to pc17 in 4 are correspondingly marked with "x", which will be explained later, and will not be repeated here.
  • M bytes are divided into 0th to 15th bytes according to the increment of natural numbers;
  • Y second check codes are divided into 3rd to 7th second check codes according to the increment of natural numbers;
  • the two check codes are obtained in the following ways:
  • the third second check code (corresponding to p13 in Figure 4) is: XOR or XOR of all data in the 0th, 2nd, 3rd, 4th, 5th, 6th and 8th bytes ;
  • the fourth second check code (corresponding to p14 in Figure 4) is: the 0th, 1st, 4th, 5th, 7th, 9th, 10th and 12th bytes of all data exclusive Or or same or;
  • the fifth second check code (corresponding to p15 in Figure 4) is: the 1st, 2nd, 4th, 6th, 9th, 11th, 13th and 14th bytes XOR or XOR of all data;
  • the 6th second check code (corresponding to p16 in Figure 4) is: 3rd, 5th, 6th, 7th, 10th, 11th, 14th and 15th XOR or XOR of all data of bytes;
  • the seventh second check code (corresponding to p17 in Figure 4) is: the 8th, 9th, 10th
  • each second check code is obtained by an exclusive OR operation; or, each second check code is obtained by an exclusive OR operation.
  • the circuit corresponding to obtaining the second check code in the first encoding unit 112 is designed as: XOR the XOR results of byte 0 and byte 4 to obtain result 0_4; XOR the result to get result 2_6; XOR the result of byte 3 and byte 5 to get result 3_5; XOR the result of byte 1 and byte 5 to get result 1_5; The result of byte 4 is XORed to get result 1_4.
  • Figure 7 shows a schematic diagram of the principle of performing the second encoding operation on all bytes. Compared with bytes 0 to 7, the same set of circuits can be used to complete the byte coding. The operation from 8 to byte 15, that is, just changing the input, the same operation can be performed on byte 8 to byte 15 to get result 9_13, result 10_12, result 11_15, result 10_14, result 11_14. In addition, in addition to these operations that can use the same circuit, it is also necessary to XOR byte 6 and byte 7 to obtain result 6_7, and XOR the result of byte 7 and byte 9 to obtain result 7_9.
  • the first encoding unit 112 may also be configured such that, for each byte, the number of times participating in the second encoding operation is a, and a satisfies: (Y-1)/2 ⁇ a ⁇ (Y+ 1)/2, and a is a positive integer.
  • the first encoding unit 112 is used to perform the first encoding operation to obtain the first check code
  • the first encoding unit 112 is used to perform the second encoding operation to obtain the second check code. Since the method for obtaining the first update check code is the same as the method for obtaining the first check code, and the method for obtaining the second update check code is the same as the method for obtaining the second check code, the second code is no longer used in this embodiment.
  • Unit 122 will be described in detail.
  • the second encoding unit 122 is used to perform the first encoding operation to obtain the first update check code, and the second encoding unit 122 is used to perform the second encoding operation to obtain the second update check code.
  • the first coding unit 112 and the second coding unit 122 may be the same coding unit.
  • the first operation code is obtained based on the first check code and the first update check code
  • the second operation code is obtained based on the second check code and the second update check code.
  • the first operation code is generated based on the comparison between the first check code and the first update check code
  • the second operation code is generated based on the comparison between the second check code and the second update check code.
  • the error correction system further includes: a comparison module 103, and the comparison module 103 is configured to perform XOR or XOR on the first check code and the first update check code to obtain X first check codes.
  • operation code, and XOR or exclusive OR is performed on the second check code and the second update check code to obtain Y second operation codes.
  • the received data of different bits in each byte and the first check code p10 are XORed or exclusively ORed to obtain the first operation code p20 ;
  • Use the pc1 operation formula to carry out XOR or the same or the data of different bits in each byte received and the first check code p11 to obtain the first operation code p21;
  • Use the pc2 operation formula to receive the The obtained data of different bits in each byte and the first check code p12 are XORed or XORed to obtain the first operation code p22.
  • the first opcode and the second opcode correspond to PB in FIG. 2 .
  • the encoding operation in the decoding stage needs to XOR the second check code p13, p14, p15, p16 or p17, correspondingly obtain the second opcode p23, p24, p25, p26 or p27.
  • p20, p21, and p22 constitute a third binary number, and p20 is the lowest bit and p22 is the highest bit.
  • the third encoding operation is an exclusive OR (it can also be an exclusive OR in other embodiments), it is not difficult to find that:
  • the first operation codes p20, p21 and p22 are not affected, and the three first operation codes are 0, the decimal number corresponding to the third binary number 000 is 0, so as to detect an error in the data of the 0th bit.
  • the first operation code p20 is affected to be 1, while the first operation code p21 and p22 are not involved. If the affected value is 0, the third binary number is 001 and the decimal number corresponding to 1 is 1, so as to detect that the data of the first bit is wrong;
  • the third binary number is The decimal number corresponding to 010 is 2, in order to detect an error in the data of the second bit;
  • the third bit participates in the two arithmetic expressions of pc0 and pc1, the first operational codes p20 and p21 are both 1, and p12 is 0; then the third binary number is 011 corresponding to The decimal number is 3 to detect an error in the data of the 3rd bit;
  • the error correction system 1 further includes: a second encoding module 202 configured to, during the write operation, obtain a third calibration code based on a plurality of data, X first check codes and Y second check codes code verification.
  • the third check code is obtained by performing a fifth encoding operation on a plurality of data, X first check codes and Y second check codes.
  • the fifth encoding operation is XOR;
  • the second encoding module 202 is configured to perform XOR operation on a plurality of data, X first check codes and Y second check codes, to generate the third check code.
  • the error correction system 1 stores both a plurality of data, X first check codes and Y second check codes, and also stores a third check code.
  • the subsequent first check code, second check code, and third check code are jointly used to determine the number of digits of the erroneous data.
  • a third operation code will be generated based on multiple data, the first check code, the second check code, and the third check code. Both the check code and the third check code participate in the operation of generating the third operation code. If the third operation code is 0, it means there is no error or there are 2-bit errors (assuming that there are only 2 errors at most), but only according to the The third operation code is difficult to judge whether the data is wrong; if the third operation code is 1, it means that there is a 1-bit error, but it is difficult to judge whether the data is wrong or the first check code, the second check code or the third operation code alone.
  • the third check code is wrong. It can be understood that, in other embodiments, if 0 indicates an error and 1 indicates no error, then the third operational code is 1, which means there is no error or there is a 2-bit error, and if the third operational code is 0, it means that there is 1. Bit error.
  • p18 represents the third check code
  • pc8 represents the operation formula used when the fifth encoding operation is performed.
  • the first encoding operation and the second encoding operation are first performed to generate the first check codes p10-p12 and the second check codes p13-p17, and then all data, the first check codes p10-p12 and the second check codes p10-p12 and the second check codes p10-p12 are generated.
  • the check codes p13-p17 are subjected to a fifth encoding operation to obtain a third check code.
  • XOR or exclusive OR is performed on all data in each byte, and then the XOR result or the exclusive OR result is compared with the first check code p10-p12 and the second check code p13- p17 performs exclusive OR or exclusive OR, which is the pc8 operation formula, and the result of the operation is given to p18 to generate the third check code.
  • the second encoding module 202 is further configured to, during the read operation, obtain a third check code based on the data to be read, the X first check codes, the Y second check codes and the third check codes opcode. Specifically, in the decoding stage, a plurality of transmitted data, X first check codes, Y second check codes and third check codes are received, and based on the plurality of data, X first check codes , Y second check codes are subjected to a sixth encoding operation to generate a third operation code.
  • the comparison module 103 includes: X first comparison circuits (not shown), each of which is used to receive a first check code and a corresponding first update check code, and perform an exclusive OR or Same or, to obtain a first operation code; Y second comparison circuits (not shown), each second comparison circuit is used to receive a second check code and a corresponding second update check code, and perform XOR or XOR to obtain a second opcode.
  • comparison module 103 may further include: a third comparison circuit (not shown), configured to receive multiple data, X first operation codes, Y second operation codes and third check codes, and perform an exclusive OR Or the same or to get the third opcode.
  • a third comparison circuit (not shown), configured to receive multiple data, X first operation codes, Y second operation codes and third check codes, and perform an exclusive OR Or the same or to get the third opcode.
  • FIG. 8 is a functional block diagram of the first comparison circuit or the second comparison circuit in the error correction system provided by this embodiment
  • FIG. 9 is a schematic diagram of the circuit structure of the first comparison circuit or the second comparison circuit in the error correction system provided by this embodiment. .
  • the first comparison circuit or the second comparison circuit includes: a common module (not shown), connected to the power supply signal Vcc and the ground signal Vss, and controls the output power based on the first signal B and the second signal BN
  • the signal Vcc or the ground signal Vss, the first signal B and the second signal BN are inverted;
  • the first logic unit 23, connected to the common module is used to receive the third signal A and the fourth signal AN, the third signal A and the fourth signal AN is inverted, and outputs the first operation signal Y, which is the exclusive OR of the first signal B and the third signal A;
  • the second logic unit 24 is connected to the common module for receiving the third signal A and the third signal A.
  • the second operation signal YN is the same OR of the first signal B and the third signal A.
  • the first check code is used as the first signal
  • the first update check code is used as the third signal
  • the second check code is used as the first signal
  • the second update check code is used as the first signal. code as the third signal.
  • the sharing module includes: a first sharing unit 21 connected to the power supply signal Vcc and controlled to output the power supply signal Vcc based on the first signal B and the second signal BN; a second sharing unit 22 connected to the ground signal Vss, and control the output ground signal Vss based on the first signal B and the second signal BN; wherein, the first logic unit 23 is connected between the first sharing unit 21 and the second sharing unit 22, and the second logic unit 24 is connected between the between a common unit 21 and a second common unit 22 .
  • the first sharing unit 21 includes: a zeroth PMOS transistor MP0, the gate of which receives the first signal B, and the source is connected to the power supply signal Vcc; the seventh PMOS transistor MP7, the gate of which receives the second signal BN, the source The pole is connected to the power supply signal Vcc.
  • the zeroth PMOS transistor MP0 When the first signal B is at a high level and the second signal BN is at a low level, the zeroth PMOS transistor MP0 is turned off and the seventh PMOS transistor MP7 is turned on; when the first signal B is at a low level and the second signal BN is at a high level , the zeroth PMOS transistor MP0 is turned on and the seventh PMOS transistor MP7 is turned off.
  • the second sharing unit 22 includes: a zeroth NMOS transistor MN0, the gate receiving the first signal B, the source connected to the ground signal Vss; the seventh NMOS transistor MN7, the gate receiving the second signal BN, the source connected to the ground signal Vss.
  • the zeroth NMOS transistor MN0 is turned on and the seventh NMOS transistor MN7 is turned off;
  • the first signal B is at a low level and the second signal BN is at a high level
  • the The zero NMOS transistor MN0 is turned off and the seventh NMOS transistor MN7 is turned on.
  • the first logic unit 23 includes: a first PMOS transistor MP1, the gate of which receives the fourth signal AN, and the source is connected to the drain of the zeroth PMOS transistor MP0; the first NMOS transistor MN1, whose gate receives the third signal A, the drain is connected to the drain of the first PMOS transistor MP1, the source is connected to the drain of the zeroth NMOS transistor MN0; the fourth PMOS transistor MP4, the gate receives the third signal A, and the source is connected to the drain of the seventh PMOS transistor MP7
  • the fourth NMOS transistor MN4, the gate receives the fourth signal AN, the drain is connected to the drain of the fourth PMOS transistor MP4, and the source is connected to the drain of the seventh NMOS transistor MN7.
  • the second logic unit 24 includes: a second PMOS transistor MP2, the gate of which receives the third signal A, the source is connected to the drain of the zeroth PMOS transistor MP0; the second NMOS transistor MN2, the gate of which receives the fourth signal AN, and the drain is connected to The drain of the second PMOS transistor MP2, the source is connected to the drain of the zeroth NMOS transistor MN0; the fifth PMOS transistor MP5, the gate receives the fourth signal AN, the source is connected to the drain of the seventh PMOS transistor MP7; the fifth NMOS transistor The gate of the transistor MN5 receives the third signal A, the drain is connected to the drain of the fifth PMOS transistor MP5, and the source is connected to the drain of the seventh NMOS transistor MN7.
  • the drain of the first PMOS transistor MP1 is connected to the drain of the fourth PMOS transistor MP4 to output the first operation signal Y; the drain of the second PMOS transistor MP2 is connected to the drain of the fifth PMOS transistor MP5 to output the second Operation signal YN.
  • the first logic unit 23 for realizing exclusive-OR logic and the second logic unit 24 for realizing exclusive-OR logic are connected to the same shared module, so that the area occupied by the circuit structure of the shared module can be reduced, so that the first logic
  • the circuit area corresponding to the unit 23 and the second logic unit 24 is set to be larger, thereby improving the driving capability of the first logic unit 23 and the second logic unit 24, thereby improving the comparison circuit to perform the XOR operation and the XOR operation. rate, which is beneficial to improve the error detection and/or error correction rate of the error correction system.
  • FIG. 10 is another schematic structural diagram of a decoding unit corresponding to a byte according to an embodiment of the present application
  • FIG. 11 is an enlarged schematic structural diagram of a decoding unit corresponding to byte 5 in FIG. 10 .
  • X is 3, and N is 8; correspondingly, the decoder 301 has 3 input terminals and 8 output terminals, and the number of the second AND gate units 304 is 8 .
  • the decoder 301 is a three-to-eight decoder, three input terminals respectively receive three first operation codes, and eight output terminals output eight first decoded signals, and each first decoded signal is respectively Indicates the case of 8-bit data in the same byte.
  • each decoding unit 31 performs decoding processing on X first operational codes and Y second operational codes. That is, the number of decoding units 31 is the same as the number of bytes.
  • FIG. 11 only illustrates the connection relationship between one first decoded signal and one second AND gate unit 304 .
  • X is 3 and N is 8, and the decoder 301 is a three-eight decoder; the decoder 301 has 3 input terminals and 8 output terminals; the three input terminals receive three first Operation code, 8 first decoded signals output from the eight output terminals, and each first decoded signal respectively represents the condition of 8-bit data in the same byte.
  • the first operational codes p20, p21 and p22 are 0 or 1, and the output terminals are marked with 0 to 7. If an error occurs in the 0th bit, and the 0th bit does not participate in the encoding operation of the first operational code, then p20, p21 and p22 are all 0, the corresponding "0" output terminal is 1, and the rest of the output terminals are 0; if An error occurs in the 1st bit, then p20 is 1 and p21 and p22 are 0, the corresponding "1" output terminal is 1 and the rest of the output terminals are 0; and so on, if an error occurs in the 7th bit, then p20, p21 and p22 are all 1, the corresponding "7" output is 1 and the rest of the outputs are 0.
  • the number of input terminals and the number of output terminals of the decoder may also be reasonably set according to the difference between the first check code and the number of bits in each byte.
  • the first AND gate unit 302 has the characteristic that if the input terminals are all 1, the output terminal is 1, and if there are one or more 0s in the input terminal, the output terminal is 0.
  • the first AND gate unit 302 has three input terminals; the first AND gate unit 302 is further configured so that, if the number of selected operation codes is 2, an input terminal of the first AND gate unit 302 is connected to the power supply VDD.
  • the characteristic of the NOR gate unit 303 is that if the input terminals are all 0, the output is 1, and if the input terminal has one or more 1s, the output terminal is 0.
  • the NOR gate unit 303 has three input terminals; the NOR gate unit 303 is also configured so that if the number of unselected operation codes is 2, one input terminal of the NOR gate unit 303 is grounded to Vss.
  • the selected operation code corresponds to, for this byte, the second operation code corresponding to the second check code obtained by comparison; the unselected operation code corresponds to, for this byte
  • the other second check codes except the corresponding second check codes are the second operation codes obtained by comparison.
  • the second operation codes p23 and p24 are the second operation codes obtained by comparing the second check codes p13 and p14 corresponding to byte 0, then the second operation codes p23 and p24 are input to The input terminal of the first AND gate unit 302, and the remaining second operational codes p25, p26 and p27 are input to the input terminal of the NOR gate unit 303; for byte 1, the second operational codes p24 and p25 are AND byte 1
  • the corresponding second check codes p14 and p15 are compared to obtain the second operation code, then the second operation codes p24 and p25 are input to the input terminal of the first AND gate unit 302, and the remaining second operation codes p23, p26 and p27 input to the input terminal of the NOR gate unit 303; for byte 4, the second operational codes p23, p24 and p25 are input to the input terminal of the first AND gate unit 302, and the remaining second operational codes p26 and p27 are input to The input terminal of
  • the number of second AND cells 304 is the same as the number of bits in the same byte. In this embodiment, if N is 8, there are 8 second AND gate units 304 correspondingly, and according to the outputs of the 8 second AND gate units 304, it is determined whether there is erroneous data in the byte and which bit has the error. .
  • the circuit of the decoding unit 31 is the same, but the wiring of the input terminal is different, and the first AND gate unit 302 and the NOR gate corresponding to each byte are The wiring of the input terminal of the unit 303 is determined by the five arithmetic expressions of pc3 to pc7 in FIG. 4 .
  • the second operation code obtained by comparing the corresponding second check code is connected to The input end of the first AND gate unit 302 is connected to the input end of the NOR gate unit 303 through the second operation code obtained by comparing the second check codes except the corresponding second check codes; , the input terminal of the unused first AND gate unit 302 is connected to the power supply VDD, the input terminal of the unused NOR gate unit 303 is grounded to Vss; and the first operational code is connected to the input terminal of the decoder 301 . Therefore, the decoding unit 301 only uses 8 wires to connect the input terminals, and each wire transmits a first operation code or a second operation code, which saves lines and area, and helps to improve the decoding speed.
  • the decoding unit 31 corresponding to byte 5 is taken as an example, and the decoding unit 31 will be described in more detail below in combination with the working principle of the decoding unit 31 .
  • the outputs of the eight second AND gate units 304 have one 1, it means that an error has occurred in one bit of data in the byte. Specifically, the data of this byte is wrong, the second operation codes p23, p24 and p26 are all 1 and the output of the first AND gate unit 302 is 1, the unselected operation codes p25 and p27 are both 0 and the NOR gate unit 303 The output is 1; at this time, to see which of the N second AND gate units 304 corresponds to the second AND gate unit 304 corresponding to the first decoded signal, the output of the second AND gate unit 304 is 1, then the bit corresponding to this first decoded signal The data has an error.
  • the first decoding signal is 1 when the corresponding bit data is erroneous as an example, and the first decoding signal is 0 when the corresponding bit data is not erroneous.
  • it can also be set that, if the first decoding signal is 0, the data of the corresponding bit is wrong, and if the first decoding signal is 1, the data of the corresponding bit is not wrong, and accordingly,
  • Other parts can be designed by those skilled in the art as required, for example, the first decoded signal is connected to the NOR gate circuit and outputted.
  • This embodiment provides an error correction system with superior structure and performance.
  • the ECC is implemented through special design of the error correction system, which can detect and correct a 1-bit error (if the 1-bit error is located in the data instead of the check code) ), can also detect 2-bit errors, and can also reduce hardware circuits, thereby reducing the power consumption of the error correction system and improving the encoding speed and decoding speed.
  • the difference in encoding time for all data combinations is small, and the difference in decoding time for all data combinations is also small, thereby reducing the need for control circuit requirements.
  • the circuit of the decoding unit corresponding to each byte can be set to the same circuit, but the first operation code and the second operation code connected to the input terminals in different decoding units are different, which is beneficial to The lines and areas of all decoding units in the error correction system are saved, and all bytes can be decoded simultaneously for error detection and/or error correction, thus improving the error detection and correction speed of the error correction system.
  • the error correction system is applied to the storage system, and the error correction system generates X first operation codes, Y second operation codes and third operation codes based on the storage system;
  • the error correction system includes an error state judgment unit And M decoding units;
  • the error state judgment unit is used for judging the current error state, and when the plurality of data has a 1-bit error, the M decoding units are used for X first operation codes and Y th
  • the two operational codes are decoded to obtain whether there is erroneous data in the byte corresponding to the decoding unit, and to locate the bits of the erroneous data. In this way, the embodiment of the present application can detect a 1-bit error and perform error correction, and can also detect a 2-bit error.

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Abstract

一种纠错系统，应用于存储系统，且纠错系统基于存储系统产生X个第一运算码、Y个第二运算码以及第三运算码；纠错系统包括错误状态判断单元以及M个译码单元；错误状态判断单元用于判断当前的错误状态，且当所述多个数据具有1位错误时，M个译码单元用于对X个第一运算码以及Y个第二运算码进行译码处理，以获取该译码单元对应的字节中是否具有出错的数据并对出错的数据的比特位进行定位。本系统能够检测出1位错误并进行纠错，且还能够检测出2位错误。

Description

纠错系统
相关申请的交叉引用
本申请要求在2021年01月14日提交中国专利局、申请号为202110050726.6、申请名称为“纠错系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及但不限于一种纠错系统。
背景技术
半导体存储可以分为非易失性存储和易失性存储。动态随机存取存储器(Dynamic Random Access Memory，DRAM)作为易失性存储，具备存储密度高、读写速度快等优点，广泛用于各种电子系统中。
随着DRAM的制程工艺越来越先进、存储密度越来越高，DRAM中存储数据可能会发生错误，严重影响DRAM性能。因此，DRAM中通常采用纠错码(ECC，Error Checking and Correction or Error correction Coding)技术来对存储数据的错误进行检测或修正。
发明内容
本申请实施例提供一种纠错系统，应用于存储系统，所述存储系统在读写操作期间写入或读取多个数据，所述多个数据分为M个字节，且每一所述字节具有N个不同比特位的数据；所述存储系统具有编码阶段以及译码阶段，且在所述译码阶段所述纠错系统基于所述存储系统产生X个第一运算码以及、Y个第二运算码以及第三运算码，所述X个第一运算码、所述Y个第二运算码以及第三运算码用于判断所述多个数据的错误状态，且当所述多个数据具有1位错误时，所述Y个第二运算码用于定位所述1位错误所属的具体字节，所述X个第一运算码用于定位该1位错误所属的具体比特位所述第一运算码用于对N个 数据进行检测和/或纠错，所述第二运算码用于对M个字节进行检错和/或纠错；其中，所述纠错系统包括：错误状态判断单元，用于对所述X个第一运算码、所述Y个第二运算码以及所述第三运算码进行译码处理，以识别当前的错误状态；M个译码单元，每一所述译码单元与一所述字节对应，用于对X个所述第一运算码以及Y个所述第二运算码进行译码处理，以获取所述字节中是否具有出错的数据并对出错的数据的比特位进行定位。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为本申请一实施例提供的纠错系统与存储系统的功能框图；
图2为本申请一实施例提供的纠错系统的一种结构示意图；
图3为图2中每个字节对应的译码单元的放大结构示意图；
图4为本申请实施例提供的多个数据的分类示意图以及与第一校验码、第二校验码以及第三校验码之间的关系示意图；
图5示意出了字节0对应的第一校验码的放大示意图；
图6为本申请一实施例提供的纠错系统的一种结构示意图；
图7示意出了对所有字节进行第二编码运算的原理示意图；
图8为本申请实施例提供的纠错系统中第一比较电路或者第二比较电路的功能框图；
图9为本申请实施例提供的纠错系统中第一比较电路或者第二比较电路的电路结构示意图；
图10为本申请一实施例提供的译码单元与字节对应的另一种结构示意图；
图11为图10中字节5对应的译码单元的放大结构示意图。
具体实施方式
本申请实施例提供一种纠错系统，应用于存储系统，且存储系统在读写操作期间写入或读取多个数据，该多个数据分为M个字节且每一字节具有N个不同比特位数据，且在译码阶段存储系统产生X个第一运算码、Y个第二运算码以及第三运算码，第一运算码、第二运算码以及第三运算码用于判断多个数据的错误状态，且第一运算码用于对N个数据进行检错和/或纠错，第二运算码用于对M个字节进行检错和/或纠错；纠错系统包括用于识别当前的错误状态的错误状态判断单元以及用于定位出错的数据所属的具体字节以及具体比特位的译码单元。采用本申请实施例提供的纠错系统，既能够检测出1位错误并纠正，还能够检测出2位错误。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1为本申请一实施例提供的纠错系统与存储系统的功能框图，图2为本申请一实施例提供的纠错系统的一种结构示意图，图3为图2中每个字节对应的译码单元的放大结构示意图。
参考图1至图3，本实施例中，纠错系统1应用于存储系统101，该存储系统101在读写操作期间写入或读取多个数据，该多个数据分为M个字节，且每一字节具有N个不同比特位的数据；存储系统101具有编码阶段以及译码阶段，且在译码阶段该纠错系统1基于存储系统101产生X个第一运算码、Y为第二运算码以及第三运算码，X个第一运算码、Y个第二运算码以及第三运算码用于判断多个数据的错误状态，且当多个数据具有1位错误时，Y个第二运算码用于定位1位错误所属的具体字节，X个第一运算码用于定位该1位错误所属的具体比特位；纠错系统1包括：错误状态判断单元30，用于对X个第一运算 码、Y个第二运算码以及第三运算码进行译码处理，以识别当前的错误状态；M个译码单元31，每一译码单元31与一字节对应，用于对X个第一运算码以及Y个第二运算码进行译码处理，以获取字节中是否具有出错的数据并对出错的数据的比特位进行定位。
具体地，当前的错误状态包括：0位错误、1位错误、2位错误。可以认为，第一运算码用于对每一字节中的N个数据进行检错和/或纠错，第二运算码用于对M个字节进行检错和/或纠错。需要注意的是，本实施例中所称的第一运算码用于对每一字节中的N个数据进行检错和/或纠错，第二运算码用于对M个字节进行检错和/或纠错，应当理解为，所有的第一运算码和第二运算码共同用于对M个字节的所有数据进行检错和/或纠错，第二运算码将用于定位发生错误的数据位于M个字节中哪个字节，第一运算码将用于定位发生错误的数据位于该字节中的哪个比特位。
错误状态判断单元30用于根据第一运算码、第二运算码、第三运算码判断数据出错的位数，错误状态包括0位错误、1位错误、2位错误。具体地，在一个例子中，判断原理如下：
若第三运算码为1，且第一运算码以及第二运算码不全为0，则代表出错的数据是1位，该1位错误可能出现在数据中，也可能出现在第一校验码或者第二校验码中。此时通过译码单元31进行检错/纠错。有关译码单元31检测出出错的数据的位置的原理后续会进行详细说明，在此暂不做赘述。
若第三运算码为1，且第一运算码以及第二运算码全为0，则代表存储系统读取的数据未出错，第三校验码出错，此时可纠正也可不纠正，本领域技术人员可根据需要自行选择。
若第三运算码为0，且第一运算码和第二运算码全为0，则代表读取的数据未出错，且第一校验码、第二校验码和第三校验码均未出错。
若第三运算码为0，且第一运算码和第二运算码不全为0，则代表出错的位数为2位，此时无法进行纠正，根据需要，本领域技术人员可设计将出错信息发送给控制设备。
需要注意的是，以上描述的前提是假设最多只有2位错误的情况。
错误状态判断单元30与M个译码单元31连接，若存在1位错误(即第三运算码为1，且第一运算码以及第二运算码不全为0的情况)，则可采用M个译码单元31对出错的数据进行定位。
图2中示意了2个字节对应的译码单元的结构示意图，以下将结合附图对本实施例提供的纠错系统进行详细说明。
参考图2及图3，译码单元31包括：译码器301，用于接收X个第一运算码并输出N个第一译码信号，每一第一译码信号与N个数据的一比特位对应，N大于X；第一与门单元302，用于接收Z个选中运算码，并进行逻辑与运算，选中运算码为，Y个第二运算码中与该字节对应的第二运算码；或非门单元303，用于接收(Y-Z)未选运算码，并进行逻辑或非运算，未选运算码为选中运算码外的第二运算码；N个第二与门单元304，每一第二与门单元304的输入端连接第一与门302的输出端、或非门单元303的输出端以及一第一译码信号，基于N个第二与门单元304的输出对存储系统101进行检错和/或纠错；其中，X、Y以及N均为正自然数，Z为大于等于(Y-1)/2且小于等于(Y+1)/2的整数。
本实施例中，X为3且N为8，相应的译码器301为三八译码器，该译码器301具有3个输入端以及8个输出端，且第二与门单元304的数量为8，即N为8。
由于Z为大于等于(Y-1)/2且小于等于(Y+1)/2的整数，使得第一与门单元302的输入端的数量以及或非门单元303的输入端的数量之和最小，且第一与门单元302的输入端以及或非门单元303的输入端均能得到有效利用。
在一个例子中，Y为5，则2≤Z≤3，若第一与门单元门302接收2个选中运算码，即第一与门单元302需要2个输入端，则或非门单元303接收3个未选运算码，即或非门单元303需要3个输入端；若第一与门单元302接收3个选中运算码，即第一与门单元302需要3个输入端，则或非门单元303接收2个未选运算码，即或非门单元303需要2个输入端。
在一个具体例子中，第一与门单元302具有3个输入端；第一与门单元302 还被配置为，若选中运算码的数量为2，则第一与门单元302的一输入端连接电源VDD。相应的，或非门单元303具有三个输入端；或非门单元303还被配置为，若未选运算码的数量为2，则或非门单元303的一输入端接地Vss。
由于第一运算码是用于对N个数据进行检错和/或纠错，因此，若存储系统具有1位出错的数据，则通过译码器301输出的N个第一译码信号能够获知是N个不同比特位数据中哪一比特位的数据出错，但是通过N个第一译码信号无法获知是哪一个字节中的这一比特位的数据出错。
选中运算码为Y个第二运算码中与字节对应的第二运算码，此处所称的对应指的是，该字节的数据参与过该第二运算码的编码运算。具体地，Y个第二运算码中，每一第二运算码是对不同的字节中的所有数据进行编码运算得到的，可以理解的是，对于一字节而言，若该字节中的所有数据参与编码运算得到的第二运算码，定义为与该字节对应的第二运算码。不难发现，由于不同字节参与编码运算所获得第二运算码不完全相同，Y个第二运算码可用于对M个字节进行检错和/或纠错。
由于第二运算码用于对M个字节进行检错和/或纠错，对于第一与门单元302而言，与该字节对应的第二运算码即选中运算码作为第一与门单元302的输入。若存储系统具有1位出错的数据且该字节中的数据出错，则会影响到选中运算码，使得第一与门单元302的输出结果受到影响。对于或非门单元303而言，所有第二运算码中选中运算码以外的第二运算码即为未选运算码，该未选运算码作为或非门单元303的输入。若存储系统具有1位出错的数据且该字节中的数据出错，则不会影响到未选运算码，或非门单元303的输出结果不受影响；同样的，若存储系统具有1位出错的数据且该字节中的数据未出错，则会影响到未选运算码，或非门单元303的输出结果受到影响。
每个第二与门单元304连接一第一译码信号以及第一与门单元302的输出端以及或非门单元303的输出端，使得每个第二与门单元304的输出端受到该该字节中的每一比特位的数据的影响，即通过第二与门单元304的输出端能够获知该字节的对应的各比特位的数据是否出错。
举例来说，若该字节中具有1位出错的数据，且出错的数据位于第1比特位，定义与第1比特位对应的第一译码信号作为标记译码信号，那么，接收该标记译码信号的第二与门单元304的输出结果不符合预期且与其他第二与门单元304的输出结果不同，从而逆向推导出第1比特位的数据为出错的数据。若该字节中的数据均为正确的数据，则所有第二与门单元304的输出结果均相同且均符合预期，从而逆向推导出出错的数据不在该字节内。
可以理解的是，在一个例子中，存储系统101包括存储芯片，错误状态判断单元30以及M个译码单元31均可以集成在存储芯片内。
本实施例提供的纠错系统1，每个字节对应的译码单元31的电路可以设置为相同的电路，只是不同译码单元31中各输入端连接的第一运算码和第二运算码不同，有利于节省纠错系统中所有译码单元的线道和面积，且可以同时对所有字节进行译码处理以进行检错和/或纠错，因此能够提高纠错系统的检错纠错速度。
以下将结合存储系统的工作原理对纠错系统进行进一步的说明。
具体地，存储系统101可以为DRAM，例如可以为DDR4、LPDDR4、DDR5或者LPDDR5；存储系统101可以为其他类型的存储系统，例如为NAND、NOR、FeRAM、PcRAM等非易失性存储器。
对于该存储系统101而言，将数据划分为不同的字节，通常的，字节是数据处理的基本单位。以字节为单位存储和解释信息，规定1个字节由8个二进制位构成，即1个字节等于8个比特，8比特中每个比特具有相应的比特位，即1Byte＝8bit。基于此，本实施例中，N为8，以使每个字节中的比特位最大化，因而有利于提高比较系统20所需电路的利用率。可以理解的是，在其他实施例中，N也可以为其他合适的正整数。
以存储系统101在单次读写操作期间传输的数据为128位(即128比特位)作为示例，则M为16，N为8。需要说明的是，在其他实施例中，根据存储系统在读写操作期间传输的数据位数的不同，M也可以其他合适的正整数，满足M*N与读写操作期间传输的数据的位数相等即可。
图4为本实施例提供的多个数据的分类示意图以及与第一校验码、第二校验码以及第三校验码之间的关系示意图，N个数据中每一数据的比特位不同。具体地，如图4所示，对于每一字节，N个数据具有按照自然数递增的从第0至第7的比特位；对于所有字节，M个字节划分为从第0按照自然数递增至第15的16个字节。另外，对于不同的字节而言，字节内具有的N个数据均具有从第0递增至第7的8个比特位。需要说明的是，由于位置的限制，图4中实际应该为同一个行的表格拆分成了三个表格，实际为一个完整的表格。为便于图示，图5示意出了字节0对应的第一校验码的放大示意图。
图6为本申请一实施例提供的纠错系统的一种结构示意图。
参考图6，纠错系统1还包括：第一编码模块102，被配置为，在读取操作期间以及写入操作期间的编码阶段，均基于每一个字节中的若干数据产生X个第一校验码，同一第一校验码对应的若干数据在不同字节中的比特位相同，且均基于若干字节中的所有数据产生Y个第二校验码，其中，X个第一校验码用于对每一字节中的N个数据进行检错和/或纠错，Y个第二校验码用于对M个字节进行检错和/或纠错，X和Y均为正自然数。
第一校验码用于对每一字节中的N个数据进行检错和/或纠错，第二校验码用于对M个字节进行检错和/或纠错，这种检错纠错的编码方式不仅能够实现ECC，且还能够使用更少的硬件电路来实现ECC，有利于降低存储系统的功耗且优化ECC的速度以及结果。
需要注意的是，本实施例中所称的第一校验码用于对每一字节中的N个数据进行检错和/或纠错，第二校验码用于对M个字节进行检错和/或纠错，应当理解为，所有的第一校验码和第二校验码共同用于对M个字节的所有数据进行检错和/或纠错，第二校验码将用于定位发生错误的数据位于M个字节中哪个字节，第一校验码将用于定位发生错误的数据位于该字节中的哪个比特位。
本实施例中，第一编码模块102利用奇偶校验(Parity Check)原理产生第一校验码和第二校验码，相应的，第一校验码和第二校验码均为奇偶校验码。具体地，第一编码模块102包括：第一编码单元112，被配置为，在写入操作 期间，基于写入的多个数据获取X个第一校验码和Y个第二校验码；第二编码单元122，被配置为，在读取操作期间，基于待读取的多个数据获取X个第一更新校验码和Y个第二更新校验码，第一更新校验码的获取方法与第一校验码的获取方法相同，第二更新校验码的获取方法与第二校验码的获取方法相同；其中，第一运算码基于第一校验码和第一更新校验码获取，第二运算码基于第二校验码和第二更新校验码获取。
X个第一校验码构成X位第一二进制数；其中，2 X≥N，且每一第一校验码由所有字节中的若干数据进行第一编码运算得到，且每一第一校验码所对应的若干数据对应字节中不同的比特位组合。也就是说，每一第一校验码选取每一字节中的多个比特位的数据进行第一编码运算得到，且对于同一第一校验码而言所有字节中被选中的比特位组合相同，对于不同的第一校验码而言N个数据中被选中的比特位组合不同。
其中，N个数据具有从第0按照自然数递增至第N-1的比特位，且每一比特位被选中进行第一编码运算所得到的第一校验码不完全相同。具体地，不同的第一校验码基于所有字节中不同的数据进行第一编码运算得到，以使得对于不同的第一校验码而言，影响第一校验码的结果的比特位不同。同时，由于2 X≥N，可以使得每一比特位被选中进行第一编码运算得到的第一校验码不完全相同，以便通过分析，可以获取是哪一个比特位对应的数据发生了错误。
本实施例中，X为3，既能够满足不同比特位的数据的错误均能够被指示出来，且还能够减小第一编码单元112的硬件电路的复杂性。
在一个具体例子中，3个第一校验码按照比特位从低位到高位的排序包括第0位第一校验码、第1位第一校验码以及第2位第一校验码，N个数据具有从第0按照自然数递增至第N-1的比特位，举例来说：对于第0比特位，其未参与任何一个第一校验码对应的第一编码运算；对于第1比特位，其参与了第0位第一校验码对应的第一编码运算；对于第2比特位，其参与了第1位第一校验码对应的第一编码运算；对于第3比特位，其参与了第0位以及第1位第一校验码对应的第一编码运算；对于第4比特位，其参与了第2位第一校验码 对应的第一编码运算；对于第5比特位，其参与了第0位以及第2位第一校验码对应的第一编码运算；对于第6比特位，其参与了第1以及第2位第一校验码对应的第一编码运算；对于第7比特位，其参与了第0、第1以及第2位第一校验码对应的第一编码运算。应当理解的是，本领域内的技术人员可以根据需要，设置第一校验码的数目，以及其他的编码运算关系，只要满足每一比特位被选中进行第一编码运算得到的第一校验码不完全相同即可。
本实施例中，第一编码运算为异或；相应的，第一编码单元112被配置为，在X位第一二进制数中，处于最低比特的第一校验码为所有字节中第1、第3、第5以及第7比特位的数据的异或，处于最高比特的第一校验码为所有字节中第4、第5、第6以及第7比特位的数据的异或，处于中间比特的第一校验码为所有字节中第2、第3、第6以及第7比特位的数据的异或。
需要说明的是，在其他实施例中，第一编码运算还可以为同或；相应的，第一编码单元被配置为，在X位二进制数中，处于最低比特的第一校验码为所有字节中第1、第3、第5以及第7比特位的数据的同或，处于最高比特的第一校验码为所有字节中第4、第5、第6以及第7比特位的数据的同或，处于中间比特的第一校验码为所有字节中第2、第3、第6以及第7比特位的数据的同或。
以下将结合图4和图5对第一校验码的生成原理进行说明。
如图4和图5所示，“×”表示当前参与这一行的编码运算，即进行同或或者异或；且128位数据分到了第0至第15共16个字节，每个字节有8个比特位。p10、p11以及p12代表了三个第一校验码；p13、p14、p15、p16以及p17代表了5个第二校验码；pc0至pc7代表了进行编码运算时p10至p17对应采用的8个运算式。在每一行中，所有标“×”的位置表示这一列对应的数据需要在这个运算式里参与异或或者同或。第一校验码和第二校验码与pb对应。
在写入操作期间的编码阶段的第一编码运算或第二编码运算时，利用pc0至pc7这8个运算式进行第一编码运算或第二编码运算，运算的结果分别存至p10至p17中，且p10至p17不参与第一编码运算或第二编码运算；在译码阶段时，各行对应的运算式不变，且存储的p10至p17需要参与运算，因此图4 的表格中p10至p17对应标记有“×”，关于这一点，后续会进行详细说明。
具体地，在写入操作期间的编码阶段：对于每一个字节，将这个字节中的第1、3、5、7位的数据进行异或或者同或，再将16个字节的所有异或结果或者同或结果进行异或或者同或，即为pc0运算式，运算的结果给到p10。对于每一个字节，将这个字节中的第2、3、6、7位的数据进行异或或者同或，再将16个字节的所有异或结果或者同或结果进行异或或者同或，即为pc1运算式，运算的结果给到p11。对于每一个字节，将这个字节中的第4、5、6、7位的数据进行异或或者同或，再将16个字节的所有异或结果或者同或结果进行异或或者同或，即为pc2运算式，运算的结果给到p12。
p10、p11以及p12构成第一二进制数，且p10为最低位且p12为最高位。在存储器的多个数据中只有一位数据发生错误的前提下，不难发现：
如果第0比特位的数据发生错误，由于第0比特位未参与pc0、pc1以及pc2这三个运算式，则第一校验码p10、p11以及p12均未受到影响；
如果第1比特位的数据发生错误，由于第1比特位参与pc0这个算式而未参与pc1以及pc2两个运算式，第一校验码p10受到影响，而第一校验码p11以及p12未受到影响；
如果第2比特位的数据发生错误，由于第2比特位参与pc1这个运算式，则第一校验码p10和p12未受到影响，第一校验码p11受到影响；
如果第3比特位的数据发生错误，由于第3比特位参与pc0以及pc1两个运算式，则第一校验码p10以及p11均受到影响，第一校验码p12未受到影响；
依次类推，如果第7比特位的数据发生错误，由于第7比特位参与pc0、pc1以及pc2三个运算式，则第一校验码p10、p11以及p12均受到影响。
需要注意的是，此处所说特定数据发生错误后特定第一校验码受到影响的意思是，在特定数据发生错误后，若重新进行第一编码运算得到的该特定第一校验码，会与数据发生错误前形成的该第一校验码不同。
可以理解的是，对于每一运算式而言，由于不同字节中的参与第一编码运算的比特位是相同的，因此通过第一校验码可以获取是哪一个比特位的数据发 生了错误，但是并不能检测是哪一个字节中相应比特位的数据发生错误。因此，还需要通过第二校验码以获取是哪一个字节中的相应比特位的数据发生错误。
Y个第二校验码构成Y位第二二进制数，其中，2 Y≥M，且每一第二校验码由若干字节进行第二编码运算得到。
2 Y≥M，以保证每一字节参与第二编码运算所得到的第二校验码不完全相同。具体地，不同的第二校验码基于不同的若干字节进行第二编码运算得到，以使得对于不同的第二校验码而言，影响第二校验码的结果的字节不同，以便于综合分析以获取是哪一个字节中的数据发生了错误。再结合是字节中哪一个比特位发生了错误，以最终判断出是哪一个字节中的哪一个比特位的数据发生错误。需要注意的是，此处所说的影响第二校验码的结果中的“影响”意思与前面所述的“影响”含义相同。
本实施例中，Y为5，既能够满足不同字节的数据的错误均能够被指示出来，且还能够减小第一编码单元112的硬件电路的复杂性。第二编码运算可以为异或，相应的，第一编码单元112可以被配置为，包括：第一级运算单元，用于对选中的两个字节的所有数据进行异或，并存储若干第一运算结果，每一第一运算结果为选中的两个字节的异或结果；第二级运算单元，用于对至少两个第一运算结果进行异或，并产生第二校验码，并基于不同的编码需求产生Y个第二校验码。通过对第一编码单元112的特殊设计，第二级运算单元可以重复使用第一级运算单元的第一运算结果，使得第一编码单元112可以通过更少的硬件电路来实现，从而降低存储系统的功耗。
在其他实施例中，第一编码运算也可以为同或，相应的，第一编码单元可以被配置为，包括：第一级运算单元，用于对选中的两个字节的所有数据进行同或，并存储若干第一运算结果，每一第一运算结果为选中的两个字节的同或结果；第二级运算单元，用于对至少两个第一运算结果进行同或，并产生所述第二校验码，并基于不同的编码需求产生Y个第二校验码。
具体地，如图4所示，在写入操作期间的编码阶段，对于每一个字节，将这个字节中的所有8个比特位的数据进行异或，得到这个字节的异或结果；然 后将总共16个字节的16个异或结果，根据pc3至pc7这5个运算式进行第二编码运算，即每一行的表格中标示“×”的数据均参与运算，相应得到第二校验码pc13至pc17。可以理解的是，在编码阶段第二校验码pc13至pc17不参与编码运算，在后续的解码阶段(或称为译码阶段)第二校验码pc13至pc17也需要参与运算，因此在图4中第二校验码pc13至pc17相应也标示有“×”，关于这一点后续会说明，在此不做赘述。
本实施例中，M个字节按照自然数递增分为第0至第15个字节；Y个第二校验码按照自然数递增分为第3至第7个第二校验码；5个第二校验码的获取方式分别如下：
第3个第二校验码(对应图4中的p13)为：第0、第2、第3、第4、第5、第6以及第8个字节的所有数据的异或或者同或；第4个第二校验码(对应图4中的p14)为：第0、第1、第4、第5、第7、第9、第10以及第12个字节的所有数据的异或或同或；第5个第二校验码(对应图4中的p15)为：第1、第2、第4、第6、第9、第11、第13以及第14个字节的所有数据的异或或同或；第6个第二校验码(对应图4中的p16)为：第3、第5、第6、第7、第10、第11、第14以及第15个字节的所有数据的异或或同或；第7个第二校验码(对应图4中的p17)为：第8、第9、第10、第11、第12、第13以及第15个字节的所有数据的异或或同或。
需要说明的是，每一第二校验码均是异或运算获得的；或者，每一第二校验码均是同或运算获得的。
第一编码单元112中用于获取第二校验码对应的电路被设计为：将字节0和字节4的异或结果进行异或，得到结果0_4；将字节2和字节6的结果进行异或，得到结果2_6；将字节3和字节5的结果进行异或，得到结果3_5；将字节1和字节5的结果进行异或，得到结果1_5；将字节1和字节4的结果进行异或，得到结果1_4。
不难发现，如图7所示，图7示意出了对所有字节进行第二编码运算的原理示意图，相较于字节0至7而言，可以使用同样的一套电路完成对字节8到 字节15的运算，即只是改变输入，可以对字节8到字节15进行同样的运算，得到结果9_13、结果10_12、结果11_15、结果10_14、结果11_14。此外，除了这些可以使用同样的电路的运算，还需要将字节6和字节7进行异或，得到结果6_7，将字节7和字节9的结果进行异或，得到结果7_9。
按照pc3至pc7的运算式要求进行异或：例如根据运算式pc3，将结果0_4、结果2_6、结果3_5以及字节8的异或结果进行异或，得到第二校验码p13；根据运算式pc4，将结果0_4、结果1_5、结果7_9以及结果10_12进行异或，得到第二校验码p14；关于第二校验码p15、p16以及p17的获取方式不再一一具体说明。可以理解的是，结果0_4、结果2_6等都可以重复使用，以节省电路资源。
此外，本实施例中，第一编码单元112还可以被配置为，对于每一字节，参与第二编码运算的次数为a，a满足：(Y-1)/2≤a≤(Y+1)/2，且a为正整数。通过这样的设置，在进行后续的译码阶段所需的译码电路中，电路的线路和面积能够得到减少，且还有利于提升译码速度。
由前述分析可知，在写入操作期间，利用第一编码单元112进行第一编码运算获取第一校验码，利用第一编码单元112进行第二编码运算获取第二校验码。由于第一更新校验码的获取方法与第一校验码的获取方法相同，第二更新校验码的获取方法与第二校验码的获取方法相同，本实施例不再对第二编码单元122进行赘述。
本实施例中，在读取操作期间，利用第二编码单元122进行第一编码运算获取第一更新校验码，利用第二编码单元122进行第二编码运算获取第二更新校验码。相应的，第一编码单元112和第二编码单元122可以为同一编码单元。
第一运算码基于第一校验码和第一更新校验码获取，第二运算码基于第二校验码和第二更新校验码获取。具体地，基于第一校验码和第一更新校验码进行比较产生第一运算码，基于第二校验码和第二更新校验码进行比较产生第二运算码。相应的，参考图6，纠错系统还包括：比较模块103，比较模块103被配置为，对第一校验码以及第一更新校验码进行异或或者同或，以获取X个 第一运算码，且对第二校验码以及第二更新校验码进行异或或者同或，以获取Y个第二运算码。
更具体地，结合参考图4以及前述对第一校验码和第二校验码的产生原理的说明。对于第一运算码p20而言，利用pc0运算式，将接收到的每个字节中的不同比特位的数据、以及第一校验码p10进行异或或者同或，得到第一运算码p20；利用pc1运算式，将接收到的每个字节中的不同比特位的数据、以及第一校验码p11进行异或或者同或，得到第一运算码p21；利用pc2运算式，将接收到的每个字节中的不同比特位的数据、以及第一校验码p12进行异或或者同或，得到第一运算码p22。第一运算码和第二运算码在图2中与PB对应。
同样的，对于第二校验码和第二运算码而言，在译码阶段的编码运算，需要在前述的编码阶段的编码运算基础上，分别再异或第二校验码p13、p14、p15、p16或者p17，相应的获得第二运算码p23、p24、p25、p26或者p27。
p20、p21以及p22构成第三二进制数，且p20为最低位且p22为最高位。在多个数据中只有一位数据发生错误的前提下，若第三编码运算为异或的话(在其他实施例中也可以为同或)，不难发现：
如果第0比特位的数据发生错误，由于第0比特位未参与pc0、pc3以及pc3这三个算式，则第一运算码p20、p21以及p22均未受到影响，三个第一运算码均为0，则第三二进制数000对应的十进制数为0，以检测出第0比特位的数据发生错误。
如果第1比特位的数据发生错误，由于第一比特位参与pc0这个运算式而未参与pc1以及pc2两个运算式，第一运算码p20受到影响为1，而第一运算码p21以及p22未受到影响为0，则第三二进制数为001对应的十进制数为1，以检测出第1比特位的数据发生错误；
如果第2比特位的数据发生错误，由于第2比特位参与pc1这个运算式，则第一运算码p20为0，第一运算码p21为1，p12为0，则第三二进制数为010对应的十进制数为2，以检测出第2比特位的数据发生错误；
如果第3比特位的数据发生错误，由于第3比特位参与pc0以及pc1两个 运算式，则第一运算码p20以及p21均为1，p12为0；则第三二进制数为011对应的十进制数为3，以检测出第3比特位的数据发生错误；
依次类推，如果第7比特位的数据发生错误，由于第7比特位参与pc0、pc1以及pc2三个运算式，则第一运算码p20、p21以及p22均为1；则第三二进制数111对应的十进制数为7，以检测出第7比特位的数据发生错误。
此外，纠错系统1还包括：第二编码模块202，被配置为，在写入操作期间，基于多个数据、X个第一校验码以及Y个第二校验码，获取第三校验码。
具体地，第三校验码由多个数据、X个第一校验码以及Y个第二校验码进行第五编码运算得到。本实施例中，第五编码运算为异或；相应的，第二编码模块202被配置为，对多个数据、X个第一校验码以及Y个第二校验码进行异或运算，以生成第三校验码。在写入操作期间，纠错系统1既存储多个数据、X个第一校验码以及Y个第二校验码，且还存储第三校验码。
后续第一校验码、第二校验码以及第三校验码共同用于判断出错的数据的位数。具体地，后续在读取数据期间会基于多个数据、第一校验码、第二校验码以及第三校验码生成第三运算码，由于所有数据、第一校验码、第二校验码以及第三校验码均参与了生成第三运算码的运算，若第三运算码为0则代表没有错误或者有2位错误(假设最多只有2位出错的情况)，但是仅根据第三运算码难以判断数据是否出错；若第三运算码为1，则代表有1位错误，但是仅根据第三运算码难以判断是数据出错还是第一校验码、第二校验码或者第三校验码出错。可以理解的是，在其他实施例中，若0表示出错且1表示未出错，则第三运算码为1则代表没有错误或者有2位错误，若第三运算码为0，则代表有1位错误。
以下将结合图4对第三校验码的生成原理进行说明。
如图4所示，p18代表了第三校验码且pc8代表了进行第五编码运算时采用的运算式。具体地，先进行第一编码运算和第二编码运算以生成第一校验码p10-p12以及第二校验码p13-p17，然后对所有数据、第一校验码p10-p12以及第二校验码p13-p17进行第五编码运算，得到第三校验码。
更具体地，在编码阶段，对每一字节中的所有数据进行异或或者同或，再将异或结果或者同或结果与第一校验码p10-p12以及第二校验码p13-p17进行异或或者同或，即为pc8运算式，运算的结果给到p18以生成第三校验码。
另外，第二编码模块202还被配置为，在读取操作期间，基于待读取的数据、X个第一校验码、Y个第二校验码以及第三校验码，获取第三运算码。具体地，在译码阶段，接收传输的多个数据、X个第一校验码、Y个第二校验码以及第三校验码，并基于多个数据、X个第一校验码、Y个第二校验码进行第六编码运算产生第三运算码。
结合参考图4以及前述对第三校验码的产生原理的说明，具体地，利用pc8运算式，将接收到的所有数据、X个第一校验码、Y个第二校验码以及第三校验码p18进行第六编码运算，得到第三运算码p28。
结合第一运算码、第二运算码以及第三运算码能够判断出错的数据的位数是0为、1位还是2位。
具体地，比较模块103包括：X个第一比较电路(未图示)，每一第一比较电路用于接收一第一校验码以及相应的第一更新校验码，并进行异或或者同或，以获取一第一运算码；Y个第二比较电路(未图示)，每一第二比较电路用于接收一第二校验码以及相应的第二更新校验码，并进行异或或者同或，以获取一第二运算码。
此外，比较模块103还可以包括：第三比较电路(未图示)，用于接收多个数据、X个第一运算码、Y个第二运算码以及第三校验码，并进行异或或者同或，以获取第三运算码。
图8为本实施例提供的纠错系统中第一比较电路或者第二比较电路的功能框图，图9为本实施例提供的纠错系统中第一比较电路或者第二比较电路的电路结构示意图。
本实施例中，参考图8，第一比较电路或者第二比较电路包括：共用模块(未标示)，连接电源信号Vcc以及接地信号Vss，并基于第一信号B以及第二信号BN控制输出电源信号Vcc或者接地信号Vss，第一信号B与第二信号BN 反相；第一逻辑单元23，连接共用模块，用于接收第三信号A和第四信号AN，第三信号A和第四信号AN反相，并输出第一运算信号Y，第一运算信号Y为第一信号B与第三信号A的异或；第二逻辑单元24，连接共用模块，用于接收第三信号A和第四信号AN并输出第二运算信号YN，第二运算信号YN为第一信号B与第三信号A的同或。其中，对于第一比较电路，第一校验码作为第一信号，第一更新校验码作为第三信号；对于第二比较电路，第二校验码作为第一信号，第二更新校验码作为第三信号。
本实施例中，参考图8，共用模块包括：第一共用单元21，连接电源信号Vcc，并基于第一信号B以及第二信号BN控制输出电源信号Vcc；第二共用单元22，连接接地信号Vss，并基于第一信号B以及第二信号BN控制输出接地信号Vss；其中，第一逻辑单元23连接在第一共用单元21以及第二共用单元22之间，第二逻辑单元24连接在第一共用单元21以及第二共用单元22之间。
具体地，参考图9，第一共用单元21包括：第零PMOS管MP0，栅极接收第一信号B，源极连接电源信号Vcc；第七PMOS管MP7，栅极接收第二信号BN，源极连接电源信号Vcc。第一信号B为高电平、第二信号BN为低电平时，第零PMOS管MP0截止且第七PMOS管MP7导通；第一信号B为低电平、第二信号BN为高电平时，第零PMOS管MP0导通且第七PMOS管MP7截止。
第二共用单元22包括：第零NMOS管MN0，栅极接收第一信号B，源极连接接地信号Vss；第七NMOS管MN7，栅极接收第二信号BN，源极连接接地信号Vss。第一信号B高电平、第二信号BN为低电平时，第零NMOS管MN0导通且第七NMOS管MN7截止；第一信号B低电平、第二信号BN为高电平时，第零NMOS管MN0截止且第七NMOS管MN7导通。
本实施例中，第一逻辑单元23包括：第一PMOS管MP1，栅极接收第四信号AN，源极连接第零PMOS管MP0的漏极；第一NMOS管MN1，栅极接收第三信号A，漏极连接第一PMOS管MP1的漏极，源极连接第零NMOS管MN0的漏极；第四PMOS管MP4，栅极接收第三信号A，源极连接第七PMOS管MP7的漏极；第四NMOS管MN4，栅极接收第四信号AN，漏极连接第四 PMOS管MP4的漏极，源极连接第七NMOS管MN7的漏极。
第二逻辑单元24包括：第二PMOS管MP2，栅极接收第三信号A，源极连接第零PMOS管MP0的漏极；第二NMOS管MN2，栅极接收第四信号AN，漏极连接第二PMOS管MP2的漏极，源极连接第零NMOS管MN0的漏极；第五PMOS管MP5，栅极接收第四信号AN，源极连接第七PMOS管MP7的漏极；第五NMOS管MN5，栅极接收第三信号A，漏极连接第五PMOS管MP5的漏极，源极连接第七NMOS管MN7的漏极。
此外，第一PMOS管MP1的漏极与第四PMOS管MP4的漏极连接，输出第一运算信号Y；第二PMOS管MP2的漏极与第五PMOS管MP5的漏极连接，输出第二运算信号YN。
用于实现异或逻辑的第一逻辑单元23以及用于实现同或逻辑的第二逻辑单元24连接同一共用模块，因而可以减小共用模块的电路结构占用的面积，以便于能够将第一逻辑单元23和第二逻辑单元24对应的电路面积设置的更大一些，从而提高第一逻辑单元23以及第二逻辑单元24具有的驱动能力，进而提高比较电路进行同或运算以及异或运算的运算速率，进而有利于提高纠错系统的检错和/或纠错速率。
以下将结合上述提及的纠错系统产生第一校验码、第二校验码、第一运算码以及第二运算码对译码单元31进行更进一步的说明。图10为本申请一实施例提供的译码单元与字节对应的另一种结构示意图，图11为图10中字节5对应的译码单元的放大结构示意图。
参考图10以及图11，本实施例中，X为3，且N为8；相应的，译码器301具有3个输入端以及8个输出端，且第二与门单元304的数量为8。具体地，译码器301为三八译码器，三个输入端分别接收三个第一运算码，八个输出端输出的8个第一译码信号，且每一第一译码信号分别表征同一字节中8个比特位的数据的情况。
图10中以p20、p21以及p22标示第一运算码，以p23、p24、p25、p26以及p27标示第二运算码。具体地，每一译码单元31对X个第一运算码和Y 个第二运算码进行译码处理。也就是说，译码单元31的数量与字节的数量相同。
需要说明的是，图11中仅示意出了一个第一译码信号与一个第二与门单元304的连接关系。
本实施例中，X为3且N为8，译码器301为三八译码器；该译码器301具有3个输入端以及8个输出端；三个输入端分别接收三个第一运算码，八个输出端输出的8个第一译码信号，且每一第一译码信号分别表征同一字节中8个比特位的数据的情况。
具体地，第一运算码p20、p21以及p22为0或者1，且输出端以0至7进行标示。若第0比特位发生错误，第0比特位未参与第一运算码的编码运算，则p20、p21以及p22均为0，相应的“0”输出端为1且其余输出端均为0；若第1比特位发生错误，则p20为1且p21以及p22为0，相应的“1”输出端为1且其余输出端均为0；依次类推，若第7比特位发生错误，则p20、p21以及p22均为1，相应的“7”输出端为1且其余输出端均为0。
需要说明的是，在其他实施例中，根据第一校验码和每个字节中比特位的数量的不同，也可以合理设置译码器的输入端的数量以及输出端的数量。
第一与门单元302具有的特性为，若输入端均为1则输出端为1，若输入端中具有一个或多个0则输出端为0。本实施例中，第一与门单元302具有三个输入端；第一与门单元302还被配置为，若选中运算码的数量为2，则第一与门单元302的一输入端连接电源VDD。
或非门单元303具有的特性为，若输入端均为0则输出为1，若输入端具有一个或者多个1则输出端为0。本实施例中，或非门单元303具有三个输入端；或非门单元303还被配置为，若未选运算码的数量为2，则或非门单元303的一输入端接地Vss。
具体地，选中运算码对应为，对于这一字节而言，与之对应的所述第二校验码经由比较后得到的第二运算码；未选运算码对应为，对于这一字节而言，除与之对应的第二校验码外的其余第二校验码经由比较得到的第二运算码。
例如，对于字节0而言，第二运算码p23和p24为与字节0对应的第二检 验码p13和p14进行过比较获得的第二运算码，则第二运算码p23和p24输入至第一与门单元302的输入端，其余第二运算码p25、p26以及p27输入至或非门单元303的输入端；对于字节1而言，第二运算码p24以及p25为与字节1对应的第二校验码p14和p15进行过比较获得的第二运算码，则第二运算码p24和p25输入至第一与门单元302的输入端，其余第二运算码p23、p26以及p27输入至或非门单元303的输入端；对于字节4而言，则第二运算码p23、p24和p25输入至第一与门单元302的输入端，其余第二运算码p26以及p27输入至或非门单元303的输入端。关于其他字节的情况，不再一一列举。
第二与门单元304的数量与同一字节中的比特位的数量相同。本实施例中，N为8，则相应具有8个第二与门单元304，且根据8个第二与门单元304的输出判断该字节中是否具有出错的数据以及是哪个比特位发生错误。
不难发现，本实施例中，对于每个字节而言译码单元31的电路都是一样的，只是输入端的接线不同，且每个字节对应的第一与门单元302和或非门单元303的输入端的接线由图4中的pc3至pc7这5个运算算式决定，对于每一个字节，将与之对应的所述第二校验码经由比较后得到的第二运算码连接到第一与门单元302的输入端，将除与之对应的第二校验码外的其余第二校验码经由比较所得到的第二运算码连接到或非门单元303的输入端；此外，没有用到的第一与门单元302的输入端连接电源VDD，没有用到的或非门单元303的输入端接地Vss；且第一运算码连接译码器301的输入端。因此，译码单元301只用到了8根走线连接输入端，每根走线传输一第一运算码或一第二运算码，从而节省了线道和面积，同时有利于提升译码速度。
为了便于理解译码单元31，以字节5对应的译码单元作为示例，以下将结合译码单元31的工作原理对译码单元31进行更详细的说明。
若8个第二与门单元304的输出均为0，则表示该字节中所有的数据均未出错。
若8个第二与门单元304的输出具有1个1，则表示该字节中一比特位的数据发生了错误。具体地，该字节的数据出错，第二运算码p23、p24以及p26 均为1且第一与门单元302的输出为1，未选运算码p25以及p27均为0且或非门单元303的输出为1；此时，看N个第二与门单元304中哪一个第一译码信号对应的第二与门单元304的输出为1，则这一第一译码信号对应的比特位的数据发生错误。
可以理解的是，本实施例中，以第一译码信号为1则对应的比特位的数据发生错误作为示例，且第一译码信号为0则对应的比特位的数据未发生错误。在其他实施例中，也可以设置为，第一译码信号为0则对应的比特位的数据发生错误，且第一译码信号为1则对应的比特位的数据未发生错误，相应的，其他部分本领域技术人员可根据需要自行设计，比如第一译码信号连接到或非门电路并输出等。
需要注意的是，若M个字节中所有的数据均未出错，仅X个第一校验码中的1位发生错误，则第一运算码中会有一个为1，进而译码器301的其中一个输出为1，但是由于Y个第二校验码未发生错误，则所有的第二运算码均为0，进而第一与门单元302的输出为0，第二与门单元304的输出也均为0，表示M个字节中所有数据均未出错。若M个字节中所有的数据均未出错，仅Y个第二校验码中的1位发生错误，第一运算码均为0，进而译码器301的输出端为1，但是由于其余Y-1个第二校验码均未发生错误，则与之对应的Y-1个第二运算码为0，则第一与门单元302的输出为0，进而第二与门单元304的输出也均为0，表示M个字节中所有数据均未出错。
本实施例提供一种结构性能优越的纠错系统，通过对纠错系统的特殊设计实现ECC，既能够对1位错误进行检测并纠正(若该1位错误位于数据中而非校验码中)，还能够对2位错误进行检测，且还能够减少硬件电路，从而降低纠错系统的功耗且提升编码速度以及译码速度。此外，通过对第一校验码和第二校验码的特殊设计，使得对于所有数据组合的编码时间的差异小，且对于所有数据组合的译码时间的差异也很小，从而降低了对控制电路的要求。
此外，本申请实施例中，每个字节对应的译码单元的电路可以设置为相同的电路，只是不同译码单元中各输入端连接的第一运算码和第二运算码不同， 有利于节省纠错系统中所有译码单元的线道和面积，且可以同时对所有字节进行译码处理以进行检错和/或纠错，因此能够提高纠错系统的检错纠错速度。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请明的保护范围应当以权利要求限定的范围为准。
工业实用性
在本申请实施例中，纠错系统应用于存储系统，且纠错系统基于存储系统产生X个第一运算码、Y个第二运算码以及第三运算码；纠错系统包括错误状态判断单元以及M个译码单元；错误状态判断单元用于判断当前的错误状态，且当所述多个数据具有1位错误时，M个译码单元用于对X个第一运算码以及Y个第二运算码进行译码处理，以获取该译码单元对应的字节中是否具有出错的数据并对出错的数据的比特位进行定位。这样，本申请实施例能够检测出1位错误并进行纠错，且还能够检测出2位错误。

Claims (17)

  1. 一种纠错系统，应用于存储系统，所述存储系统在读写操作期间写入或读取多个数据，所述多个数据分为M个字节，且每一所述字节具有N个不同比特位的数据；所述存储系统具有编码阶段以及译码阶段，且在所述译码阶段所述纠错系统基于所述存储系统产生X个第一运算码、Y个第二运算码以及第三运算码，所述X个第一运算码、所述Y个第二运算码以及第三运算码用于判断所述多个数据的错误状态，且当所述多个数据具有1位错误时，所述Y个第二运算码用于定位所述1位错误所属的具体字节，所述X个第一运算码用于定位该1位错误所属的具体比特位；其中，所述纠错系统包括：
    错误状态判断单元，用于对所述X个第一运算码、所述Y个第二运算码以及所述第三运算码进行译码处理，以识别当前的错误状态；
    M个译码单元，每一所述译码单元与一所述字节对应，用于对X个所述第一运算码以及Y个所述第二运算码进行译码处理，以获取所述字节中是否具有出错的数据并对出错的数据的比特位进行定位。
  2. 根据权利要求1所述的纠错系统，其中，所述译码单元包括：
    译码器，用于接收所述X个第一运算码并输出N个第一译码信号，每一所述第一译码信号与N个数据的一比特位对应，N大于X；
    第一与门单元，用于接收Z个选中运算码，并进行逻辑与运算，所述选中运算码为，所述Y个第二运算码中与所述字节对应的所述第二运算码；
    或非门单元，用于接收(Y-Z)个未选运算码，并进行逻辑或非运算，所述未选运算码为所述选中运算码除外的所述第二运算码；
    N个第二与门单元，每一所述第二与门单元的输入端连接所述第一与门单元的输出端、所述或非门单元的输出端以及一所述第一译码信号，基于所述N个第二与门单元的输出对所述存储系统进行检错和/或纠错；
    其中，所述X、Y以及N均为正自然数，Z为大于等于(Y-1)/2且小于等于(Y+1)/2的整数。
  3. 根据权利要求2所述的纠错系统，其中，所述X为3，N为8，所述译码器具有3个输入端以及8个输出端；所述第二与门单元的数量为8。
  4. 根据权利要求2所述的纠错系统，其中，所述Y为5，所述第一与门单元具有3个输入端；所述第一与门单元还被配置为，若所述选中运算码的数量为2，则所述第一与门单元的一输入端连接电源。
  5. 根据权利要求2或4所述的纠错系统，其中，所述Y为5，所述或非门单元具有三个输入端；所述或非门单元还被配置为，若所述未选运算码的数量为2，则所述或非门单元的一输入端接地。
  6. 根据权利要求2所述的纠错系统，所述纠错系统还包括：第一编码模块，被配置为，在读取操作期间以及写入操作期间的所述编码阶段，均基于每一个所述字节中的若干数据产生X个第一校验码，同一所述第一校验码对应的所述若干数据在不同所述字节中的比特位相同，且均基于若干所述字节中的所有数据产生Y个第二校验码，其中，所述X个第一校验码用于对每一所述字节中的所述N个数据进行检错和/或纠错，所述Y个第二校验码用于对所述M个字节进行检错和/或纠错，所述X和Y均为正自然数。
  7. 根据权利要求6所述的纠错系统，其中，所述第一编码模块包括：
    第一编码单元，被配置为，在写入操作期间，基于写入的多个数据获取X个所述第一校验码和Y个所述第二校验码；
    第二编码单元，被配置为，在读取操作期间，基于待读取的多个数据获取X个第一更新校验码和Y个第二更新校验码，所述第一更新校验码的获取方法与所述第一校验码的获取方法相同，所述第二更新校验码的获取方法与所述第二校验码的获取方法相同；
    其中，所述第一运算码基于所述第一校验码和所述第一更新校验码获取，所述第二运算码基于所述第二校验码和所述第二更新校验码获取。
  8. 根据权利要求7所述的纠错系统，其中，所述第一编码单元和所述第二编码单元为同一编码单元。
  9. 根据权利要求7所述的纠错系统，所述纠错系统还包括：比较模块，所 述比较模块被配置为，对所述第一校验码以及所述第一更新校验码进行异或或者同或，以获取X个所述第一运算码，且对所述第二校验码以及所述第二更新校验码进行异或或者同或，以获取Y个所述第二运算码。
  10. 根据权利要求9所述的纠错系统，其中，所述比较模块包括：
    X个第一比较电路，每一所述第一比较电路用于接收一所述第一校验码以及相应的所述第一更新校验码，并进行异或或者同或，以获取一所述第一运算码；
    Y个第二比较电路，每一所述第二比较电路用于接收一所述第二校验码以及相应的所述第二更新校验码，并进行异或或者同或，以获取一所述第二运算码。
  11. 根据权利要求10所述的纠错系统，其中，所述第一比较电路或者所述第二比较电路包括：
    共用模块，连接电源信号以及接地信号，并基于第一信号以及第二信号控制输出所述电源信号或者所述接地信号，所述第一信号与所述第二信号反相；第一逻辑单元，连接所述共用模块，用于接收第三信号和第四信号，所述第三信号与所述第四信号反相，并输出第一运算信号，所述第一运算信号为所述第一信号与所述第三信号的异或；
    第二逻辑单元，连接所述共用模块，用于接收所述第三信号和所述第四信号并输出第二运算信号，所述第二运算信号为所述第一信号与所述第三信号的同或；
    其中，对于所述第一比较电路，所述第一校验码作为所述第一信号，所述第一更新校验码作为所述第三信号；对于所述第二比较电路，所述第二校验码作为所述第一信号，所述第二更新校验码作为所述第三信号。
  12. 根据权利要求11所述的纠错系统，其中，所述共用模块包括：
    第一共用单元，连接所述电源信号，并基于所述第一信号以及所述第二信号控制输出所述电源信号；
    第二共用单元，连接所述接地信号，并基于所述第一信号以及所述第二信 号控制输出所述接地信号；
    其中，所述第一逻辑单元连接在所述第一共用单元与所述第二共用单元之间，所述第二逻辑单元连接在所述第一共用单元与所述第二共用单元之间。
  13. 根据权利要求12所述的纠错系统，其中，所述第一共用单元包括：
    第零PMOS管，栅极接收所述第一信号，源极连接所述电源信号；第七PMOS管，栅极接收所述第二信号，源极连接所述电源信号；
    所述第二共用单元包括：第零NMOS管，栅极接收所述第一信号，源极连接所述接地信号；第七NMOS管，栅极接收所述第二信号，源极连接所述接地信号。
  14. 根据权利要求13所述的纠错系统，其中，所述第一逻辑单元包括：
    第一PMOS管，栅极接收所述第四信号，源极连接所述第零PMOS管的漏极；
    第一NMOS管，栅极接收所述第三信号，漏极连接所述第一PMOS管的漏极，源极连接所述第零NMOS管的漏极；
    第四PMOS管，栅极接收所述第三信号，源极连接所述第七PMOS管的漏极；
    第四NMOS管，栅极接收所述第四信号，漏极连接所述第四PMOS管的漏极，源极连接所述第七NMOS管的漏极。
  15. 根据权利要求13所述的纠错系统，其中，所述第二逻辑单元包括：
    第二PMOS管，栅极接收所述第三信号，源极连接所述第零PMOS管的漏极；
    第二NMOS管，栅极接收所述第四信号，漏极连接所述第二PMOS管的漏极，源极连接所述第零NMOS管的漏极；
    第五PMOS管，栅极接收所述第四信号，源极连接所述第七PMOS管的漏极；
    第五NMOS管，栅极接收所述第三信号，漏极连接所述第五PMOS管的漏极，源极连接所述第七NMOS管的漏极。
  16. 根据权利要求7所述的纠错系统，所述纠错系统还包括：第二编码模块，被配置为，在写入操作期间，基于所述多个数据、所述X个第一校验码以及所述Y个第二校验码，获取第三校验码；还被配置为，在读取操作期间，基于待读取的多个数据、所述X个第一校验码、所述Y个第二校验码以及所述第三校验码，获取所述第三运算码。
  17. 根据权利要求1所述的纠错系统，其中，所述存储系统包括存储芯片，所述错误状态判断单元和M个所述译码单元集成在所述存储芯片内。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1242088A (zh) * 1996-10-25 2000-01-19 英特尔公司 利用错误定位码校正一个多级单元存储器的方法和装置
US20040095666A1 (en) * 2002-11-20 2004-05-20 International Business Machines Corporation On-drive integrated sector format raid error correction code system and method
CN1881477A (zh) * 2005-06-15 2006-12-20 日立环球储存科技荷兰有限公司 编码数据的错误检测和校正
CN109036493A (zh) * 2018-06-11 2018-12-18 西北工业大学 一种具有检错纠错机制的NAND Flash控制器
CN109308228A (zh) * 2017-07-27 2019-02-05 三星电子株式会社 存储器系统和存储器模块的操作方法以及存储器控制器

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI332611B (en) * 2007-05-24 2010-11-01 Realtek Semiconductor Corp Method for writing data in flash memory and error correction coding/decoding method thereof
US8327242B1 (en) * 2008-04-10 2012-12-04 Apple Inc. High-performance ECC decoder
EP2178215A1 (en) * 2008-10-16 2010-04-21 Thomson Licensing Method for error correction and error detection of modified array codes
CN102339647B (zh) * 2010-07-23 2014-05-14 北京兆易创新科技股份有限公司 一种检错/纠错校验模块的检测方法及装置
CN104750569A (zh) * 2013-12-30 2015-07-01 深圳市中兴微电子技术有限公司 一种实现数据纠错的方法及装置
CN106708655B (zh) * 2017-02-16 2021-07-16 中云信安（深圳）科技有限公司 基于二维纠错码的内存加固方法及电路
CN109979521B (zh) * 2017-12-28 2021-03-02 长鑫存储技术有限公司 检测电路及应用其的存储器
CN108733504B (zh) * 2018-05-04 2021-08-13 西安电子科技大学 一种四维奇偶校验码与汉明码相结合的存储器校验编码及检错纠错方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1242088A (zh) * 1996-10-25 2000-01-19 英特尔公司 利用错误定位码校正一个多级单元存储器的方法和装置
US20040095666A1 (en) * 2002-11-20 2004-05-20 International Business Machines Corporation On-drive integrated sector format raid error correction code system and method
CN1881477A (zh) * 2005-06-15 2006-12-20 日立环球储存科技荷兰有限公司 编码数据的错误检测和校正
CN109308228A (zh) * 2017-07-27 2019-02-05 三星电子株式会社 存储器系统和存储器模块的操作方法以及存储器控制器
CN109036493A (zh) * 2018-06-11 2018-12-18 西北工业大学 一种具有检错纠错机制的NAND Flash控制器

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