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WO2022141681A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2022141681A1
WO2022141681A1 PCT/CN2021/072707 CN2021072707W WO2022141681A1 WO 2022141681 A1 WO2022141681 A1 WO 2022141681A1 CN 2021072707 W CN2021072707 W CN 2021072707W WO 2022141681 A1 WO2022141681 A1 WO 2022141681A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
line
transistor
pixel unit
signal line
Prior art date
Application number
PCT/CN2021/072707
Other languages
English (en)
French (fr)
Inventor
李梅
董甜
王丽
商广良
郑灿
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/621,861 priority Critical patent/US11925082B2/en
Priority to CN202180000040.4A priority patent/CN115244606A/zh
Publication of WO2022141681A1 publication Critical patent/WO2022141681A1/zh
Priority to US18/417,495 priority patent/US20240206256A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • H01L27/124—
    • H01L27/15—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K65/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element and at least one organic radiation-sensitive element, e.g. organic opto-couplers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/033—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures

Definitions

  • At least one embodiment of the present disclosure relates to a display panel and a display device.
  • AMOLED Active-Matrix Organic Light-Emitting Diode
  • At least one embodiment of the present disclosure relates to a display panel and a display device.
  • At least one embodiment of the present disclosure provides a display panel, including: a pixel unit including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the pixel circuit including a first transistor, the pixel unit It includes a first pixel unit and a second pixel unit located in the same row and adjacent columns; a first gate line, connected to the gate of the first transistor of the first pixel unit; a second gate line, connected to the the gate of the first transistor of the second pixel unit is connected; the first gate signal line extends along the first direction, is connected to the first pixel unit, and is configured to provide the first pixel unit with the first gate signal line.
  • a scan signal a second gate signal line, extending along the first direction, connected to the second pixel unit, and configured to provide a second scan signal to the second pixel unit; a first connection line, along the extending in a second direction, the first gate line is connected to the first gate signal line through the first connecting line; and a second connecting line extending along the second direction, the second gate line passing through the The second connection line is connected to the second gate signal line, and the second direction intersects the first direction.
  • the first gate signal line and the second gate signal line are insulated from each other.
  • the first gate line and the second gate line are separated from each other and arranged along the first direction.
  • the second gate signal line is closer to the first gate line than the first gate signal line.
  • the orthographic projection of the first gate signal line and the second gate signal line on the base substrate and the channel region of the first transistor on the base substrate do not overlap.
  • the first gate line, the first connection line, and the first gate signal line are located in three different layers
  • the second gate line, the first gate line, the The two connecting lines and the second gate signal line are located in three different layers.
  • the first gate line and the second gate line are located in the same layer
  • the first connection line and the second connection line are located in the same layer
  • the first The gate signal line and the second gate signal line are located in the same layer.
  • the first gate line and the second gate line are located in a first conductive pattern layer; the first gate signal line and the second gate signal line are located in a second conductive pattern layer. a pattern layer; the first connection lines and the second connection lines are located in a third conductive pattern layer; the first conductive pattern layer is closer to the base substrate than the second conductive pattern layer, the second conductive pattern The layer is closer to the base substrate than the third conductive pattern layer.
  • the display panel further includes a first gate insulating layer, a second gate insulating layer, and an interlayer insulating layer, the first conductive pattern layer is located on the first gate insulating layer, so The second gate insulating layer is provided between the first conductive pattern layer and the second conductive pattern layer, the interlayer insulating layer is located on the second conductive pattern layer, and the third conductive pattern layer is located on the second conductive pattern layer.
  • one end of the first connection line is connected to the first gate line through a first via hole passing through the second gate insulating layer and the interlayer insulating layer, and the first The other end of the connecting line is connected to the first gate signal line through a second via hole penetrating the interlayer insulating layer; one end of the second connecting line passes through the second gate insulating layer and the interlayer
  • the third via hole of the insulating layer is connected to the second gate line, and the other end of the second connection line is connected to the second gate signal line through a fourth via hole penetrating the interlayer insulating layer.
  • the pixel circuit further includes a driving transistor and a second transistor; the gate of the second transistor of the first pixel unit is connected to the first gate line, the The gate of the second transistor of the second pixel unit is connected to the second gate line, the first electrode of the second transistor is connected to the second electrode of the driving transistor, and the second electrode of the second transistor is connected to the second electrode of the driving transistor.
  • the pole is connected to the gate of the driving transistor.
  • the display panel further includes a first power terminal and a data line, wherein the first power terminal is configured to provide a first voltage signal to the pixel circuit, and the data line is is configured to provide a data signal to the pixel circuit;
  • the pixel circuit further includes a storage capacitor; the first pole of the first transistor is connected to the data line, and the first pole of the driving transistor is connected to the first transistor The second pole of the storage capacitor is connected to the gate of the driving transistor, and the second pole of the storage capacitor is connected to the first power supply terminal.
  • the orthographic projection of the first gate signal line and the second gate signal line on the base substrate and the channel region of the second transistor on the base substrate do not overlap.
  • the display panel further includes an initialization signal line configured to provide an initialization signal to the pixel circuit, the pixel circuit further including a first reset transistor; the first reset transistor; The first electrode of a reset transistor is connected to the initialization signal line, and the second electrode of the first reset transistor is connected to the gate of the driving transistor.
  • the first gate signal line and the second gate signal line are located between the second transistor and the first reset transistor.
  • the pixel unit further includes a third pixel unit located in the same column as the first pixel unit, and the data line includes a first data line, a second data line and a third data line A data line, the first data line is connected to the first pixel unit, the second data line is connected to the second pixel unit, and the third data line is connected to the third pixel unit.
  • the pixel unit further includes a fourth pixel unit located in the same column as the second pixel unit, the data line includes a fourth data line, and the fourth data line is the same as the second pixel unit.
  • the fourth pixel unit is connected.
  • the display panel further includes a connection element, the light-emitting element is connected to the pixel circuit through the connection element, and the connection element includes a shielding portion, and the shielding portion extends along the first Extending in two directions; the data line and the shielding portion are located on the same layer, the data line includes two adjacent data lines, the shielding portion is located between the two adjacent data lines, and the first connection
  • the orthographic projection of the line on the base substrate does not overlap with the orthographic projection of the shielding portion on the base substrate.
  • the pixel circuit includes a driving transistor and a second transistor, a first electrode of the second transistor is connected to a second electrode of the driving transistor, and a first electrode of the second transistor is connected to a second electrode of the driving transistor.
  • the diode is connected to the gate of the driving transistor; the display panel further includes a third connection line, and the gate of the driving transistor is connected to the second electrode of the second transistor through the third connection line, so The area of the orthographic projection of the shielding portion on the base substrate is larger than the area of the orthographic projection of the third connection line on the base substrate.
  • the orthographic projection of the gate of the driving transistor on the base substrate partially overlaps the orthographic projection of the shielding portion on the base substrate, the shielding The area of the overlapping portion of the portion and the gate of the driving transistor is smaller than that of the gate of the driving transistor.
  • the size of the gate of the driving transistor in the first direction is larger than the size of the shielding portion in the first direction; the shielding portion is in the first direction.
  • the size in the two directions is larger than the size of the gate of the driving transistor in the second direction.
  • an orthographic projection of the shielding portion on the base substrate intersects an orthographic projection of the first grid line or the second grid line on the base substrate stack.
  • At least one embodiment of the present disclosure further provides a display device including any of the above-mentioned display panels.
  • 1 is a schematic diagram of a 7T1C pixel circuit
  • FIG. 2 is a working timing diagram of the pixel circuit shown in FIG. 1;
  • FIG. 3 is a pixel circuit diagram of a repeating unit of a display panel according to an embodiment of the present disclosure
  • FIG. 4 is a plan view of a semiconductor pattern in a display panel according to an embodiment of the present disclosure.
  • FIG. 5 is a plan view of a first conductive pattern layer in a display panel according to an embodiment of the present disclosure
  • FIG. 6 is a plan view of a second conductive pattern layer in a display panel according to an embodiment of the present disclosure
  • FIG. 7 is a plan view of a third conductive pattern layer in a display panel according to an embodiment of the present disclosure.
  • FIG. 8 is a plan view of a fourth conductive pattern layer in a display panel according to an embodiment of the present disclosure.
  • FIG. 9 is a plan view of a structure of a repeating unit after forming a fourth conductive pattern layer in a display panel according to an embodiment of the present disclosure.
  • FIG. 10 is a plan view of a structure of a pixel unit after forming a fourth conductive pattern layer in a display panel according to an embodiment of the disclosure
  • FIG. 11 is a cross-sectional view along line AB of FIG. 10;
  • FIG. 12 is a plan view of a structure of a pixel unit after forming a light-emitting element in a display panel according to an embodiment of the disclosure.
  • FIG. 13 is a cross-sectional view taken along line CD of FIG. 12 .
  • Dual gate & dual source technical solutions can solve the problem of insufficient compensation time in high frequency display.
  • this solution has problems of pixel layout space limitations and parasitic capacitances between signal lines.
  • the Dual Data solution can achieve 120Hz driving under the premise of ensuring the display effect.
  • FIG. 1 is a schematic diagram of a 7T1C pixel circuit.
  • FIG. 2 is an operation timing diagram of the pixel circuit shown in FIG. 1 .
  • the pixel circuit shown in FIG. 1 may be a pixel circuit of a low temperature polysilicon (Low Temperature Poly-silicon, LTPS) AMOLED common in the related art.
  • LTPS Low Temperature Poly-silicon
  • FIG. 1 shows a pixel circuit of a pixel unit of a display panel.
  • the pixel unit 101 includes a pixel circuit 10 and a light-emitting element 20 .
  • the pixel circuit 10 includes six switching transistors ( T2 - T7 ), one driving transistor T1 and one storage capacitor Cst.
  • the six switching transistors are respectively a data writing transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, and a second reset transistor T7.
  • the light-emitting element 20 includes a first electrode 201 , a second electrode 202 , and a light-emitting functional layer between the first electrode 201 and the second electrode 202 .
  • the first pole 201 is an anode
  • the second pole 202 is a cathode
  • the threshold compensation transistor T3 and the first reset transistor T6 use a dual-gate thin film transistor (Thin Film Transistor, TFT) to reduce leakage.
  • TFT Thin Film Transistor
  • the display panel includes a gate line GT, a data line DT, a first power supply terminal VDD, a second power supply terminal VSS, an emission control signal line EML, an initialization signal line INT, and a reset control signal line RT.
  • the reset control signal line RT includes a first reset control signal line RT1 and a second reset control signal line RT2.
  • the first power supply terminal VDD is configured to provide a constant first voltage signal ELVDD to the pixel unit 101
  • the second power supply terminal VSS is configured to provide a constant second voltage signal ELVSS to the pixel unit 101
  • the first voltage signal ELVDD is greater than the first voltage signal ELVDD.
  • Two voltage signals ELVSS Two voltage signals ELVSS.
  • the gate line GT is configured to provide a scan signal SCAN to the pixel unit 101
  • the data line DT is configured to provide a data signal DATA (data voltage VDATA) to the pixel unit 101
  • the light emission control signal line EML is configured to provide light emission control to the pixel unit 101 signal EM
  • the first reset control signal line RT1 is configured to provide the pixel unit 101 with the reset control signal RESET
  • the second reset control signal line RT2 is configured to provide the pixel unit 101 with the scan signal SCAN
  • the initialization signal line INT is configured to provide the pixel unit 101 with a scan signal SCAN.
  • the pixel unit 101 provides the initialization signal Vinit.
  • the initialization signal Vinit is a constant voltage signal, and its magnitude may be between, but not limited to, the first voltage signal ELVDD and the second voltage signal ELVSS, for example, the initialization signal Vinit may be greater than or equal to the second voltage signal ELVSS .
  • the initialization signal line INT includes a first initialization signal line INT1 and a second initialization signal line INT2.
  • the first initialization signal line INT1 is configured to supply the initialization signal Vinit1 to the pixel unit 101
  • the second initialization signal line INT1 is configured to supply the initialization signal Vinit2 to the pixel unit 101 .
  • the first initialization signal Vinit1 and the second initialization signal Vinit2 are equal, and both are Vinit.
  • the driving transistor T1 is electrically connected to the light-emitting element 20 and outputs a driving current to drive the light-emitting element 20 under the control of the scan signal SCAN, the data signal DATA, the first voltage signal ELVDD, the second voltage signal ELVSS and other signals. glow.
  • the light emitting element 20 is an organic light emitting diode (OLED), and the light emitting element 20 emits red light, green light, blue light, or white light, etc. under the driving of the corresponding pixel circuit 10 .
  • one pixel includes a plurality of pixel units.
  • One pixel may include a plurality of pixel units that emit light of different colors.
  • one pixel includes a pixel unit that emits red light, a pixel unit that emits green light, and a pixel unit that emits blue light, but is not limited thereto.
  • the number of pixel units included in a pixel and the light output of each pixel unit can be determined as required.
  • the gate T20 of the data writing transistor T2 is connected to the gate line GT
  • the first pole T21 of the data writing transistor T2 is connected to the data line DT
  • the second pole T22 of the data writing transistor T2 is connected to the data line DT.
  • the first pole T11 of the driving transistor T1 is connected.
  • the pixel circuit 10 further includes a threshold compensation transistor T3, the gate T30 of the threshold compensation transistor T3 is connected to the gate line GT, and the first electrode T31 of the threshold compensation transistor T3 is connected to the second electrode T12 of the driving transistor T1
  • the second pole T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1.
  • the display panel further includes an emission control signal line EML
  • the pixel circuit 10 further includes a first emission control transistor T4 and a second emission control transistor T5, and the gate T40 of the first emission control transistor T4 is connected to the emission control transistor T4.
  • the signal line EML is connected, the first electrode T41 of the first light-emitting control transistor T4 is connected to the first power supply terminal VDD, the second electrode T42 of the first light-emitting control transistor T4 is connected to the first electrode T11 of the driving transistor T1; the second light-emitting control transistor T4 is connected to the first electrode T11 of the driving transistor T1;
  • the gate T50 of the transistor T5 is connected to the light-emitting control signal line EML, the first electrode T51 of the second light-emitting control transistor T5 is connected to the second electrode T12 of the driving transistor T1, and the second electrode T52 of the second light-emitting control transistor T5 is connected to the light-emitting element.
  • the first pole 201 of 20 is connected.
  • the first reset transistor T6 is connected to the gate T10 of the driving transistor T1, and is configured to reset the gate T10 of the driving transistor T1
  • the second reset transistor T7 is connected to the first electrode 201 of the light-emitting element 20. connected and configured to reset the first pole 201 of the light emitting element 20 .
  • the first initialization signal line INT1 is connected to the gate of the driving transistor T1 through the first reset transistor T6.
  • the second initialization signal line INT2 is connected to the first electrode 201 of the light emitting element 20 through the second reset transistor T7.
  • first initialization signal line INT1 and the second initialization signal line INT2 are connected to receive the same initialization signal, but not limited thereto, in some embodiments, the first initialization signal line INT1 and the second initialization signal line INT2 are also can be isolated from each other and configured to input signals separately.
  • the first electrode T61 of the first reset transistor T6 is connected to the first initialization signal line INT1
  • the second electrode T62 of the first reset transistor T6 is connected to the gate T10 of the driving transistor T1
  • the second reset transistor T6 is connected to the gate T10 of the driving transistor T1.
  • the first electrode T71 of the transistor T7 is connected to the second initialization signal line INT2
  • the second electrode T72 of the second reset transistor T7 is connected to the first electrode 201 of the light emitting element 20 .
  • the gate T60 of the first reset transistor T6 is connected to the first reset control signal line RT1
  • the gate T70 of the second reset transistor T7 is connected to the second reset control signal line RT2.
  • the first power supply terminal VDD is configured to provide a first voltage signal ELVDD to the pixel circuit 10; the pixel circuit further includes a storage capacitor Cst, and the first electrode Ca of the storage capacitor Cst is connected to the gate T10 of the driving transistor T1 , the second pole Cb of the storage capacitor Cst is connected to the first power supply terminal VDD.
  • the display panel further includes a second power supply terminal VSS, and the second power supply terminal VSS is connected to the second pole 201 of the light-emitting element 20 .
  • the driving method of the pixel unit includes a first reset phase t1, data writing and threshold compensation, a second reset phase t2, and a light-emitting phase t3.
  • the reset control signal RESET is at a low level , resets the gate of the driving transistor T1, and resets the first electrode 201 (eg, anode) of the light-emitting element 20 when the scan signal SCAN is at a low level.
  • the first electrode 201 eg, anode
  • the storage capacitor is used to hold the voltage signal, so that the potential of the signal holding terminal can be kept constant, and a voltage difference is formed between the gate and the source of the driving transistor, so as to control the driving transistor A drive current is formed, and the light-emitting element 20 is driven to emit light.
  • the light emission control signal EM is set as the off voltage
  • the reset control signal RESET is set as the on voltage
  • the scan signal SCAN is set as the off voltage.
  • the light emission control signal EM is set as the off voltage
  • the reset control signal RESET is set as the off voltage
  • the scan signal SCAN is set as the on voltage.
  • the light-emitting control signal EM is set as the turn-on voltage
  • the reset control signal RESET is set as the turn-off voltage
  • the scan signal SCAN is set as the turn-off voltage.
  • the first voltage signal ELVDD and the second voltage signal ELVSS are both constant voltage signals, for example, the initialization signal Vinit is between the first voltage signal ELVDD and the second voltage signal ELVSS.
  • the turn-on voltage in the embodiments of the present disclosure refers to a voltage that can turn on the first and second electrodes of the corresponding transistor
  • the turn-off voltage refers to a voltage that can turn off the first and second electrodes of the corresponding transistor.
  • the turn-on voltage is a low voltage (eg, 0V)
  • the turn-off voltage is a high voltage (eg, 5V)
  • the turn-on voltage is a high voltage (eg, 5V)
  • the turn-off voltage is high.
  • the voltage is a low voltage (eg, 0V).
  • the driving waveforms shown in FIG. 2 are all described by taking a P-type transistor as an example.
  • the turn-on voltage is a low voltage (eg, 0V)
  • the turn-off voltage is a high voltage (eg, 5V), but not limited thereto.
  • the first reset transistor T6 transmits the first initialization signal (initialization voltage Vinit) Vinit1 to the gate of the drive transistor T1 and is stored by the storage capacitor Cst, resets the drive transistor T1 and erases the data stored in the last (last frame) light emission .
  • the light emission control signal EM is the off voltage
  • the reset control signal RESET is the off voltage
  • the scan signal SCAN is the on voltage.
  • the data writing transistor T2 and the threshold compensation transistor T3 are in the conducting state
  • the second reset transistor T7 is in the conducting state
  • the second reset transistor T7 transmits the second initialization signal (initialization voltage Vinit) Vinit2 to the light-emitting element 20
  • the first electrode 201 to reset the light-emitting element 20 .
  • the first light-emitting control transistor T4, the second light-emitting control transistor T5, and the first reset transistor T6 are in an off state.
  • the data writing transistor T2 transmits the data voltage VDATA to the first pole of the driving transistor T1, that is, the data writing transistor T2 receives the scan signal SCAN and the data voltage VDATA and transmits the data voltage VDATA to the first pole of the driving transistor T1 according to the scan signal SCAN Write data voltage VDATA.
  • the threshold compensation transistor T3 is turned on to connect the driving transistor T1 into a diode structure, thereby charging the gate of the driving transistor T1.
  • the gate voltage of the driving transistor T1 is VDATA+Vth, where VDATA is the data voltage, and Vth is the threshold voltage of the driving transistor T1, that is, the threshold compensation transistor T3 receives the scan signal SCAN and adjusts the driving transistor according to the scan signal SCAN.
  • the gate voltage of T1 performs threshold voltage compensation. At this stage, the voltage difference across the storage capacitor Cst is ELVDD-VDATA-Vth.
  • the light-emitting control signal EM is the turn-on voltage
  • the reset control signal RESET is the turn-off voltage
  • the scan signal SCAN is the turn-off voltage.
  • the first light emission control transistor T4 and the second light emission control transistor T5 are in an on state
  • the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6 and the second reset transistor T7 are in an off state.
  • the first voltage signal ELVDD is transmitted to the first pole of the driving transistor T1 through the first light-emitting control transistor T4, the gate voltage of the driving transistor T1 is kept as VDATA+Vth, and the light-emitting current I passes through the first light-emitting control transistor T4, the driving transistor T1 and the
  • the second light emission control transistor T5 flows into the light emitting element 20, and the light emitting element 20 emits light. That is, the first light emission control transistor T4 and the second light emission control transistor T5 receive the light emission control signal EM, and control the light emitting element 20 to emit light according to the light emission control signal EM.
  • the luminous current I satisfies the following saturation current formula:
  • ⁇ n is the channel mobility of the driving transistor
  • Cox is the channel capacitance per unit area of the driving transistor T1
  • W and L are the channel width and channel length of the driving transistor T1, respectively
  • Vgs is the gate and source of the driving transistor T1 The voltage difference between the poles (that is, the first pole of the driving transistor T1 in this embodiment).
  • the pixel circuit of the present invention compensates the threshold voltage of the driving transistor T1 very well.
  • the ratio of the duration of the light-emitting stage t3 to the display period of one frame can be adjusted.
  • the light-emitting brightness can be controlled by adjusting the ratio of the duration of the light-emitting stage t3 to the display time period of one frame.
  • adjusting the ratio of the duration of the light-emitting phase t3 to the display duration of one frame is achieved by controlling the scan driving circuit in the display panel or an additionally provided driving circuit.
  • the embodiment of the present disclosure is not limited to the specific pixel circuit shown in FIG. 1 , and other pixel circuits that can realize compensation for the driving transistor may be used. Based on the description and teaching of the present disclosure, other arrangements that can be easily conceived by those of ordinary skill in the art without creative efforts fall within the protection scope of the present disclosure.
  • FIG. 3 is a pixel circuit diagram of a repeating unit of a display panel according to an embodiment of the present disclosure.
  • the display panel includes a first pixel unit 101a, a second pixel unit 101b, a third pixel unit 101c, and a fourth pixel unit 101d, and the first pixel unit 101a, the second pixel unit 101b, the third pixel unit 101c and the fourth pixel unit 101d constitute a repeating unit RP.
  • a plurality of repeating units RP can form an array.
  • the repeating unit RP is one smallest repeating unit of the display array.
  • the display panel is driven by double gates and double data lines, so that the first pixel unit 101a, the second pixel unit 101b, the third pixel unit 101c, and the fourth pixel unit 101d can be independently controlled respectively.
  • the first pixel unit 101a, the second pixel unit 101b, the third pixel unit 101c and the fourth pixel unit 101d are respectively lit up in sequence.
  • the gate line of the first pixel unit 101a can be continuously turned on The writing of the data signal to the fourth pixel unit 101d is completed, and the same is true for other pixel units, so that each pixel unit can have sufficient compensation time.
  • the first pixel unit 101a and the second pixel unit 101b are located in the same row and in adjacent columns, and the third pixel unit 101c and the fourth pixel unit 101d are located in the same row and in adjacent columns.
  • the first pixel unit 101a and the third pixel unit 101c are located in the same column and in adjacent rows, and the second pixel unit 101b and the fourth pixel unit 101d are located in the same column and in adjacent rows.
  • FIG. 3 shows the first data line DT1, the second data line DT2, the third data line DT3 and the fourth data line DT4.
  • the first data line DT1 is connected to the first pixel unit 101a
  • the second data line DT2 is connected to the second pixel unit 101b
  • the third data line DT3 is connected to the third pixel unit 101c
  • the fourth data line DT4 is connected to the third pixel unit 101c.
  • the four-pixel unit 101d is connected.
  • the first reset transistor T6 and the second reset transistor T7 are connected to the same reset control signal line RT to be inputted with the same reset control signal at the same time, but the implementation of the present disclosure The example is not limited to this.
  • the first reset transistor T6 and the second reset transistor T7 may also be connected to the first reset control signal line and the second reset control signal line, respectively, and the first reset control signal line and the second reset control signal lines are insulated from each other to be input signals, respectively.
  • signals are input to the first reset transistor T6 and the second reset transistor T7 at different times.
  • the first reset transistor T6 is input with the reset control signal RESET in the first reset phase t1
  • the second reset transistor T7 is input with the reset control signal RESET.
  • T7 is input with the scan signal SCAN during data writing and threshold compensation and the second reset phase t2.
  • the gate line GT of the present stage is connected to the reset control signal line of the next stage.
  • the gate line GT and the second reset control signal line RT2 may be electrically connected to input the same signal at the same time.
  • FIG. 4 is a plan view of a semiconductor pattern in a display panel according to an embodiment of the present disclosure.
  • 5 is a plan view of a first conductive pattern layer in a display panel according to an embodiment of the present disclosure.
  • 6 is a plan view of a second conductive pattern layer in a display panel according to an embodiment of the present disclosure.
  • 7 is a plan view of a third conductive pattern layer in a display panel according to an embodiment of the present disclosure.
  • 8 is a plan view of a fourth conductive pattern layer in a display panel according to an embodiment of the present disclosure.
  • FIG. 9 is a plan view of a structure of a repeating unit after forming a fourth conductive pattern layer in a display panel according to an embodiment of the present disclosure.
  • FIG. 10 is a plan view of a structure of a pixel unit after forming a fourth conductive pattern layer in a display panel according to an embodiment of the disclosure.
  • FIG. 11 is a cross-sectional view taken along line AB of FIG. 10 .
  • FIG. 12 is a plan view of a structure of a pixel unit after forming a light-emitting element in a display panel according to an embodiment of the disclosure.
  • FIG. 13 is a cross-sectional view taken along line CD in FIG. 12 .
  • first direction X is perpendicular to the second direction Y as an example.
  • first direction X is the row direction of the pixel unit
  • second direction Y is the column direction of the pixel unit.
  • Both the first direction X and the second direction Y are directions parallel to the base substrate BS.
  • 11 and 13 show a third direction Z, which is a direction perpendicular to the base substrate BS.
  • the third direction Z is perpendicular to the first direction X and is perpendicular to the second direction Y.
  • the insulating layer is shown in the form of via holes, the insulating layer itself is treated with transparency, and the first conductive pattern layer, the second conductive pattern layer, the third The conductive pattern layer and the fourth conductive pattern layer are translucent.
  • FIG. 4 shows the semiconductor pattern SCP
  • FIG. 5 shows the first conductive pattern layer LY1, for example, a first gate insulating layer (the first gate insulating layer GI1, Refer to Figure 11).
  • a semiconductor pattern SCP and subsequent various components are formed on a base substrate.
  • the first conductive pattern layer LY1 includes a first reset control signal line RT1 , a first gate line GT1 , a second gate line GT2 , and the first electrode Ca of the storage capacitor Cst (the gate T10 of the driving transistor T1 ) , a light emission control signal line EML, and a second reset control signal line RT2.
  • the semiconductor pattern SCP is doped with the first conductive pattern layer LY1 as a mask, so that the area of the semiconductor pattern SCP covered by the first conductive pattern layer LY1 retains semiconductor characteristics, forming an active layer ACT (see FIG. 10 ), and the semiconductor pattern SCP is formed.
  • the regions of the pattern SCP that are not covered by the first conductive pattern layer LY1 are conductorized to form the source and drain electrodes of the thin film transistor. 10 shows the active layer ACT formed after the semiconductor pattern SCP is partially conductorized.
  • a self-alignment process is used to conduct conductorization treatment on the semiconductor pattern layer SCP using the first conductive pattern layer LY1 as a mask.
  • the semiconductor pattern layer SCP is redoped by an ion implantation process.
  • the part of the semiconductor pattern layer SCP not covered by the first conductive pattern layer LY1 is conductive, forming the source region (first electrode T11) and the drain region (second electrode T12) of the driving transistor T1, the data The source region (first electrode T21) and the drain region (second electrode T22) of the write transistor T2, the source region (first electrode T31) and the drain region (second electrode T32) of the threshold compensation transistor T3, The source region (first electrode T41) and the drain region (second electrode T42) of the first light emission control transistor T4, the source region (first electrode T51) and the drain region (second electrode T51) of the second light emission control transistor T5 electrode T52), the source region (first electrode T61) and the drain region (second electrode T62) of the first reset transistor T6, and the source region (first electrode T71) and drain region of the second reset transistor T7 (Second pole T72).
  • the part of the semiconductor pattern layer SCP covered by the first conductive pattern layer L1 retains semiconductor characteristics, forming the channel region of the driving transistor T1, the channel region of the data writing transistor T2, the channel region of the threshold compensation transistor T3, the first light emitting The channel region of the control transistor T4, the channel region of the second light emission control transistor T5, the channel region of the first reset transistor T6, and the channel region of the second reset transistor T7.
  • the channel region of each transistor constitutes the active layer ACT (refer to FIG. 10 ).
  • the second pole T72 of the second reset transistor T7 and the second pole T52 of the second light emitting control transistor T5 are integrally formed; the first pole of the second light emitting control transistor T5 T51, the second pole T12 of the driving transistor T1 and the first pole T31 of the threshold compensation transistor T3 are integrally formed; the first pole T11 of the driving transistor T1, the second pole T22 of the data writing transistor T2, and the first pole T22 of the first light-emitting control transistor T4
  • the second pole T42 is formed integrally; the second pole T32 of the threshold compensation transistor T3 and the second pole T62 of the first reset transistor T6 are formed integrally.
  • the channel region (active layer) of the transistor used in the embodiments of the present disclosure may be single crystal silicon, polysilicon (eg, low temperature polysilicon) or metal oxide semiconductor material (eg IGZO, AZO, etc.).
  • the transistors are all P-type low temperature polysilicon (LTPS) thin film transistors.
  • the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are metal-oxide-semiconductor thin-film transistors, that is, the channel material of the transistors is a metal-oxide-semiconductor material (such as IGZO , AZO, etc.), the metal oxide semiconductor thin film transistor has a lower leakage current, which can help reduce the gate leakage current of the driving transistor T1.
  • the LTPO Low Temperature Polycrystalline Oxide, LTPO
  • the LTPO process combines the advantages of low temperature polysilicon (Low Tempreture Poly-Silicon, LTPS) and oxide (Oxide). That is, two TFT devices of low temperature polysilicon (LTPS) and oxide (Oxide) are integrated in the same pixel unit.
  • the transistors employed in the embodiments of the present disclosure may include various structures, such as a top-gate type, a bottom-gate type, or a double-gate structure.
  • the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are dual-gate thin film transistors, which can help reduce the gate leakage current of the driving transistor T1.
  • a part of the light emission control signal line EML serves as the gate T40 of the first light emission control transistor T4
  • a part of the light emission control signal line EML serves as the gate of the second light emission control transistor T5 T50
  • the gate T60 of the first reset transistor T6 is a part of the first reset control signal line RT1
  • the gate T70 of the second reset transistor T7 is a part of the second reset control signal line RT2
  • data is written to the gate of the transistor T2 T20 is a part of the gate line GT
  • the gate T30 of the threshold compensation transistor T3 is a part of the gate line GT.
  • the gate line GT is the first gate line GT1 or the second gate line GT2.
  • the first reset control signal line RT1 , the first gate line GT1 , the second gate line GT2 , the light emission control signal line EML and the second reset control signal line RT2 all extend along the first direction X.
  • the data line DT extends along the second direction Y, and the first data line DT1 , the third data line DT3 , the fourth data line DT4 and the second data line DT2 extend along the first direction X arrangement.
  • FIG. 6 shows the second conductive pattern layer LY2.
  • a second gate insulating layer (the second gate insulating layer GI2 , see FIG. 11 ) is provided between the second conductive pattern layer LY2 and the first conductive pattern layer LY1 .
  • the second conductive pattern layer LY2 includes a stopper BK, a first initialization signal line INT1, a second initialization signal line INT2, a second electrode Cb of the storage capacitor Cst, a first gate signal line SL1 and a second gate signal line SL2.
  • the first gate signal line SL1 extends along the first direction X
  • the second gate signal line SL2 extends along the first direction X.
  • the first initialization signal line INT1 extends along the first direction X
  • the second initialization signal line INT2 extends along the first direction X
  • the first initialization signal line INT1, the first gate signal line SL1, the second gate signal line SL2, and the second initialization signal line INT2 are arranged along the second direction Y.
  • the first gate signal line SL1 and the second gate signal line SL2 are located between the first initialization signal line INT1 and the second pole Cb of the storage capacitor Cst. As shown in FIG.
  • the first initialization signal line INT1 and the second initialization signal line INT2 are located on both sides of the second pole Cb of the storage capacitor Cst, and the first initialization signal line INT1 and the second initialization signal line INT2 are located on the side of the stopper BK.
  • the first gate signal line SL1, the second gate signal line SL2, the second pole Cb of the storage capacitor Cst and the block BK are arranged between the first initialization signal line INT1 and the second initialization signal line INT2. As shown in FIG.
  • the first initialization signal line INT1, the first gate signal line SL1, the second gate signal line SL2, the stopper BK, the second pole Cb of the storage capacitor Cst, and the second initialization signal line INT2 are along the second direction Y is arranged in order.
  • the third conductive pattern layer LY3 includes a power supply connection line VDD0, a first connection electrode CEa, a second connection electrode CEb, a third connection electrode CEc, a fourth connection electrode CEd, a fifth connection electrode CEe, and a first connection electrode CEb.
  • An interlayer insulating layer (interlayer insulating layer ILD, see FIG. 11 ) is provided between the third conductive pattern layer LY3 and the second conductive pattern layer LY2 .
  • the power supply connection line VDD0 is electrically connected to the first electrode T41 of the first light-emitting control transistor T4 through the via hole H2
  • the power supply connection line VDD0 is electrically connected to the storage capacitor Cst through the via holes H3 and H30
  • the second pole Cb is electrically connected
  • the power connection line VDD0 is electrically connected to the conductive block BK through the via hole H0.
  • One end of the first connection electrode CEa is electrically connected to the first initialization signal line INT1 through the via hole H12, and the other end of the first connection electrode CEa is connected to the first electrode T61 of the first reset transistor T6 through the via hole H11, so that the first The first pole T61 of the reset transistor T6 is electrically connected to the first initialization signal line INT1.
  • One end of the second connection electrode CEb is electrically connected to the second electrode T62 of the first reset transistor T6 through the via hole H22, and the other end of the second connection electrode CEb is electrically connected to the gate T10 (that is, the storage capacitor) of the driving transistor T1 through the via hole H21.
  • the first electrode Ca) of Cst is electrically connected, so that the second electrode T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1 (ie, the first electrode Ca of the storage capacitor Cst).
  • One end of the third connection electrode CEc is electrically connected to the second initialization signal line INT2 through the via hole H32, and the other end of the third connection electrode CEc is connected to the first electrode T71 of the second reset transistor T7 through the via hole H31, so that the second The first electrode T71 of the reset transistor T7 is electrically connected to the second initialization signal line INT2.
  • the fourth connection electrode CEd is electrically connected to the second electrode T52 of the second light-emitting control transistor T5 through the via hole H40.
  • the fourth connection electrode CEd can be used to connect to the sixth connection electrode CEf formed later, and then to be electrically connected to the first electrode 201 (refer to FIG. 9 ) of the light-emitting element 20 .
  • the fifth connection electrode CEe is electrically connected to the first electrode T21 of the data writing transistor T2 through the via hole H5.
  • the fifth connection electrode CEe is used for connecting with the data line.
  • FIG. 8 shows the fourth conductive pattern layer LY4.
  • the fourth conductive pattern layer LY4 includes a data line DT, a sixth connection electrode CEf, and a first power supply line VDD1.
  • a passivation layer (passivation layer PVX, see FIG. 11 ) and a first planarization layer (first planarization layer PLN1 , see FIG. 11 ) are provided between the third conductive pattern layer LY3 and the fourth conductive pattern layer LY4 .
  • the first power supply line VDD1 is connected to the power supply connection line VDD0 through the via hole H6 passing through the passivation layer and the first planarization layer
  • the sixth connection electrode CEf is connected to the fourth power supply line VDD0 through the via hole H7 passing through the passivation layer and the first planarization layer.
  • the connecting electrodes CEd are connected.
  • the data line DT is connected to the fifth connection electrode CEe through the via hole H8, and is further electrically connected to the first electrode T21 of the data writing transistor T2.
  • the sixth connection electrode CEf (connection electrode CEf) and the fourth connection electrode CEd (connection electrode CEd) constitute the connection element CE0.
  • the light-emitting element 20 is connected to the pixel circuit 10 through the connection element CE0.
  • the pixel circuit 10 is connected to the fourth connection electrode CEd (connection electrode CEd), the fourth connection electrode CEd (connection electrode CEd) is connected to the sixth connection electrode CEf (connection electrode CEf), and the sixth connection electrode CEf (connection electrode CEf) ) is connected to the light-emitting element 20.
  • FIG. 8 shows the first data line DT1, the second data line DT2, the third data line DT3 and the fourth data line DT4.
  • FIG. 8 also shows the positions of the first pixel unit 101a, the second pixel unit 101b, the third pixel unit 101c and the fourth pixel unit 101d.
  • the first data line DT1 is connected to the fifth connection electrode CEe at the corresponding position through the via hole H81
  • the second data line DT2 is connected to the fifth connection electrode CEe at the corresponding position through the via hole H82
  • the third data line DT2 is connected to the fifth connection electrode CEe at the corresponding position through the via hole H82.
  • the data line DT3 is connected to the fifth connection electrode CEe at the corresponding position through the via hole H83
  • the fourth data line DT4 is connected to the fifth connection electrode CEe at the corresponding position through the via hole H84.
  • the orthographic projection of the first gate signal line SL1 and the second gate signal line SL2 on the substrate and data writing do not overlap.
  • the orthographic projection of the first gate signal line SL1 and the second gate signal line SL2 on the substrate is the same as that of the threshold compensation transistor.
  • the orthographic projections of the channel region T33 on the base substrate do not overlap.
  • the data line DT extends along the second direction Y, and the first data line DT1 , the third data line DT3 , the fourth data line DT4 and the second data line DT2 are arranged along the first direction X.
  • the first power supply line VDD1 is configured to supply the first voltage signal ELVDD to the pixel circuit 10 .
  • the first power line VDD1 is connected to the stopper BK to supply a constant voltage to the stopper BK.
  • the first power supply line VDD1 is connected to the first power supply terminal VDD, and the second pole Cb of the storage capacitor Cst is connected to the first power supply line VDD1.
  • the second pole Cb of the storage capacitor Cst is connected to the first power supply terminal VDD through the power supply connection line VDD0 and the first power supply line VDD1.
  • FIG. 9 shows a plan view of the structure after forming the fourth conductive pattern layer LY4.
  • the first pole T41 of the first light emission control transistor T4 is connected to the first power supply terminal VDD through the power supply connection line VDD0 and the first power supply line VDD1 (refer to FIGS. 9 and 10 ).
  • the threshold compensation transistor T3 is a dual-gate transistor, and the threshold compensation transistor T3 includes a first channel T331 and a second channel T332, and the first channel T331 and the second channel T332 pass through the first conductive connection part CP1 connected.
  • the first reset transistor T6 is a double-gate transistor, the first reset transistor T6 includes a first channel T631 and a second channel T632, and the first channel T631 and the second channel T632 are connected by a second conductive connection connected to CP2.
  • the stopper BK is configured to block the first conductive connection part CP1 between the two channels of the threshold compensation transistor T3, and the stopper BK and the first conductive connection part CP1 form a capacitance (stabilizing capacitance) to The leakage current of the threshold compensation transistor T3 is avoided to avoid affecting the display effect.
  • the stopper BK and the first conductive connection portion CP1 partially overlap.
  • the first initialization signal line INT1 and the second conductive connection portion CP2 partially overlap, and a capacitance (stable capacitance) is formed between the first initialization signal line INT1 and the second conductive connection portion CP2 to The leakage current of the first reset transistor T6 is avoided, and the display effect is avoided.
  • the first gate line GT1 is connected to the gate of the data writing transistor T2 of the first pixel unit 101a; the second gate line GT2 is connected to the gate of the data writing transistor T2 of the second pixel unit 101b .
  • the first gate signal line SL1 extends along the first direction X, is connected to the first pixel unit 101a, and is configured to provide the first scan signal to the first pixel unit 101a;
  • the second gate signal line SL2 It extends along the first direction X, is connected to the second pixel unit 101b, and is configured to provide a second scan signal to the second pixel unit 101b.
  • the first connection line CL1 extends along the second direction Y, the first gate line GT1 is connected to the first gate signal line SL1 through the first connection line CL1; the second connection line CL2 extends along the second direction Y , the second gate line GT2 is connected to the second gate signal line SL2 through the second connecting line CL2.
  • the display panel provided by the embodiments of the present disclosure can realize the Dual gate&Dual source technical solution under high resolution.
  • the lateral wiring of the Dual gate signal is realized through the second conductive pattern layer, and the connection lines in the third conductive pattern layer are respectively connected to the gate lines and the first conductive pattern layer through the via holes.
  • the gate signal lines in the two conductive pattern layers have a compact pixel layout, which is conducive to realizing high PPI.
  • the application of the Dual source&Dual gate technical solution at a high resolution of 413PPI is implemented.
  • the first gate signal line SL1 and the second gate signal line SL2 are insulated from each other, so that scan signals can be respectively input to two adjacent columns of pixel units in the same row of pixel units.
  • the first gate signal line SL1 is used to input the scan signal to the pixel units of odd columns
  • the second gate signal line SL2 is used to input the scan signal to the pixel units of even columns.
  • the first gate line GT1 and the second gate line GT2 are separated from each other and arranged in the first direction X.
  • a second gate line GT2 is provided between two adjacent first gate lines GT1
  • a first gate line GT1 is provided between two adjacent second gate lines GT2.
  • the first gate line GT1 extends along the first direction X
  • the second gate line GT2 extends along the first direction X.
  • the extension of a component in a certain direction refers to the overall extension trend of the component, not necessarily that every part of the component extends along the extension direction.
  • the second gate signal line SL2 is closer to the first gate line GT1 than the first gate signal line SL1 , and the length of the first connection line CL1 along the second direction Y is greater than that of the second connection line CL2 Length along the second direction Y.
  • the first gate line GT1 , the first connection line CL1 , and the first gate signal line SL1 are located in three different layers
  • the second gate line GT2 , the second connection line The line CL2 and the second gate signal line SL2 are located in three different layers.
  • the first gate line GT1 and the second gate line GT2 are located in the same layer
  • the first connection line CL1 and the second connection line CL2 are located in the same layer
  • the first gate signal The line SL1 and the second gate signal line SL2 are located on the same layer.
  • the first gate line GT1 and the second gate line GT2 are located in the first conductive pattern layer LY1 ; the first gate signal line SL1 and the second gate line SL1
  • the signal line SL2 is located in the second conductive pattern layer LY2; the first connection line CL1 and the second connection line CL2 are located in the third conductive pattern layer LY3; the first conductive pattern layer LY1 is closer to the base substrate BS than the second conductive pattern layer LY2,
  • the second conductive pattern layer LY2 is closer to the base substrate BS than the third conductive pattern layer LY3.
  • the display panel further includes a first gate insulating layer GI1, a second gate insulating layer GI2 and an interlayer insulating layer ILD; the first conductive pattern layer LY1 is located on the first gate insulating layer GI1, and the first A second gate insulating layer GI2 is disposed between the conductive pattern layer LY1 and the second conductive pattern layer LY2, the interlayer insulating layer ILD is located on the second conductive pattern layer LY2, and the third conductive pattern layer LY3 is located on the interlayer insulating layer ILD.
  • one end of the first connection line CL1 is connected to the first gate line GT1 through a first via V1 penetrating the second gate insulating layer GI2 and the interlayer insulating layer ILD, and the first connection line CL1 The other end is connected to the first gate signal line SL1 through the second via hole V2 penetrating the interlayer insulating layer ILD; one end of the second connection line CL2 is connected to the third via hole penetrating the second gate insulating layer GI2 and the interlayer insulating layer ILD V3 is connected to the second gate line GT2, and the other end of the second connection line CL2 is connected to the second gate signal line SL2 through a fourth via hole V4 penetrating the interlayer insulating layer ILD.
  • the gate of the threshold compensation transistor T3 of the first pixel unit 101a is connected to the first gate line GT1
  • the gate of the threshold compensation transistor T3 of the second pixel unit 101b is connected to the second gate line GT2
  • the first electrode of the threshold compensation transistor T3 is connected to the second electrode of the driving transistor T1
  • the second electrode of the threshold compensation transistor T3 is connected to the gate of the driving transistor T1.
  • the first gate signal line SL1 and the second gate signal line SL2 are located between the threshold compensation transistor T3 and the first reset transistor T6, so that the first gate signal line SL1 and the second gate signal line SL2 are located between the threshold compensation transistor T3 and the first reset transistor T6.
  • the position in the second direction is defined.
  • the length of the sixth connection electrode CEf in the second direction Y is larger than that of a normal connection electrode. As shown in FIG. 8 , the length of the sixth connection electrode CEf in the second direction Y is greater than the length of the sixth connection electrode CEf in the first direction X. For example, the length of the sixth connection electrode CEf in the second direction Y is greater than 2-5 times the maximum length of the sixth connection electrode CEf in the first direction X. In some embodiments, the sixth connection electrode CEf is in the second direction The length in the direction Y is greater than 3 times, 4 times or 5 times the maximum length of the sixth connection electrode CEf in the first direction X.
  • the sixth connection electrode CEf shown in FIG. 8 may be referred to as a shield portion CEs.
  • the shield portion CEs and the fourth connection electrode CEd (connection electrode CEd) constitute the connection element CE0.
  • one end of the second connection electrode CEb is electrically connected to the gate T10 of the driving transistor T1 (ie, the first electrode Ca of the storage capacitor Cst) through the via hole H21 , and the second connection electrode CEb The other end is electrically connected to the second electrode T62 of the first reset transistor T6 through the via hole H22, and the second connection electrode CEb may also be referred to as the third connection line CL3.
  • the gate T10 of the driving transistor T1 is connected to the second electrode T32 of the threshold compensation transistor T3 through the third connection line CL3.
  • the shielding portions CEs extend in the second direction Y.
  • the light emitting element 20 is connected to the pixel circuit 10 through the connection element CE0 (including the fourth connection electrode CEd and the shielding portion CEs).
  • the data lines DT and the shielding parts CEs are located in the same layer, and both the data lines DT and the shielding parts CEs are located in the fourth conductive pattern layer LY4.
  • the data line DT includes two adjacent data lines DT, the shielding portion CEs is located between the two adjacent data lines DT, and the orthographic projection of the shielding portion CEs on the base substrate BS and the third connection line CL3 are on the base substrate BS The orthographic projections of at least partially overlap.
  • the data line DT includes a first data line DT1 and a third data line DT3, the first data line DT1 and the third data line DT3 are adjacent, and in the first direction X, the shielding portion CEs is located in the first between the data line DT1 and the third data line DT3.
  • the fact that part A and part B are adjacent means that part A and part B do not have part A or part B between them.
  • the shielding portion CEs extends along the second direction and is inserted between two adjacent data lines DT, and the shielding effect is more obvious at a position where the adjacent data lines are closer.
  • the orthographic projection of the third connection line CL3 on the base substrate BS completely falls within the orthographic projection of the shielding portion CEs on the base substrate BS.
  • the orthographic projection of the first connection line CL1 on the base substrate BS does not overlap with the orthographic projection of the shielding portions CEs on the base substrate BS.
  • the orthographic projection of the second connection line CL2 on the base substrate BS does not overlap with the orthographic projection of the shielding portions CEs on the base substrate BS.
  • the display panel includes a first conductive structure CDT1 , and the first conductive structure CDT1 is connected to the gate T10 of the driving transistor T1 .
  • the material of the first conductive structure CDT1 is the same as the material of the first conductive connection portion CP1.
  • the first conductive structure CDT1 and the first conductive connection portion CP1 can be fabricated from the same film layer through the same process.
  • the material of the first conductive structure CDT1 includes a conductive material obtained by doping a semiconductor material.
  • the material of the first conductive structure CDT1 includes, but is not limited to, a conductive material obtained by doping polysilicon.
  • the first conductive structure CDT1 is multiplexed as the second electrode T62 of the first reset transistor T6.
  • the first conductive structure CDT1 is used as an example of the second electrode T62 of the first reset transistor T6 for description.
  • the first conductive structure CDT1 , the third connection line CL3 and the gate T10 of the driving transistor T1 constitute the gate signal portion PT1 of the driving transistor T1 .
  • the orthographic projection of the shielding portion CEs on the base substrate BS and the orthographic projection of the gate signal portion PT1 on the base substrate BS at least partially overlap, so that the shielding portion CEs shields the gate signal portion PT1 from the data Parasitic capacitance between lines, alleviating longitudinal crosstalk problems.
  • the orthographic projection of the shielding portion CEs on the base substrate BS and the orthographic projection of the third connection line CL3 on the base substrate BS at least partially overlap, so that the shielding portion CEs shields the gate signal portion PT1 ( The parasitic capacitance between the gate point) and the data line reduces the vertical crosstalk problem.
  • the 120Hz driving scheme adopts the time-sharing writing method, that is, the data signal is first stored in the storage capacitor, and then the scanning signal is turned on and then written into the pixel unit.
  • the interference between the data signals will affect the accurate writing of the data signal. affect the display effect.
  • the shielding portion CEs is located between two adjacent data lines DT, and the orthographic projection of the third connection line CL3 on the base substrate BS and the orthographic projection of the shielding portion CEs on the base substrate BS are at least at least Partial overlap can reduce the coupling effect and improve this problem.
  • the orthographic projection of the shielding portion CEs on the base substrate BS is larger than the orthographic projection of the third connection line CL3 on the base substrate BS.
  • the area of the orthographic projection of the shielding portions CEs on the base substrate BS is larger than the area of the orthographic projection of the third connection line CL3 on the base substrate BS.
  • the orthographic projection of the shielding portion CEs on the base substrate BS covers the orthographic projection of the third connection line CL3 on the base substrate BS.
  • the shield portion CEs covers the third connection line CL3.
  • the main surface of the base substrate BS is a surface for producing the respective components, and the respective components are provided on the main surface of the base substrate BS.
  • the orthographic projection of the gate T10 of the driving transistor T1 on the base substrate BS partially overlaps the orthographic projection of the shielding portion CEs on the base substrate BS, and the shielding portion CEs and the driving transistor
  • the area of the overlapping portion of the gate electrode T10 of T1 is smaller than that of the gate electrode T10 of the driving transistor T1.
  • the size of the gate T10 of the driving transistor T1 in the first direction X is larger than the size of the shielding portion CEs in the first direction X; the shielding portion CEs is in the second direction X.
  • the dimension in the direction Y is larger than the dimension in the second direction Y of the gate of the driving transistor T1 .
  • the gate T10 of the driving transistor T1 protrudes from the shielding portions CEs from both sides in the first direction X, respectively.
  • the gate line GT may include a first gate line GT1 or a second gate line GT2.
  • the orthographic projection of the first grid line GT1 or the second grid line GT2 on the base substrate BS partially overlaps the orthographic projection of the shielding portions CEs on the base substrate BS.
  • the pixel unit includes two adjacent pixel units located in the same column, and the two adjacent data lines DT are respectively connected to the two pixel units.
  • FIG. 9 shows the positions of the first pixel unit 101a, the second pixel unit 101b, the third pixel unit 101c and the fourth pixel unit 101d.
  • the second electrode T62 of the first reset transistor T6 is connected to the gate electrode T10 of the driving transistor T1 through the third connection line CL3.
  • the second electrode T62 of the first reset transistor T6 is integrally formed with the second electrode T32 of the threshold compensation transistor T3, so that the second electrode T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1.
  • the orthographic projection of the shielding portion CEs on the base substrate BS at least partially overlaps the orthographic projection of the second pole T62 of the first reset transistor T6 on the base substrate BS.
  • the orthographic projection of the shielding portion CEs on the base substrate BS is at the same level as the second electrode T32 of the threshold compensation transistor T3.
  • the orthographic projections on the base substrate BS at least partially overlap.
  • the orthographic projection of the shielding portion CEs on the base substrate BS does not overlap with the orthographic projection of the second gate signal line SL2 on the base substrate BS, so that the shielding portion CEs The upper end position in the second direction Y is defined.
  • the first initialization signal line INT1 and the second initialization signal line INT2 are respectively provided on opposite sides of the gate T10 of the driving transistor T1, and the orthographic projection of the shielding portion CEs on the base substrate BS It overlaps with the orthographic portion of the second initialization signal line INT2 on the base substrate BS.
  • the orthographic projection of the second initialization signal line INT2 on the base substrate BS partially overlaps the orthographic projection of the second conductive connection portion CP2 of the pixel unit in the next row on the base substrate BS, so that the second A capacitor is formed between the initialization signal line INT2 and the shield portion CEs, and the capacitor serves as a stabilizing capacitor to reduce the leakage current of the first reset transistor T6.
  • the first reset control signal line RT1 and the second reset control signal line RT2 are respectively provided on opposite sides of the gate T10 of the driving transistor T1 , and referring to FIG. 9 , the second reset control signal line RT2 is on the substrate
  • the orthographic projection on the substrate BS and the orthographic projection of the shielding portions CEs on the base substrate BS do not overlap. Thereby, the lower end position of the shielding portion CEs in the second direction Y is defined.
  • the orthographic projection of the first reset control signal line RT1 on the base substrate BS and the orthographic projection of the shielding portions CEs on the base substrate BS do not overlap.
  • the first reset control signal line extends along the first direction X
  • the second reset control signal line extends along the first direction X.
  • each sixth connection electrode CEf is connected to one light-emitting element, that is, each sixth connection electrode CEf corresponds to one pixel unit 101 .
  • each shielding portion CEs is connected to one light-emitting element, that is, each shielding portion CEs corresponds to one pixel unit 101 .
  • the orthographic projection of the first gate T601 and the second gate T602 of the first reset transistor T6 on the base substrate BS is the same as the first channel T631 and the second channel T632 of the first reset transistor T6
  • the orthographic projections on the base substrate BS overlap, respectively.
  • the orthographic projection of the first gate T301 and the second gate T302 of the threshold compensation transistor T3 on the substrate substrate BS is the same as that of the first channel T331 and the second channel T332 of the threshold compensation transistor T3 on the substrate
  • the orthographic projections on the base substrate BS overlap, respectively.
  • the first power supply line VDD1 is connected to the second pole Cb of the storage capacitor Cst through the power supply connection line VDD0 .
  • the threshold compensation transistor T3 is a dual-gate transistor, and the intermediate node (the first conductive connection portion CP1 ) of the threshold compensation transistor T3 is disturbed by the transition of the scan signal, and the voltage increases at the moment when the scan signal is turned off. The gate leakage will increase, which will lead to flicker (Flicker) problem.
  • the orthographic projection of the stopper BK on the base substrate BS at least partially overlaps the orthographic projection of the first conductive connection CP1 on the base substrate BS.
  • a stable capacitance is formed between the block BK and the first conductive connection portion CP1. Increasing the parasitic capacitance between the intermediate node of the threshold compensation transistor T3 and the first voltage signal ELVDD can reduce the amount of disturbance and improve the leakage problem.
  • a pixel circuit is formed on a base substrate to form the display panel shown in FIG. 9 or FIG. 10 , and on the basis of the display panel shown in FIG. 9 or FIG. 10 , light-emitting elements are formed to obtain a display panel that can be displayed, thereby , the pixel circuit is closer to the base substrate than the light-emitting element. As shown in FIG. 13 , the pixel circuit 10 is closer to the base substrate BS than the light-emitting element 20 is.
  • FIG. 12 shows the first pole 201 of the light emitting element 20 .
  • FIG. 13 is a cross-sectional view of a display panel according to an embodiment of the disclosure.
  • the film layer on the first pole 201 of the light-emitting element is omitted.
  • the layers above the first pole 201 of the light-emitting element 20 can be referred to in cross-sectional views.
  • the arrangement position and shape of the first pole 201 of the light-emitting element are not limited to those shown in FIG. 12 , and those skilled in the art can adjust the arrangement position and shape of the first pole 201 of the light-emitting element as required.
  • the buffer layer BL is located on the base substrate BS
  • the isolation layer BR is located on the buffer layer BL
  • the channel region, source and drain of the transistor are located on the isolation layer BR
  • the channel region, the source and the drain of the transistor are located on the isolation layer BR.
  • a first gate insulating layer GI1 is formed on the source and drain electrodes, the first conductive pattern layer LY1 is located on the first gate insulating layer GI1, the second gate insulating layer GI2 is located on the first conductive pattern layer LY1, and the second conductive pattern layer LY2 is located on the second gate insulating layer GI2, the interlayer insulating layer ILD is located on the second conductive pattern layer LY2, the third conductive pattern layer LY3 is located on the interlayer insulating layer ILD, and the passivation layer PVX is located on the first conductive pattern layer LY,
  • the first planarization layer PLN1 is located on the passivation layer PVX, and the fourth conductive pattern layer LY4 is located on the first planarization layer PLN1.
  • the second planarization layer PLN2 is located on the fourth conductive pattern layer LY4, the first pole 201 of the light emitting element 20 is located on the second planarization layer PLN2, the pixel definition layer PDL and the spacer PS are located on the second planarization layer
  • the pixel defining layer PDL has an opening OPN, and the opening OPN is configured to define a light-emitting area (light-emitting area, effective light-emitting area) of the pixel unit.
  • the spacer PS is configured to support the fine metal mask when the light emitting functional layer 203 is formed.
  • the opening OPN is the light emitting area of the pixel unit.
  • the light emitting functional layer 203 is located on the first pole 201 of the light emitting element 20
  • the second pole 202 of the light emitting element 20 is located on the light emitting functional layer 203
  • the encapsulation layer CPS is disposed on the light emitting element 20 .
  • the encapsulation layer CPS includes a first encapsulation layer CPS1, a second encapsulation layer CPS2 and a third encapsulation layer CPS3.
  • the first encapsulation layer CPS1 and the third encapsulation layer CPS3 are inorganic material layers, and the second encapsulation layer CPS2 is an organic material layer.
  • the first electrode 201 is the anode of the light-emitting element 20, and the second electrode 202 is the cathode of the light-emitting element 20, but it is not limited thereto.
  • the first electrode 201 of the light emitting element 20 is connected to the shielding portion CEs (sixth connection electrode CEf) through a via hole H9 penetrating the second planarization layer PLN2.
  • the light emitting element 20 includes an organic light emitting diode.
  • the light-emitting functional layer 203 is located between the second pole 202 and the first pole 201 .
  • the second electrode 202 is located on the side of the first electrode 201 away from the base substrate BS.
  • the light-emitting functional layer 203 includes at least a light-emitting layer, and may also include a hole transport layer, a hole injection layer, and at least one of the electron transport layer and the electron injection layer. one.
  • the second electrode Cb of the storage capacitor has an opening OPN1 , and the setting of the opening OPN1 facilitates that the second connecting electrode CEb is connected to the gate T10 of the driving transistor T1 .
  • the transistors in the pixel circuits of the embodiments of the present disclosure are all thin film transistors.
  • the first conductive pattern layer LY1, the second conductive pattern layer LY2, the third conductive pattern layer LY3, and the fourth conductive pattern layer LY4 are all made of metal materials.
  • the first conductive pattern layer LY1 and the second conductive pattern layer LY2 are formed of metal materials such as nickel and aluminum, but are not limited thereto.
  • the third conductive pattern layer LY3 and the fourth conductive pattern layer LY4 are formed of materials such as titanium, aluminum, etc., but are not limited thereto.
  • the third conductive pattern layer LY3 and the fourth conductive pattern layer LY4 are structures formed by three sub-layers of Ti/AL/Ti, respectively, but not limited thereto.
  • a glass substrate or a polyimide substrate can be used as the base substrate, but it is not limited thereto, and can be selected as required.
  • the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the passivation layer PVX, the first planarization layer PLN1, the second planarization layer PLN2, the pixel definition layer PDL, the spacer PS All are made of insulating material.
  • the materials of the first pole 201 and the second pole 202 of the light-emitting element can be selected as required.
  • the first electrode 201 may be at least one of transparent conductive metal oxide and silver, but not limited thereto.
  • the transparent conductive metal oxide includes, but is not limited to, indium tin oxide (ITO).
  • ITO indium tin oxide
  • the first pole 201 may adopt a structure in which three sub-layers of ITO-Ag-ITO are provided.
  • the second pole 202 may be a low work function metal, at least one of magnesium and silver may be used, but not limited thereto.
  • the shielding portions CEs shown in FIG. 16 may not be provided. Instead, connecting electrodes with a smaller length in the second direction are used. That is, the sixth connection electrode CEf/shield CEs may take other sizes and shapes.
  • the data writing transistor T2 may be referred to as a first transistor, and the threshold compensation transistor T3 may be referred to as a second transistor.
  • the first gate signal line SL1 and the second gate signal line SL1 and the second gate signal At least one of the lines SL2 can output the turn-on signal of the N-type transistor; the film layers selected by the first gate line GT1 and the second gate line GT2 are not limited to the first conductive pattern layer LY1, the first gate signal line SL1 and the second gate line GT2.
  • the film layer selected for the gate signal line SL2 is not limited to the second conductive pattern layer LY2, but can also be other metal film layers, such as the metal film layer above the second conductive pattern layer LY2, such as the third conductive pattern layer LY3, which can also be used.
  • oxide TFT oxide thin film transistor
  • oxide semiconductor can also be used as a connecting line, or a transfer structure, etc. through a conductorization process.
  • At least one embodiment of the present disclosure further provides a display device including any one of the above-mentioned display panels.
  • the display device includes an OLED or a high frame rate driven product including an OLED.
  • the display device includes any product or component with a display function, such as a TV, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, a navigator, etc., which contain the above-mentioned display panel.
  • the above description takes a 7T1C pixel circuit as an example, and embodiments of the present disclosure include but are not limited to this. It should be noted that the embodiments of the present disclosure do not limit the number of thin film transistors and the number of capacitors included in the pixel circuit.
  • the pixel circuit of the display panel may also have a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, which is not limited in the embodiments of the present disclosure.
  • elements located on the same layer may be processed by the same patterning process from the same film layer.
  • elements located on the same layer may be located on a surface of the same element remote from the base substrate.
  • the patterning or patterning process may include only a photolithography process, or may include a photolithography process and an etching step, or may include other processes for forming predetermined patterns such as printing and inkjet.
  • the lithography process refers to the process of film formation, exposure, development, etc., using photoresist, mask, exposure machine, etc. to form patterns.
  • Corresponding patterning processes may be selected according to the structures formed in the embodiments of the present disclosure.

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Abstract

一种显示面板和显示装置。显示面板包括：像素单元（101），包括像素电路（10）和发光元件（20），像素电路（10）包括第一晶体管（T2），像素单元（101）包括位于同一行且位于相邻列的第一像素单元（101a）和第二像素单元（101b）；第一栅线（GT1），与第一像素单元（101a）的第一晶体管（T2）的栅极（T20）相连；第二栅线（GT2），与第二像素单元（101b）的第一晶体管（T2）的栅极（T20）相连；第一栅信号线（SL1），沿第一方向（X）延伸，与第一像素单元（101a）相连，并被配置为向第一像素单元（101a）提供第一扫描信号；第二栅信号线（SL2），沿第一方向（X）延伸，与第二像素单元（101b）相连，并被配置为向第二像素单元（101b）提供第二扫描信号；第一连接线（CL1），沿第二方向（Y）延伸，第一栅线（GT1）通过第一连接线（CL1）与第一栅信号线（SL1）相连；以及第二连接线（CL2），沿第二方向（Y）延伸，第二栅线（GT2）通过第二连接线（CL2）与第二栅信号线（SL2）相连。

Description

显示面板和显示装置
相关申请的交叉引用
出于所有目的，本专利申请要求于2020年12月28日递交的PCT专利申请第PCT/CN2020/140199号的优先权，在此全文引用上述PCT专利申请公开的内容以作为本公开的实施例的一部分。
技术领域
本公开至少一实施例涉及一种显示面板和显示装置。
背景技术
随着显示技术的不断发展，有源矩阵型有机发光二极管(Active-Matrix Organic Light-Emitting Diode，AMOLED)显示技术因其自发光、广视角、高对比度、低功耗、高反应速度等优点已经在手机、平板电脑、数码相机等显示装置上得到越来越多地应用。
发明内容
本公开的至少一实施例涉及一种显示面板和显示装置。
本公开至少一实施例提供一种显示面板，包括：像素单元，包括像素电路和发光元件，所述像素电路被配置为驱动所述发光元件，所述像素电路包括第一晶体管，所述像素单元包括位于同一行且位于相邻列的第一像素单元和第二像素单元；第一栅线，与所述第一像素单元的所述第一晶体管的栅极相连；第二栅线，与所述第二像素单元的所述第一晶体管的栅极相连；第一栅信号线，沿第一方向延伸，与所述第一像素单元相连，并被配置为向所述第一像素单元提供第一扫描信号；第二栅信号线，沿所述第一方向延伸，与所述第二像素单元相连，并被配置为向所述第二像素单元提供第二扫描信号；第一连接线，沿第二方向延伸，所述第一栅线通过所述第一连接线与所述第一栅信号线相连；以及第二连接线，沿所述第二方向延伸，所述第二栅线通过所述第二连接线与所述第二栅信号线相连，所述第二方向与所述第一方向相交。
例如，在本公开的一些实施例中，所述第一栅信号线和所述第二栅信号线彼此绝缘。
例如，在本公开的一些实施例中，所述第一栅线和所述第二栅线彼此分离，并沿所述第一方向排列。
例如，在本公开的一些实施例中，所述第二栅信号线比所述第一栅信号线更靠近所述第一栅线。
例如，在本公开的一些实施例中，所述第一栅信号线和所述第二栅信号线在衬底基板上的正投影与所述第一晶体管的沟道区在所述衬底基板上的正投影不交叠。
例如，在本公开的一些实施例中，所述第一栅线、所述第一连接线、所述第一栅信号线位于三个不同的层，并且所述第二栅线、所述第二连接线和所述第二栅信号线位于三个 不同的层。
例如，在本公开的一些实施例中，所述第一栅线和所述第二栅线位于同一层，所述第一连接线和所述第二连接线位于同一层，并且所述第一栅信号线和所述第二栅信号线位于同一层。
例如，在本公开的一些实施例中，所述第一栅线和所述第二栅线位于第一导电图案层；所述第一栅信号线和所述第二栅信号线位于第二导电图案层；所述第一连接线和所述第二连接线位于第三导电图案层；所述第一导电图案层比所述第二导电图案层更靠近衬底基板，所述第二导电图案层比所述第三导电图案层更靠近所述衬底基板。
例如，在本公开的一些实施例中，显示面板还包括第一栅绝缘层、第二栅绝缘层和层间绝缘层，所述第一导电图案层位于所述第一栅绝缘层上，所述第一导电图案层和所述第二导电图案层之间设有所述第二栅绝缘层，所述层间绝缘层位于所述第二导电图案层上，所述第三导电图案层位于所述层间绝缘层上；所述第一连接线的一端通过贯穿所述第二栅绝缘层和所述层间绝缘层的第一过孔与所述第一栅线相连，所述第一连接线的另一端通过贯穿所述层间绝缘层的第二过孔与所述第一栅信号线相连；所述第二连接线的一端通过贯穿所述第二栅绝缘层和所述层间绝缘层的第三过孔与所述第二栅线相连，所述第二连接线的另一端通过贯穿所述层间绝缘层的第四过孔与所述第二栅信号线相连。
例如，在本公开的一些实施例中，所述像素电路还包括驱动晶体管和第二晶体管；所述第一像素单元的所述第二晶体管的栅极与所述第一栅线相连，所述第二像素单元的所述第二晶体管的栅极与所述第二栅线相连，所述第二晶体管的第一极与所述驱动晶体管的第二极相连，所述第二晶体管的第二极与所述驱动晶体管的栅极相连。
例如，在本公开的一些实施例中，显示面板还包括第一电源端和数据线，其中，所述第一电源端被配置为向所述像素电路提供第一电压信号，所述数据线被配置为向所述像素电路提供数据信号；所述像素电路还包括存储电容；所述第一晶体管的第一极与所述数据线相连，所述驱动晶体管的第一极与所述第一晶体管的第二极相连；所述存储电容的第一极与所述驱动晶体管的栅极相连，所述存储电容的第二极与所述第一电源端相连。
例如，在本公开的一些实施例中，所述第一栅信号线和所述第二栅信号线在衬底基板上的正投影与所述第二晶体管的沟道区在所述衬底基板上的正投影不交叠。
例如，在本公开的一些实施例中，显示面板还包括初始化信号线，所述初始化信号线被配置为向所述像素电路提供初始化信号，所述像素电路还包括第一复位晶体管；所述第一复位晶体管的第一极与所述初始化信号线相连，所述第一复位晶体管的第二极与所述驱动晶体管的栅极相连。
例如，在本公开的一些实施例中，所述第一栅信号线和所述第二栅信号线位于所述第二晶体管和所述第一复位晶体管之间。
例如，在本公开的一些实施例中，所述像素单元还包括与所述第一像素单元位于同一列的第三像素单元，所述数据线包括第一数据线、第二数据线和第三数据线，所述第一数据线与所述第一像素单元相连，所述第二数据线与所述第二像素单元相连，所述第三数据 线与所述第三像素单元相连。
例如，在本公开的一些实施例中，所述像素单元还包括与第二像素单元位于同一列的第四像素单元，所述数据线包括第四数据线，所述第四数据线与所述第四像素单元相连。
例如，在本公开的一些实施例中，显示面板还包括连接元件，所述发光元件通过所述连接元件与所述像素电路相连，所述连接元件包括屏蔽部，所述屏蔽部沿所述第二方向延伸；所述数据线与所述屏蔽部位于同一层，所述数据线包括两条相邻数据线，所述屏蔽部位于所述两条相邻数据线之间，所述第一连接线在所述衬底基板上的正投影与所述屏蔽部在所述衬底基板上的正投影不交叠。
例如，在本公开的一些实施例中，所述像素电路包括驱动晶体管和第二晶体管，所述第二晶体管的第一极与所述驱动晶体管的第二极相连，所述第二晶体管的第二极与所述驱动晶体管的栅极相连；所述显示面板还包括第三连接线，所述驱动晶体管的栅极通过所述第三连接线与所述第二晶体管的第二极相连，所述屏蔽部在所述衬底基板上的正投影的面积大于所述第三连接线在所述衬底基板上的正投影的面积。
例如，在本公开的一些实施例中，所述驱动晶体管的栅极在所述衬底基板上的正投影与所述屏蔽部在所述衬底基板上的正投影部分交叠，所述屏蔽部与所述驱动晶体管的栅极的交叠部分的面积小于所述驱动晶体管的栅极的面积。
例如，在本公开的一些实施例中，所述驱动晶体管的栅极在所述第一方向上的尺寸大于所述屏蔽部在所述第一方向上的尺寸；所述屏蔽部在所述第二方向上的尺寸大于所述驱动晶体管的栅极在所述第二方向上的尺寸。
例如，在本公开的一些实施例中，所述屏蔽部在所述衬底基板上的正投影与所述第一栅线或所述第二栅线在所述衬底基板上的正投影交叠。
本公开至少一实施例还提供一种显示装置，包括上述任一显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种7T1C的像素电路的示意图；
图2为图1所示的像素电路的工作时序图；
图3为本公开一实施例提供的一种显示面板的一个重复单元的像素电路图；
图4为本公开一实施例提供的一种显示面板中的半导体图形的平面图；
图5为本公开一实施例提供的一种显示面板中的第一导电图案层的平面图；
图6为本公开一实施例提供的一种显示面板中的第二导电图案层的平面图；
图7为本公开一实施例提供的一种显示面板中的第三导电图案层的平面图；
图8为本公开一实施例提供的一种显示面板中的第四导电图案层的平面图；
图9为本公开一实施例提供的一种显示面板中的形成第四导电图案层后的重复单元的结构的平面图；
图10为本公开一实施例提供的一种显示面板中的形成第四导电图案层后的像素单元的结构的平面图；
图11为图10的沿AB线的剖视图；
图12为本公开一实施例提供的一种显示面板中的形成发光元件后的像素单元的结构的平面图；以及
图13为图12的沿CD线的剖视图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
双栅以及双数据线(Dual gate&Dual source)技术方案可以解决高频显示中存在的补偿时间不足问题。但是该方案在高分辨率显示设备应用中存在像素布局空间限制，以及各信号线之间寄生电容的问题。
目前市场有较大的高帧频AMOLED显示面板的需求，例如，双数据(Dual Data)方案可以在保证显示效果的前提下实现120Hz的驱动。
图1为一种7T1C的像素电路的示意图。图2为图1所示的像素电路的工作时序图。图1所示的像素电路可为相关技术中常见的低温多晶硅(Low Temperature Poly-silicon，LTPS)AMOLED的像素电路。
图1示出了显示面板的一个像素单元的像素电路，如图1所示，像素单元101包括像素电路10和发光元件20。像素电路10包括六个开关晶体管(T2-T7)、一个驱动晶体管T1和一个存储电容Cst。六个开关晶体管分别为数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、以及第二复位晶体管T7。发光元件20包括第一极201、第二极202以及位于第一极201和第二极202之间的发光功能层。例如，第一极201为阳极，第二极202为阴极。通常，阈值补偿晶体管T3、第一复位晶体管T6采用双栅薄膜晶体管(Thin Film Transistor，TFT)的方式降低漏电。
如图1所示，显示面板包括栅线GT、数据线DT、第一电源端VDD、第二电源端VSS、发光控制信号线EML、初始化信号线INT、复位控制信号线RT等。例如，复位控制信号线RT包括第一复位控制信号线RT1和第二复位控制信号线RT2。第一电源端VDD被配置为向像素单元101提供恒定的第一电压信号ELVDD、第二电源端VSS被配置为向像素单元101提供恒定的第二电压信号ELVSS，并且第一电压信号ELVDD大于第二电压信号ELVSS。栅线GT被配置为向像素单元101提供扫描信号SCAN、数据线DT被配置为向像素单元101提供数据信号DATA(数据电压VDATA)、发光控制信号线EML被配置为向像素单元101提供发光控制信号EM，第一复位控制信号线RT1被配置为向像素单元101提供复位控制信号RESET，第二复位控制信号线RT2被配置为向像素单元101提供扫描信号SCAN，初始化信号线INT被配置为向像素单元101提供初始化信号Vinit。例如，初始化信号Vinit为恒定的电压信号，其大小例如可以介于第一电压信号ELVDD和第二电压信号ELVSS之间，但不限于此，例如，初始化信号Vinit可大于或等于第二电压信号ELVSS。例如，初始化信号线INT包括第一初始化信号线INT1和第二初始化信号线INT2。例如，第一初始化信号线INT1被配置为向像素单元101提供初始化信号Vinit1，第二初始化信号线INT1被配置为向像素单元101提供初始化信号Vinit2。例如，在一些实施例中，第一初始化信号Vinit1和第二初始化信号Vinit2相等，均为Vinit。
如图1所示，驱动晶体管T1与发光元件20电连接，并在扫描信号SCAN、数据信号DATA、第一电压信号ELVDD、第二电压信号ELVSS等信号的控制下输出驱动电流以驱动发光元件20发光。
例如，发光元件20为有机发光二极管(OLED)，发光元件20在其对应的像素电路10的驱动下发出红光、绿光、蓝光，或者白光等。例如，一个像素包括多个像素单元。一个像素可包括出射不同颜色光的多个像素单元。例如，一个像素包括出射红光的像素单元，出射绿光的像素单元和出射蓝光的像素单元，但不限于此。一个像素包括的像素单元的个数以及每个像素单元的出光情况可根据需要而定。
例如，如图1所示，数据写入晶体管T2的栅极T20与栅线GT相连，数据写入晶体管T2的第一极T21与数据线DT相连，数据写入晶体管T2的第二极T22与驱动晶体管T1的第一极T11相连。
例如，如图1所示，像素电路10还包括阈值补偿晶体管T3，阈值补偿晶体管T3的栅极T30与栅线GT相连，阈值补偿晶体管T3的第一极T31与驱动晶体管T1的第二极T12相连，阈值补偿晶体管T3的第二极T32与驱动晶体管T1的栅极T10相连。
例如，如图1所示，显示面板还包括发光控制信号线EML，像素电路10还包括第一发光控制晶体管T4和第二发光控制晶体管T5，第一发光控制晶体管T4的栅极T40与发光控制信号线EML相连，第一发光控制晶体管T4的第一极T41与第一电源端VDD相连，第一发光控制晶体管T4的第二极T42与驱动晶体管T1的第一极T11相连；第二发光控制晶体管T5的栅极T50与发光控制信号线EML相连，第二发光控制晶体管T5的第一极T51与驱动晶体管T1的第二极T12相连，第二发光控制晶体管T5的第二极T52与发光 元件20的第一极201相连。
如图1所示，第一复位晶体管T6与驱动晶体管T1的栅极T10相连，并被配置为对驱动晶体管T1的栅极T10进行复位，第二复位晶体管T7与发光元件20的第一极201相连，并被配置为对发光元件20的第一极201进行复位。第一初始化信号线INT1通过第一复位晶体管T6与驱动晶体管T1的栅极相连。第二初始化信号线INT2通过第二复位晶体管T7与发光元件20的第一极201相连。例如，第一初始化信号线INT1和第二初始化信号线INT2相连，以被输入相同的初始化信号，但不限于此，在一些实施例中，第一初始化信号线INT1和第二初始化信号线INT2也可以彼此绝缘，并被配置为分别输入信号。
例如，如图1所示，第一复位晶体管T6的第一极T61与第一初始化信号线INT1相连，第一复位晶体管T6的第二极T62与驱动晶体管T1的栅极T10相连，第二复位晶体管T7的第一极T71与第二初始化信号线INT2相连，第二复位晶体管T7的第二极T72与发光元件20的第一极201相连。例如，如图1所示，第一复位晶体管T6的栅极T60与第一复位控制信号线RT1相连，第二复位晶体管T7的栅极T70与第二复位控制信号线RT2相连。
如图1所示，第一电源端VDD被配置为向像素电路10提供第一电压信号ELVDD；像素电路还包括存储电容Cst，存储电容Cst的第一极Ca与驱动晶体管T1的栅极T10相连，存储电容Cst的第二极Cb与第一电源端VDD相连。
例如，如图1所示，显示面板还包括第二电源端VSS，第二电源端VSS与发光元件20的第二极201相连。
如图2所示，一帧显示时间段，像素单元的驱动方法包括第一复位阶段t1、数据写入及阈值补偿和第二复位阶段t2、和发光阶段t3，复位控制信号RESET为低电平时，给驱动晶体管T1的栅极复位，扫描信号SCAN为低电平时，给发光元件20的第一极201(例如，阳极)复位。例如，如图1所示，扫描信号SCAN为低电平时，数据电压VDATA写入，同时获取驱动晶体管T1的阈值电压Vth，并将含有数据线上数据信息的数据电压VDADA存储在电容Cst内；发光控制信号线EML为低电平时，发光元件20发光，第一节点N1(栅极点)的电压保持(发光元件20的发光稳定性)靠存储电容Cst维持。在像素电路10的驱动过程中，在发光阶段，存储电容用以保持电压信号，使其信号保持端的电位得以保持恒定，在驱动晶体管的栅极和源极之间形成电压差，从而控制驱动晶体管形成驱动电流，进而驱动发光元件20发光。
如图2所示，在复位阶段t1，设置发光控制信号EM为关闭电压，设置复位控制信号RESET为开启电压，设置扫描信号SCAN为关闭电压。
如图2所示，在数据写入及阈值补偿阶段和第二复位阶段t2，设置发光控制信号EM为关闭电压，设置复位控制信号RESET为关闭电压，设置扫描信号SCAN为开启电压。
如图2所示，在发光阶段t3，设置发光控制信号EM为开启电压，设置复位控制信号RESET为关闭电压，设置扫描信号SCAN为关闭电压。
如图2所示，第一电压信号ELVDD和第二电压信号ELVSS均为恒定的电压信号， 例如，初始化信号Vinit介于第一电压信号ELVDD和第二电压信号ELVSS之间。
例如，本公开实施例中的开启电压是指能使相应晶体管的第一极和第二极导通的电压，关闭电压是指能使相应晶体管的第一极和第二极断开的电压。当晶体管为P型晶体管时，开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)；当晶体管为N型晶体管时，开启电压为高电压(例如，5V)，关闭电压为低电压(例如，0V)。图2所示的驱动波形均以P型晶体管为例进行说明。例如，开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)，但不限于此。
请一并参阅图1和图2，在第一复位阶段t1，发光控制信号EM为关闭电压，复位控制信号RESET为开启电压，扫描信号SCAN为关闭电压。此时，第一复位晶体管T6处于导通状态，而第二复位晶体管T7、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4和第二发光控制晶体管T5处于关闭状态。第一复位晶体管T6将第一初始化信号(初始化电压Vinit)Vinit1传输到驱动晶体管T1的栅极并被存储电容Cst存储，将驱动晶体管T1复位并消除上一次(上一帧)发光时存储的数据。
在数据写入及阈值补偿和第二复位阶段t2，发光控制信号EM为关闭电压，复位控制信号RESET为关闭电压，扫描信号SCAN为开启电压。此时，数据写入晶体管T2和阈值补偿晶体管T3处于导通状态，第二复位晶体管T7处于导通状态，第二复位晶体管T7将第二初始化信号(初始化电压Vinit)Vinit2传输到发光元件20的第一电极201，以将发光元件20复位。而第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6处于关闭状态。此时，数据写入晶体管T2将数据电压VDATA传输到驱动晶体管T1的第一极，即，数据写入晶体管T2接收扫描信号SCAN和数据电压VDATA并根据扫描信号SCAN向驱动晶体管T1的第一极写入数据电压VDATA。阈值补偿晶体管T3导通将驱动晶体管T1连接成二极管结构，由此可对于驱动晶体管T1的栅极进行充电。充电完成之后，驱动晶体管T1的栅极电压为VDATA+Vth，其中，VDATA为数据电压，Vth为驱动晶体管T1的阈值电压，即，阈值补偿晶体管T3接收扫描信号SCAN并根据扫描信号SCAN对驱动晶体管T1的栅极电压进行阈值电压补偿。在此阶段，存储电容Cst两端的电压差为ELVDD-VDATA-Vth。
在发光阶段t3，发光控制信号EM为开启电压，复位控制信号RESET为关闭电压，扫描信号SCAN为关闭电压。第一发光控制晶体管T4和第二发光控制晶体管T5处于导通状态，而数据写入晶体管T2、阈值补偿晶体管T3、第一复位晶体管T6和第二复位晶体管T7处于关闭状态。第一电压信号ELVDD通过第一发光控制晶体管T4传输到驱动晶体管T1的第一极，驱动晶体管T1的栅极电压保持为VDATA+Vth，发光电流I通过第一发光控制晶体管T4、驱动晶体管T1和第二发光控制晶体管T5流入发光元件20，发光元件20发光。即，第一发光控制晶体管T4和第二发光控制晶体管T5接收发光控制信号EM，并根据发光控制信号EM控制发光元件20发光。发光电流I满足如下饱和电流公式：
K(Vgs-Vth) 2＝K(VDATA+Vth-ELVDD-Vth) 2＝K(VDATA-ELVDD) 2
其中，
Figure PCTCN2021072707-appb-000001
μ n为驱动晶体管的沟道迁移率，Cox为驱动晶体管T1单位面积的沟道电容，W和L分别为驱动晶体管T1的沟道宽度和沟道长度，Vgs为驱动晶体管T1的栅极与源极(也即本实施例中驱动晶体管T1的第一极)之间的电压差。
由上式中可以看到流经发光元件20的电流与驱动晶体管T1的阈值电压无关。因此，本像素电路非常好的补偿了驱动晶体管T1的阈值电压。
例如，发光阶段t3的时长占一帧显示时间段的比例可被调节。这样，可以通过调节发光阶段t3的时长占一帧显示时间段的比例控制发光亮度。例如，通过控制显示面板中的扫描驱动电路或者额外设置的驱动电路实现调节发光阶段t3的时长占一帧显示时间段的比例。
例如，本公开实施例不限于图1所示出的具体像素电路，可以采用其他能实现对于驱动晶体管补偿的像素电路。基于本公开对该实现方式的描述和教导，本领域普通技术人员在没有做出创造性劳动前提下能够容易想到的其它设置方式，都属于本公开的保护范围之内。
图3为本公开一实施例提供的一种显示面板的一个重复单元的像素电路图。如图3所示，显示面板包括第一像素单元101a、第二像素单元101b、第三像素单元101c和第四像素单元101d，并且第一像素单元101a、第二像素单元101b、第三像素单元101c和第四像素单元101d构成一个重复单元RP。多个重复单元RP可构成阵列。重复单元RP为显示阵列的一个最小重复单元。
例如，显示面板采用双栅以及双数据线驱动的方式，可实现第一像素单元101a、第二像素单元101b、第三像素单元101c和第四像素单元101d分别独立控制，在显示面板的驱动过程中，第一像素单元101a、第二像素单元101b、第三像素单元101c和第四像素单元101d分别依次点亮，因为双栅以及双数据线控制，第一像素单元101a的栅线可持续打开至第四像素单元101d的数据信号写入完成，其他像素单元同理，这样每个像素单元可以有足够的补偿时间。
如图3所示，第一像素单元101a和第二像素单元101b位于同一行并位于相邻列，第三像素单元101c和第四像素单元101d位于同一行并位于相邻列。第一像素单元101a和第三像素单元101c位于同一列并位于相邻行，第二像素单元101b和第四像素单元101d位于同一列并位于相邻行。
图3示出了第一数据线DT1、第二数据线DT2、第三数据线DT3和第四数据线DT4。参考图3，第一数据线DT1与第一像素单元101a相连，第二数据线DT2与第二像素单元101b相连，第三数据线DT3与第三像素单元101c相连，第四数据线DT4与第四像素单元101d相连。
在图3中，在同一个像素单元中，第一复位晶体管T6和第二复位晶体管T7连接至同一条复位控制信号线RT，以在相同时刻被输入相同的复位控制信号，但本公开的实施 例不限于此。
在其他的实施例中，在同一个像素单元中，也可以第一复位晶体管T6和第二复位晶体管T7分别连接至第一复位控制信号线和第二复位控制信号线，第一复位控制信号线和第二复位控制信号线彼此绝缘以被分别输入信号。此情况下，第一复位晶体管T6和第二复位晶体管T7在不同的时刻被输入信号，如前所述，第一复位晶体管T6在第一复位阶段t1被输入复位控制信号RESET，第二复位晶体管T7在数据写入及阈值补偿和第二复位阶段t2被输入扫描信号SCAN。例如，本级的栅线GT与下一级的复位控制信号线相连。例如，栅线GT和第二复位控制信号线RT2可以电连接以在同一时间输入相同的信号。
以下结合图4至图11对本公开的实施例提供的显示面板进行说明。图4为本公开一实施例提供的一种显示面板中的半导体图形的平面图。图5为本公开一实施例提供的一种显示面板中的第一导电图案层的平面图。图6为本公开一实施例提供的一种显示面板中的第二导电图案层的平面图。图7为本公开一实施例提供的一种显示面板中的第三导电图案层的平面图。图8为本公开一实施例提供的一种显示面板中的第四导电图案层的平面图。图9为本公开一实施例提供的一种显示面板中的形成第四导电图案层后的重复单元的结构的平面图。图10为本公开一实施例提供的一种显示面板中的形成第四导电图案层后的像素单元的结构的平面图。图11为图10的沿AB线的剖视图。图12为本公开一实施例提供的一种显示面板中的形成发光元件后的像素单元的结构的平面图。图13为图12中沿CD线的剖视图。
图4至图10示出了第一方向X和第二方向Y，第二方向Y与第一方向X相交。例如，本公开的实施例以第一方向X与第二方向Y垂直为例。例如，第一方向X为像素单元的行方向，第二方向Y为像素单元的列方向。第一方向X和第二方向Y均为平行于衬底基板BS的方向。图11和图13示出了第三方向Z，第三方向Z为垂直于衬底基板BS的方向。第三方向Z垂直于第一方向X，并且垂直于第二方向Y。
在本公开的实施例中，为了图示清晰，平面图中，绝缘层以过孔的形式示出，绝缘层本身采用了透明化处理，并且第一导电图案层、第二导电图案层、第三导电图案层、第四导电图案层做了半透明处理。
图4示出了半导体图形SCP，图5示出了第一导电图案层LY1，例如，第一导电图案层LY1和半导体图形SCP之间设置有第一栅绝缘层(第一栅绝缘层GI1，参照图11)。例如，在衬底基板上形成半导体图形SCP以及后续各种部件。如图5所示，第一导电图案层LY1包括第一复位控制信号线RT1、第一栅线GT1、第二栅线GT2、存储电容Cst的第一极Ca(驱动晶体管T1的栅极T10)、发光控制信号线EML、第二复位控制信号线RT2。
以第一导电图案层LY1为掩模版对半导体图形SCP进行掺杂，使得半导体图形SCP的被第一导电图案层LY1覆盖的区域保留半导体特性，形成有源层ACT(参见图10)，而半导体图形SCP的未被第一导电图案层LY1覆盖的区域被导体化，形成薄膜晶体管的源极和漏极。如10示出了半导体图形SCP被部分导体化之后形成的有源层ACT。
例如，在显示面板的制作过程中，采用自对准工艺，以第一导电图案层LY1为掩模 对半导体图案层SCP进行导体化处理，例如，采用离子注入工艺对半导体图案层SCP进行重掺杂，从而使得半导体图案层SCP的未被第一导电图案层LY1覆盖的部分被导体化，形成驱动晶体管T1的源极区(第一极T11)和漏极区(第二极T12)、数据写入晶体管T2的源极区(第一极T21)和漏极区(第二极T22)、阈值补偿晶体管T3的源极区(第一极T31)和漏极区(第二极T32)、第一发光控制晶体管T4的源极区(第一极T41)和漏极区(第二极T42)、第二发光控制晶体管T5的源极区(第一极T51)和漏极区(第二极T52)、第一复位晶体管T6的源极区(第一极T61)和漏极区(第二极T62)、以及第二复位晶体管T7的源极区(第一极T71)和漏极区(第二极T72)。半导体图案层SCP的被第一导电图案层L1覆盖的部分保留半导体特性，形成驱动晶体管T1的沟道区、数据写入晶体管T2的沟道区、阈值补偿晶体管T3的沟道区、第一发光控制晶体管T4的沟道区、第二发光控制晶体管T5的沟道区、第一复位晶体管T6的沟道区、以及第二复位晶体管T7的沟道区。各晶体管的沟道区构成有源层ACT(参考图10)。
例如，参考图1、图4、图9和图10，第二复位晶体管T7的第二极T72和第二发光控制晶体管T5的第二极T52一体形成；第二发光控制晶体管T5的第一极T51、驱动晶体管T1的第二极T12和阈值补偿晶体管T3的第一极T31一体形成；驱动晶体管T1的第一极T11、数据写入晶体管T2的第二极T22、第一发光控制晶体管T4的第二极T42一体形成；阈值补偿晶体管T3的第二极T32和第一复位晶体管T6的第二极T62一体形成。
例如，本公开实施例采用的晶体管的沟道区(有源层)可以为单晶硅、多晶硅(例如低温多晶硅)或金属氧化物半导体材料(如IGZO、AZO等)。在一个实施例中，该晶体管均为P型低温多晶硅(LTPS)薄膜晶体管。在另一个实施例中，与驱动晶体管T1的栅极直接连接的阈值补偿晶体管T3和第一复位晶体管T6为金属氧化物半导体薄膜晶体管，即晶体管的沟道材料为金属氧化物半导体材料(如IGZO、AZO等)，金属氧化物半导体薄膜晶体管具有较低的漏电流，可以有助于降低驱动晶体管T1的栅极漏电流。例如，该情况下，可采用LTPO(Low Temperature Polycrystalline Oxide，LTPO)工艺来制作显示面板。LTPO工艺结合低温多晶硅(Low Tempreture Poly-Silicon，LTPS)和氧化物(Oxide)的优势。即，同一个像素单元中集成了低温多晶硅(LTPS)和氧化物(Oxide)两种TFT器件。
例如，本公开实施例采用的晶体管可以包括多种结构，如顶栅型、底栅型或者双栅结构。在一些实施例中，与驱动晶体管T1的栅极直接连接的阈值补偿晶体管T3和第一复位晶体管T6为双栅型薄膜晶体管，可以有助于降低驱动晶体管T1的栅极漏电流。
例如，如图5、图9和图10所示，发光控制信号线EML的一部分作为第一发光控制晶体管T4的栅极T40，发光控制信号线EML的一部分作为第二发光控制晶体管T5的栅极T50，第一复位晶体管T6的栅极T60为第一复位控制信号线RT1的一部分，第二复位晶体管T7的栅极T70为第二复位控制信号线RT2的一部分，数据写入晶体管T2的栅极T20为栅线GT的一部分，阈值补偿晶体管T3的栅极T30为栅线GT的一部分。栅线GT为第一栅线GT1或第二栅线GT2。
如图5所示，第一复位控制信号线RT1、第一栅线GT1、第二栅线GT2、发光控制信号线EML和第二复位控制信号线RT2均沿第一方向X延伸。
如图8、图9和图10所示，数据线DT沿第二方向Y延伸，第一数据线DT1、第三数据线DT3、第四数据线DT4和第二数据线DT2沿第一方向X排列。
图6示出了第二导电图案层LY2。例如，第二导电图案层LY2和第一导电图案层LY1之间设置有第二栅绝缘层(第二栅绝缘层GI2，参照图11)。第二导电图案层LY2包括挡块BK、第一初始化信号线INT1、第二初始化信号线INT2、存储电容Cst的第二极Cb、第一栅信号线SL1和第二栅信号线SL2。例如，第一栅信号线SL1沿第一方向X延伸，第二栅信号线SL2沿第一方向X延伸。例如，参考图6，第一初始化信号线INT1沿第一方向X延伸，第二初始化信号线INT2沿第一方向X延伸。第一初始化信号线INT1、第一栅信号线SL1、第二栅信号线SL2和第二初始化信号线INT2沿第二方向Y排列。如图6所示，第一栅信号线SL1和第二栅信号线SL2位于第一初始化信号线INT1和存储电容Cst的第二极Cb之间。如图6所示，第一初始化信号线INT1和第二初始化信号线INT2位于存储电容Cst的第二极Cb的两侧，第一初始化信号线INT1和第二初始化信号线INT2位于挡块BK的两侧，第一初始化信号线INT1和第二初始化信号线INT2之间设有第一栅信号线SL1、第二栅信号线SL2、存储电容Cst的第二极Cb和挡块BK。如图6所示，第一初始化信号线INT1、第一栅信号线SL1、第二栅信号线SL2、挡块BK、存储电容Cst的第二极Cb和第二初始化信号线INT2沿第二方向Y依次排列。
如图7所示，第三导电图案层LY3包括电源连接线VDD0、第一连接电极CEa、第二连接电极CEb、第三连接电极CEc、第四连接电极CEd、第五连接电极CEe、第一连接线CL1和第二连接线CL2。第三导电图案层LY3和第二导电图案层LY2之间设有层间绝缘层(层间绝缘层ILD，参照图11)。
参考图5至图7、图9和图10，电源连接线VDD0通过过孔H2与第一发光控制晶体管T4的第一极T41电连接，电源连接线VDD0通过过孔H3和H30与存储电容Cst的第二极Cb电连接，电源连接线VDD0通过过孔H0与导电块BK电连接。第一连接电极CEa的一端通过过孔H12与第一初始化信号线INT1电连接，第一连接电极CEa的另一端通过过孔H11与第一复位晶体管T6的第一极T61相连，进而使得第一复位晶体管T6的第一极T61与第一初始化信号线INT1电连接。第二连接电极CEb的一端通过过孔H22与第一复位晶体管T6的第二极T62电连接，第二连接电极CEb的另一端通过过孔H21与驱动晶体管T1的栅极T10(也即存储电容Cst的第一极Ca)电连接，从而使得第一复位晶体管T6的第二极T62与驱动晶体管T1的栅极T10(也即存储电容Cst的第一极Ca)电连接。第三连接电极CEc的一端通过过孔H32与第二初始化信号线INT2电连接，第三连接电极CEc的另一端通过过孔H31与第二复位晶体管T7的第一极T71相连，进而使得第二复位晶体管T7的第一极T71与第二初始化信号线INT2电连接。第四连接电极CEd通过过孔H40与第二发光控制晶体管T5的第二极T52电连接。第四连接电极CEd可用来与后续形成的第六连接电极CEf相连，进而与发光元件20的第一电极201(参照 图9)电连接。第五连接电极CEe通过过孔H5与数据写入晶体管T2的第一极T21电连接。第五连接电极CEe用于与数据线相连。
图8示出了第四导电图案层LY4。第四导电图案层LY4包括数据线DT、第六连接电极CEf和第一电源线VDD1。第三导电图案层LY3与第四导电图案层LY4之间设有钝化层(钝化层PVX，参照图11)和第一平坦化层(第一平坦化层PLN1，参照图11)。第一电源线VDD1通过贯穿钝化层和第一平坦化层的过孔H6与电源连接线VDD0相连，第六连接电极CEf通过贯穿钝化层和第一平坦化层的过孔H7与第四连接电极CEd相连。数据线DT通过过孔H8与第五连接电极CEe相连，进而与数据写入晶体管T2的第一极T21电连接。例如，第六连接电极CEf(连接电极CEf)和第四连接电极CEd(连接电极CEd)构成连接元件CE0。例如，发光元件20通过连接元件CE0与像素电路10相连。例如，像素电路10与第四连接电极CEd(连接电极CEd)相连，第四连接电极CEd(连接电极CEd)与第六连接电极CEf(连接电极CEf)相连，第六连接电极CEf(连接电极CEf)与发光元件20相连。
图8示出了第一数据线DT1、第二数据线DT2、第三数据线DT3和第四数据线DT4。图8还示出了第一像素单元101a、第二像素单元101b、第三像素单元101c和第四像素单元101d的位置。如图8所示，第一数据线DT1通过过孔H81与对应位置处的第五连接电极CEe相连，第二数据线DT2通过过孔H82与对应位置处的第五连接电极CEe相连，第三数据线DT3通过过孔H83与对应位置处的第五连接电极CEe相连，第四数据线DT4通过过孔H84与对应位置处的第五连接电极CEe相连。
如图9所示，为了避免形成过孔时破坏沟道而影响数据写入晶体管T2的性能，第一栅信号线SL1和第二栅信号线SL2在衬底基板上的正投影与数据写入晶体管T2的沟道区T23在衬底基板上的正投影不交叠。
如图9所示，为了避免形成过孔时破坏沟道而影响阈值补偿晶体管T3的性能，第一栅信号线SL1和第二栅信号线SL2在衬底基板上的正投影与阈值补偿晶体管的沟道区T33在衬底基板上的正投影不交叠。
如图8和图9所示，数据线DT沿第二方向Y延伸，第一数据线DT1、第三数据线DT3、第四数据线DT4和第二数据线DT2沿第一方向X排列。
例如，第一电源线VDD1被配置为向像素电路10提供第一电压信号ELVDD。第一电源线VDD1与挡块BK相连以为挡块BK提供恒定的电压。第一电源线VDD1连接至第一电源端VDD，存储电容Cst的第二极Cb与第一电源线VDD1相连。例如，存储电容Cst的第二极Cb通过电源连接线VDD0以及第一电源线VDD1与第一电源端VDD相连。图9示出了形成第四导电图案层LY4后的结构的平面图。
例如，第一发光控制晶体管T4的第一极T41通过电源连接线VDD0、第一电源线VDD1(参考图9和图10)与第一电源端VDD相连。
如图10所示，阈值补偿晶体管T3为双栅晶体管，阈值补偿晶体管T3包括第一沟道T331和第二沟道T332，第一沟道T331和第二沟道T332通过第一导电连接部CP1相连。 如图10所示，第一复位晶体管T6为双栅晶体管，第一复位晶体管T6包括第一沟道T631和第二沟道T632，第一沟道T631和第二沟道T632通过第二导电连接部CP2相连。
如图10所示，挡块BK被配置为遮挡阈值补偿晶体管T3的两个沟道之间的第一导电连接部CP1，挡块BK与第一导电连接部CP1形成电容(稳定电容)，以避免阈值补偿晶体管T3产生漏电流，避免影响显示效果。如图9所示，在平面图中，挡块BK和第一导电连接部CP1部分交叠。
如图10所示，在平面图中，第一初始化信号线INT1和第二导电连接部CP2部分交叠，第一初始化信号线INT1和第二导电连接部CP2之间形成电容(稳定电容)，以避免第一复位晶体管T6产生漏电流，避免影响显示效果。
参考图3和图9，第一栅线GT1与第一像素单元101a的数据写入晶体管T2的栅极相连；第二栅线GT2与第二像素单元101b的数据写入晶体管T2的栅极相连。
参考图6和图9，第一栅信号线SL1沿第一方向X延伸，与第一像素单元101a相连，并被配置为向第一像素单元101a提供第一扫描信号；第二栅信号线SL2沿第一方向X延伸，与第二像素单元101b相连，并被配置为向第二像素单元101b提供第二扫描信号。
参考图7和图9，第一连接线CL1沿第二方向Y延伸，第一栅线GT1通过第一连接线CL1与第一栅信号线SL1相连；第二连接线CL2沿第二方向Y延伸，第二栅线GT2通过第二连接线CL2与第二栅信号线SL2相连。
本公开的实施例提供的显示面板，可以实现高分辨率下的Dual gate&Dual source技术方案。本公开的实施例提供的显示面板，通过第二导电图案层实现Dual gate信号的横向布线，第三导电图案层中的连接线通过过孔分别连接到第一导电图案层中的栅线和第二导电图案层中的栅信号线，像素布图结构紧凑，有利于实现高PPI。例如，在一些实施例中，实现Dual source&Dual gate技术方案在413PPI高分辨率下的应用。
例如，如图6和图9所示，第一栅信号线SL1和第二栅信号线SL2彼此绝缘，以可分别向同一行像素单元中的相邻两列像素单元输入扫描信号。例如，第一栅信号线SL1用于向奇数列像素单元输入扫描信号，第二栅信号线SL2用于向偶数列像素单元输入扫描信号。
例如，如图5和图9所示，第一栅线GT1和第二栅线GT2彼此分离，并沿第一方向X排列。例如，同一行像素单元中，相邻两个第一栅线GT1之间设有一个第二栅线GT2，相邻两个第二栅线GT2之间设有一个第一栅线GT1。例如，如图5和图9所示，第一栅线GT1沿第一方向X延伸，第二栅线GT2沿第一方向X延伸。在本公开的实施例中，部件沿某一方向延伸是指该部件的整体延伸趋势，不一定该部件的每个部分都是沿着该延伸方向延伸。
例如，如图7和图9所示，第二栅信号线SL2比第一栅信号线SL1更靠近第一栅线GT1，第一连接线CL1沿第二方向Y的长度大于第二连接线CL2沿第二方向Y的长度。
例如，参考图5、图6、图7和图9，第一栅线GT1、第一连接线CL1、第一栅信号线SL1位于三个不同的层，并且第二栅线GT2、第二连接线CL2和第二栅信号线SL2位 于三个不同的层。
例如，参考图5、图6、图7和图9，第一栅线GT1和第二栅线GT2位于同一层，第一连接线CL1和第二连接线CL2位于同一层，并且第一栅信号线SL1和第二栅信号线SL2位于同一层。
例如，参考图5、图6、图7、图9、图11和图13，第一栅线GT1和第二栅线GT2位于第一导电图案层LY1；第一栅信号线SL1和第二栅信号线SL2位于第二导电图案层LY2；第一连接线CL1和第二连接线CL2位于第三导电图案层LY3；第一导电图案层LY1比第二导电图案层LY2更靠近衬底基板BS，第二导电图案层LY2比第三导电图案层LY3更靠近衬底基板BS。
例如，参考图11和图13，显示面板还包括第一栅绝缘层GI1、第二栅绝缘层GI2和层间绝缘层ILD；第一导电图案层LY1位于第一栅绝缘层GI1上，第一导电图案层LY1和第二导电图案层LY2之间设有第二栅绝缘层GI2，层间绝缘层ILD位于第二导电图案层LY2上，第三导电图案层LY3位于层间绝缘层ILD上。
例如，参考图7和图9，第一连接线CL1的一端通过贯穿第二栅绝缘层GI2和层间绝缘层ILD的第一过孔V1与第一栅线GT1相连，第一连接线CL1的另一端通过贯穿层间绝缘层ILD的第二过孔V2与第一栅信号线SL1相连；第二连接线CL2的一端通过贯穿第二栅绝缘层GI2和层间绝缘层ILD的第三过孔V3与第二栅线GT2相连，第二连接线CL2的另一端通过贯穿层间绝缘层ILD的第四过孔V4与第二栅信号线SL2相连。
例如，如图9所示，第一像素单元101a的阈值补偿晶体管T3的栅极与第一栅线GT1相连，第二像素单元101b的阈值补偿晶体管T3的栅极与第二栅线GT2相连，阈值补偿晶体管T3的第一极与驱动晶体管T1的第二极相连，阈值补偿晶体管T3的第二极与驱动晶体管T1的栅极相连。
例如，如图9所示，第一栅信号线SL1和第二栅信号线SL2位于阈值补偿晶体管T3和第一复位晶体管T6之间，从而第一栅信号线SL1和第二栅信号线SL2在第二方向上的位置得以限定。
如图8所示，第六连接电极CEf在第二方向Y上的长度比通常的连接电极的长度大。如图8所示，第六连接电极CEf在第二方向Y上的长度大于第六连接电极CEf在第一方向X上的长度。例如，第六连接电极CEf在第二方向Y上的长度大于第六连接电极CEf在第一方向X上的最大长度的2-5倍，在一些实施例中，第六连接电极CEf在第二方向Y上的长度大于第六连接电极CEf在第一方向X上的最大长度的3倍、4倍或五倍。图8所示的第六连接电极CEf可称作屏蔽部CEs。屏蔽部CEs和第四连接电极CEd(连接电极CEd)构成连接元件CE0。
参考图7、图9和图10，第二连接电极CEb的一端通过过孔H21与驱动晶体管T1的栅极T10(也即存储电容Cst的第一极Ca)电连接，第二连接电极CEb的另一端通过过孔H22与第一复位晶体管T6的第二极T62电连接，第二连接电极CEb也可称作第三连接线CL3。如图11所示，驱动晶体管T1的栅极T10通过第三连接线CL3与阈值补偿 晶体管T3的第二极T32相连。
参考图8、图9和图10，屏蔽部CEs沿第二方向Y延伸。例如，发光元件20通过连接元件CE0(包括第四连接电极CEd和屏蔽部CEs)与像素电路10相连。
参考图8和图9，数据线DT与屏蔽部CEs位于同一层，数据线DT与屏蔽部CEs均位于第四导电图案层LY4。数据线DT包括两条相邻数据线DT，屏蔽部CEs位于两条相邻数据线DT之间，屏蔽部CEs在衬底基板BS上的正投影与第三连接线CL3在衬底基板BS上的正投影至少部分交叠。参考图8和图9，数据线DT包括第一数据线DT1和第三数据线DT3，第一数据线DT1和第三数据线DT3相邻，在第一方向X上，屏蔽部CEs位于第一数据线DT1和第三数据线DT3之间。在本公开的实施例中，部件A和部件B相邻是指部件A和部件B之间不具有部件A，也不具有部件B。屏蔽部CEs沿第二方向延伸，穿插在两条相邻数据线DT之间，在相邻数据线距离较近的位置，屏蔽效果更明显。
例如，在一些实施例中，第三连接线CL3在衬底基板BS上的正投影完全落入屏蔽部CEs在衬底基板BS上的正投影内。
例如，在一些实施例中，参考图8和图9，第一连接线CL1在衬底基板BS上的正投影与屏蔽部CEs在衬底基板BS上的正投影不交叠。参考图8和图9，第二连接线CL2在衬底基板BS上的正投影与屏蔽部CEs在衬底基板BS上的正投影不交叠。
如图10所示，显示面板包括第一导电结构CDT1，第一导电结构CDT1与驱动晶体管T1的栅极T10相连。
例如，第一导电结构CDT1的材料与第一导电连接部CP1的材料相同。例如，第一导电结构CDT1与第一导电连接部CP1可由同一膜层经同一工艺制作而成。
例如，第一导电结构CDT1的材料包括半导体材料经掺杂而得的导电材料。例如，第一导电结构CDT1的材料包括多晶硅经掺杂而得的导电材料，但不限于此。
例如，如图10所示，第一导电结构CDT1复用为第一复位晶体管T6的第二极T62。在本公开的实施例中，以第一导电结构CDT1作为第一复位晶体管T6的第二极T62为例进行说明。
例如，如图10所示，第一导电结构CDT1、第三连接线CL3和驱动晶体管T1的栅极T10构成驱动晶体管T1的栅信号部PT1。
例如，如图10所示，屏蔽部CEs在衬底基板BS上的正投影与栅信号部PT1在衬底基板BS上的正投影至少部分交叠，使得屏蔽部CEs屏蔽栅信号部PT1与数据线之间的寄生电容，减轻纵向串扰问题。
在本公开的实施例中，屏蔽部CEs在衬底基板BS上的正投影与第三连接线CL3在衬底基板BS上的正投影至少部分交叠，使得屏蔽部CEs屏蔽栅信号部PT1(栅极点)与数据线之间的寄生电容，减轻纵向串扰问题。
例如，采用120Hz的驱动方案采用分时写入方式，即数据信号先存储到存储电容中，然后扫描信号开启再写入像素单元中，数据信号之间的干扰会影响数据信号的准确写入，影响显示效果。在本公开的实施例中，屏蔽部CEs位于两条相邻数据线DT之间，第三连 接线CL3在衬底基板BS上的正投影与屏蔽部CEs在衬底基板BS上的正投影至少部分交叠，可以很好的减少耦合影响，改善这一问题。
例如，如图9和图10所示，为了最大限度的减轻纵向串扰，屏蔽部CEs在衬底基板BS上的正投影大于第三连接线CL3在衬底基板BS上的正投影。例如，屏蔽部CEs在衬底基板BS上的正投影的面积大于第三连接线CL3在衬底基板BS上的正投影的面积。例如，屏蔽部CEs在衬底基板BS上的正投影覆盖第三连接线CL3在衬底基板BS上的正投影。例如，在平面图中，屏蔽部CEs覆盖第三连接线CL3。例如，如图9和图10所示，衬底基板BS的主表面为用于制作各个部件的表面，各部件设置在衬底基板BS的主表面上。
例如，为了较大程度地减轻纵向串扰，驱动晶体管T1的栅极T10在衬底基板BS上的正投影与屏蔽部CEs在衬底基板BS上的正投影部分交叠，屏蔽部CEs与驱动晶体管T1的栅极T10的交叠部分的面积小于驱动晶体管T1的栅极T10的面积。
例如，如图9和图10所示，为了提高显示质量，驱动晶体管T1的栅极T10在第一方向X上的尺寸大于屏蔽部CEs在第一方向X上的尺寸；屏蔽部CEs在第二方向Y上的尺寸大于驱动晶体管T1的栅极在第二方向Y上的尺寸。
例如，如图9和图10所示，驱动晶体管T1的栅极T10在第一方向X上从两侧分别超出屏蔽部CEs。
例如，如图9和图10所示，屏蔽部CEs在衬底基板BS上的正投影与栅线GT在衬底基板BS上的正投影交叠。栅线GT可包括第一栅线GT1或第二栅线GT2。
例如，如图9所示，第一栅线GT1或第二栅线GT2在衬底基板BS的上的正投影与屏蔽部CEs在衬底基板BS的上的正投影部分交叠。
例如，像素单元包括位于同一列且相邻的两个像素单元，两条相邻的数据线DT分别与两个像素单元相连。图9示出了第一像素单元101a、第二像素单元101b、第三像素单元101c和第四像素单元101d的位置。
例如，如图9和图10所示，第一复位晶体管T6的第二极T62通过第三连接线CL3与驱动晶体管T1的栅极T10相连。如前所述，第一复位晶体管T6的第二极T62与阈值补偿晶体管T3的第二极T32一体形成，从而，阈值补偿晶体管T3的第二极T32与驱动晶体管T1的栅极T10相连。
例如，如图9和图10所示，屏蔽部CEs在衬底基板BS的上的正投影与第一复位晶体管T6的第二极T62在衬底基板BS的上的正投影至少部分交叠。同样，因第一复位晶体管T6的第二极T62与阈值补偿晶体管T3的第二极T32一体形成，屏蔽部CEs在衬底基板BS的上的正投影与阈值补偿晶体管T3的第二极T32在衬底基板BS的上的正投影至少部分交叠。
例如，如图9和图10所示，屏蔽部CEs在衬底基板BS的上的正投影与第二栅信号线SL2在衬底基板BS的上的正投影不交叠，从而，屏蔽部CEs在第二方向Y上的上端位置得以限定。
例如，参考图9和图10，第一初始化信号线INT1和第二初始化信号线INT2分设在驱动晶体管T1的栅极T10的相对的两侧，屏蔽部CEs在衬底基板BS的上的正投影与第二初始化信号线INT2在衬底基板BS的上的正投影部分交叠。
进一步例如，第二初始化信号线INT2在衬底基板BS的上的正投影与下一行的像素单元的第二导电连接部CP2在衬底基板BS的上的正投影部分交叠，从而，第二初始化信号线INT2与屏蔽部CEs之间形成电容，该电容作为稳定电容，起到减少第一复位晶体管T6的漏电流的作用。
例如，参考图9，第一复位控制信号线RT1和第二复位控制信号线RT2分设在驱动晶体管T1的栅极T10的相对的两侧，参考图9，第二复位控制信号线RT2在衬底基板BS的上的正投影和屏蔽部CEs在衬底基板BS的上的正投影不交叠。从而，屏蔽部CEs在第二方向Y上的下端位置得以限定。
例如，参考图9和图10，第一复位控制信号线RT1在衬底基板BS的上的正投影和屏蔽部CEs在衬底基板BS的上的正投影不交叠。
例如，参考图9和图10，第一复位控制信号线沿第一方向X延伸，第二复位控制信号线沿第一方向X延伸。
在图9中，每个第六连接电极CEf与一个发光元件相连，即，每个第六连接电极CEf对应一个像素单元101。或者说，在图9中，每个屏蔽部CEs与一个发光元件相连，即，每个屏蔽部CEs对应一个像素单元101。
例如，参考图9，第一复位晶体管T6的第一栅极T601和第二栅极T602在衬底基板BS上的正投影与第一复位晶体管T6的第一沟道T631和第二沟道T632在衬底基板BS上的正投影分别交叠。例如，参考图9，阈值补偿晶体管T3的第一栅极T301和第二栅极T302在衬底基板BS上的正投影与阈值补偿晶体管T3的第一沟道T331和第二沟道T332在衬底基板BS上的正投影分别交叠。
例如，如图9所示，第一电源线VDD1通过电源连接线VDD0与存储电容Cst的第二极Cb相连。
通常技术中，阈值补偿晶体管T3为双栅晶体管，阈值补偿晶体管T3的中间节点(第一导电连接部CP1)会受到扫描信号的跳变扰动，在扫描信号关断瞬间电压增高，向驱动晶体管T1的栅极漏电加剧，会导致闪烁(Flicker)问题。
例如，参考图9，为了减轻阈值补偿晶体管T3的漏电，挡块BK在衬底基板BS上的正投影与第一导电连接部CP1在衬底基板BS上的正投影至少部分交叠。挡块BK与第一导电连接部CP1之间形成稳定电容。增加阈值补偿晶体管T3的中间节点与第一电压信号ELVDD的寄生电容，可以降低扰动量，改善漏电问题。
在衬底基板上形成像素电路，形成图9或图10所示的显示面板，在图9或图10所示的显示面板的基础上，再形成发光元件，得到可以进行显示的显示面板，从而，像素电路比发光元件更靠近衬底基板。如图13所示，像素电路10比发光元件20更靠近所述衬底基板BS。
图12示出了发光元件20的第一极201。图13为本公开一实施例提供的显示面板的剖视图。图12中省略了发光元件的第一极201之上的膜层。发光元件20的第一极201以上的各层可参照截面图。当然，发光元件的第一极201的设置位置和形状不限于图12所示，本领域技术人员可以根据需要调整发光元件的第一极201的设置位置和形状。
参考图12和图13，缓冲层BL位于衬底基板BS上，隔离层BR位于缓冲层BL上，晶体管的沟道区、源极和漏极位于隔离层BR上，在晶体管的沟道区、源极和漏极上形成第一栅绝缘层GI1，第一导电图案层LY1位于第一栅绝缘层GI1上，第二栅绝缘层GI2位于第一导电图案层LY1上，第二导电图案层LY2位于第二栅绝缘层GI2上，层间绝缘层ILD位于第二导电图案层LY2上，第三导电图案层LY3位于层间绝缘层ILD上，钝化层PVX位于第一导电图案层LY上，第一平坦化层PLN1位于钝化层PVX上，第四导电图案层LY4位于第一平坦化层PLN1上。
参考图13，第二平坦化层PLN2位于第四导电图案层LY4上，发光元件20的第一极201位于第二平坦化层PLN2上，像素定义层PDL以及隔垫物PS位于第二平坦化层PLN2上，像素定义层PDL具有开口OPN，开口OPN被配置为限定像素单元的发光面积(出光区域，有效发光面积)。隔垫物PS被配置为在形成发光功能层203时支撑精细金属掩膜。
例如，如图12和图13所示，开口OPN为像素单元的出光区域。发光功能层203位于发光元件20的第一极201之上，发光元件20的第二极202位于发光功能层203上，光元件20上设置封装层CPS。封装层CPS包括第一封装层CPS1、第二封装层CPS2以及第三封装层CPS3。例如，第一封装层CPS1和第三封装层CPS3为无机材料层，第二封装层CPS2为有机材料层。例如，第一极201为发光元件20的阳极，第二电极202为发光元件20的阴极，但不限于此。
如图12和图13所示，发光元件20的第一极201通过贯穿第二平坦化层PLN2的过孔H9与屏蔽部CEs(第六连接电极CEf)相连。
例如，发光元件20包括有机发光二极管。发光功能层203位于第二极202和第一极201之间。第二极202位于第一极201的远离衬底基板BS的一侧，发光功能层203至少包括发光层，还可以包括空穴传输层、空穴注入层，电子传输层、电子注入层至少之一。
如图图6和图13所示，存储电容的第二极Cb具有开口OPN1，开口OPN1的设置利于第二连接电极CEb与驱动晶体管T1的栅极T10相连。
例如，本公开的实施例的像素电路中的晶体管均为薄膜晶体管。例如，第一导电图案层LY1、第二导电图案层LY2、第三导电图案层LY3、第四导电图案层LY4均采用金属材料制作。例如，第一导电图案层LY1和第二导电图案层LY2采用镍、铝等金属材料形成，但不限于此。例如，第三导电图案层LY3和第四导电图案层LY4采用钛、铝等材料形成，但不限于此。例如，第三导电图案层LY3和第四导电图案层LY4分别为Ti/AL/Ti三个子层形成的结构，但不限于此。例如，衬底基板可以采用玻璃基板或聚酰亚胺基板，但不限于此，可根据需要进行选择。例如，第一栅绝缘层GI1、第二栅绝缘层GI2、层间 绝缘层ILD、钝化层PVX、第一平坦化层PLN1、第二平坦化层PLN2、像素定义层PDL、隔垫物PS均采用绝缘材料制作。发光元件的第一极201和第二极202的材料可根据需要进行选取。一些实施例中，第一极201可采用透明导电金属氧化物和银至少之一，但不限于此。例如，透明导电金属氧化物包括氧化铟锡(ITO)，但不限于此。例如，第一极201可采用ITO-Ag-ITO三个子层叠层设置的结构。一些实施例中，第二极202可以为低功函的金属，可采用镁和银至少之一，但不限于此。
在本公开的实施例提供的显示面板中，也可以不设置如图16所示的屏蔽部CEs。而是采用在第二方向上长度较小的连接电极。即，第六连接电极CEf/屏蔽部CEs可以采用其他大小和形状。
在本公开的实施例中，数据写入晶体管T2可称作第一晶体管，阈值补偿晶体管T3可称作第二晶体管。
例如，在与驱动晶体管T1的栅极直接连接的阈值补偿晶体管T3和第一复位晶体管T6为金属氧化物半导体薄膜晶体管的情况(采用LTPO工艺)下，第一栅信号线SL1和第二栅信号线SL2中的至少之一可以输出N型晶体管的导通信号；第一栅线GT1和第二栅线GT2选用的膜层不限于第一导电图案层LY1，第一栅信号线SL1和第二栅信号线SL2选用的膜层不限于第二导电图案层LY2，也可以是其他金属膜层，如第二导电图案层LY2上方的金属膜层，例如第三导电图案层LY3，该层同时可以作为氧化物TFT的栅极等；也可以用氧化物半导体经过导体化工艺，作为连接线，或者转接结构等。
本公开至少一实施例还提供一种显示装置，包括上述任一项显示面板。例如，显示装置包括OLED或包括OLED的高帧频驱动的产品。例如，显示装置包括含有上述显示面板的电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件。
以上以7T1C的像素电路为例进行说明，本公开的实施例包括但不限于此。需要说明的是，本公开的实施例对像素电路包括的薄膜晶体管的个数以及电容的个数不做限定。例如，在另外的一些实施例中，显示面板的像素电路还可以为包括其他数量的晶体管的结构，如7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开实施例对此不作限定。
在本公开的实施例中，位于同一层的元件可由同一膜层经同一构图工艺行程。例如，位于同一层的元件可位于同一个元件的远离衬底基板的表面上。
需要说明的是，为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在本公开的实施例中，构图或构图工艺可只包括光刻工艺，或包括光刻工艺以及刻蚀步骤，或者可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺是指包括成膜、曝光、显影等工艺过程，利用光刻胶、掩模板、曝光机等形成图形。可根据本公开的实施例中所形成的结构选择相应的构图工艺。
在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种显示面板，包括：
    像素单元，包括像素电路和发光元件，所述像素电路被配置为驱动所述发光元件，所述像素电路包括第一晶体管，所述像素单元包括位于同一行且位于相邻列的第一像素单元和第二像素单元；
    第一栅线，与所述第一像素单元的所述第一晶体管的栅极相连；
    第二栅线，与所述第二像素单元的所述第一晶体管的栅极相连；
    第一栅信号线，沿第一方向延伸，与所述第一像素单元相连，并被配置为向所述第一像素单元提供第一扫描信号；
    第二栅信号线，沿所述第一方向延伸，与所述第二像素单元相连，并被配置为向所述第二像素单元提供第二扫描信号；
    第一连接线，沿第二方向延伸，所述第一栅线通过所述第一连接线与所述第一栅信号线相连；以及
    第二连接线，沿所述第二方向延伸，所述第二栅线通过所述第二连接线与所述第二栅信号线相连，所述第二方向与所述第一方向相交。
  2. 根据权利要求1所述的显示面板，其中，所述第一栅信号线和所述第二栅信号线彼此绝缘。
  3. 根据权利要求1或2所述的显示面板，其中，所述第一栅线和所述第二栅线彼此分离，并沿所述第一方向排列。
  4. 根据权利要求1-3任一项所述的显示面板，其中，所述第二栅信号线比所述第一栅信号线更靠近所述第一栅线。
  5. 根据权利要求1-4任一项所述的显示面板，其中，所述第一栅信号线和所述第二栅信号线在衬底基板上的正投影与所述第一晶体管的沟道区在所述衬底基板上的正投影不交叠。
  6. 根据权利要求1-5任一项所述的显示面板，其中，所述第一栅线、所述第一连接线、所述第一栅信号线位于三个不同的层，并且所述第二栅线、所述第二连接线和所述第二栅信号线位于三个不同的层。
  7. 根据权利要求6所述的显示面板，其中，所述第一栅线和所述第二栅线位于同一层，所述第一连接线和所述第二连接线位于同一层，并且所述第一栅信号线和所述第二栅信号线位于同一层。
  8. 根据权利要求6或7所述的显示面板，其中，
    所述第一栅线和所述第二栅线位于第一导电图案层；
    所述第一栅信号线和所述第二栅信号线位于第二导电图案层；
    所述第一连接线和所述第二连接线位于第三导电图案层；
    所述第一导电图案层比所述第二导电图案层更靠近衬底基板，所述第二导电图案层比 所述第三导电图案层更靠近所述衬底基板。
  9. 根据权利要求6-8任一项所述的显示面板，还包括第一栅绝缘层、第二栅绝缘层和层间绝缘层，
    所述第一导电图案层位于所述第一栅绝缘层上，所述第一导电图案层和所述第二导电图案层之间设有所述第二栅绝缘层，所述层间绝缘层位于所述第二导电图案层上，所述第三导电图案层位于所述层间绝缘层上；
    所述第一连接线的一端通过贯穿所述第二栅绝缘层和所述层间绝缘层的第一过孔与所述第一栅线相连，所述第一连接线的另一端通过贯穿所述层间绝缘层的第二过孔与所述第一栅信号线相连；
    所述第二连接线的一端通过贯穿所述第二栅绝缘层和所述层间绝缘层的第三过孔与所述第二栅线相连，所述第二连接线的另一端通过贯穿所述层间绝缘层的第四过孔与所述第二栅信号线相连。
  10. 根据权利要求9所述的显示面板，其中，所述像素电路还包括驱动晶体管和第二晶体管；
    所述第一像素单元的所述第二晶体管的栅极与所述第一栅线相连，所述第二像素单元的所述第二晶体管的栅极与所述第二栅线相连，
    所述第二晶体管的第一极与所述驱动晶体管的第二极相连，所述第二晶体管的第二极与所述驱动晶体管的栅极相连。
  11. 根据权利要求10所述的显示面板，还包括第一电源端和数据线，其中，所述第一电源端被配置为向所述像素电路提供第一电压信号，所述数据线被配置为向所述像素电路提供数据信号；
    所述像素电路还包括存储电容；所述第一晶体管的第一极与所述数据线相连，所述驱动晶体管的第一极与所述第一晶体管的第二极相连；
    所述存储电容的第一极与所述驱动晶体管的栅极相连，所述存储电容的第二极与所述第一电源端相连。
  12. 根据权利要求10或11所述的显示面板，其中，所述第一栅信号线和所述第二栅信号线在衬底基板上的正投影与所述第二晶体管的沟道区在所述衬底基板上的正投影不交叠。
  13. 根据权利要求10-12任一项所述的显示面板，还包括初始化信号线，其中，所述初始化信号线被配置为向所述像素电路提供初始化信号，
    所述像素电路还包括第一复位晶体管；所述第一复位晶体管的第一极与所述初始化信号线相连，所述第一复位晶体管的第二极与所述驱动晶体管的栅极相连。
  14. 根据权利要求13所述的显示面板，其中，所述第一栅信号线和所述第二栅信号线位于所述第二晶体管和所述第一复位晶体管之间。
  15. 根据权利要求10-14任一项所述的显示面板，其中，所述像素单元还包括与所述第一像素单元位于同一列的第三像素单元，所述数据线包括第一数据线、第二数据线和第 三数据线，所述第一数据线与所述第一像素单元相连，所述第二数据线与所述第二像素单元相连，所述第三数据线与所述第三像素单元相连。
  16. 根据权利要求10-15任一项所述的显示面板，其中，所述像素单元还包括与第二像素单元位于同一列的第四像素单元，所述数据线包括第四数据线，所述第四数据线与所述第四像素单元相连。
  17. 根据权利要求1-9任一项所述的显示面板，还包括连接元件，其中，所述发光元件通过所述连接元件与所述像素电路相连，所述连接元件包括屏蔽部，所述屏蔽部沿所述第二方向延伸；
    所述数据线与所述屏蔽部位于同一层，所述数据线包括两条相邻数据线，所述屏蔽部位于所述两条相邻数据线之间，所述第一连接线在所述衬底基板上的正投影与所述屏蔽部在所述衬底基板上的正投影不交叠。
  18. 根据权利要求17所述的显示面板，其中，所述像素电路包括驱动晶体管和第二晶体管，所述第二晶体管的第一极与所述驱动晶体管的第二极相连，所述第二晶体管的第二极与所述驱动晶体管的栅极相连；
    所述显示面板还包括第三连接线，所述驱动晶体管的栅极通过所述第三连接线与所述第二晶体管的第二极相连，
    所述屏蔽部在所述衬底基板上的正投影的面积大于所述第三连接线在所述衬底基板上的正投影的面积。
  19. 根据权利要求17所述的显示面板，其中，所述驱动晶体管的栅极在所述衬底基板上的正投影与所述屏蔽部在所述衬底基板上的正投影部分交叠，所述屏蔽部与所述驱动晶体管的栅极的交叠部分的面积小于所述驱动晶体管的栅极的面积。
  20. 根据权利要求17-19任一项所述的显示面板，其中，所述驱动晶体管的栅极在所述第一方向上的尺寸大于所述屏蔽部在所述第一方向上的尺寸；
    所述屏蔽部在所述第二方向上的尺寸大于所述驱动晶体管的栅极在所述第二方向上的尺寸。
  21. 根据权利要求17-19任一项所述的显示面板，其中，所述屏蔽部在所述衬底基板上的正投影与所述第一栅线或所述第二栅线在所述衬底基板上的正投影交叠。
  22. 一种显示装置，包括根据权利要求1-21任一项所述的显示面板。
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