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WO2022085151A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2022085151A1
WO2022085151A1 PCT/JP2020/039707 JP2020039707W WO2022085151A1 WO 2022085151 A1 WO2022085151 A1 WO 2022085151A1 JP 2020039707 W JP2020039707 W JP 2020039707W WO 2022085151 A1 WO2022085151 A1 WO 2022085151A1
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WO
WIPO (PCT)
Prior art keywords
region
semiconductor layer
semiconductor device
semiconductor
impurity concentration
Prior art date
Application number
PCT/JP2020/039707
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English (en)
French (fr)
Inventor
慎一 田渕
保夫 阿多
Original Assignee
三菱電機株式会社
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Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to US18/000,232 priority Critical patent/US20230207681A1/en
Priority to JP2022556327A priority patent/JP7509225B2/ja
Priority to PCT/JP2020/039707 priority patent/WO2022085151A1/ja
Priority to DE112020007709.8T priority patent/DE112020007709T5/de
Priority to CN202080106313.9A priority patent/CN116325170A/zh
Publication of WO2022085151A1 publication Critical patent/WO2022085151A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Definitions

  • This disclosure relates to semiconductor devices.
  • Patent Document 1 discloses a semiconductor device including an n-type substrate which is a hexagonal semiconductor substrate containing silicon carbide. A semiconductor layer including an n-type drift layer is formed on the substrate. In the termination region surrounding the element region, a p-type first semiconductor region is formed on the upper surface of the semiconductor layer. A silicide layer is formed on the upper surface of the first semiconductor region. The contact plug is connected to the first semiconductor region via the silicide layer.
  • the first semiconductor region includes a first extending portion extending in the first direction, a second extending portion extending in the second direction, a third extending portion extending in the third direction, and a third extending portion. It has an annular structure in which a fourth extending portion extending in four directions is connected.
  • Patent Document 1 the distribution of the pn current flowing in the terminal region is improved, and the expansion of stacking defects is suppressed.
  • the hole density in the active region is not considered, and it may not be possible to sufficiently suppress the deterioration of the electrical characteristics.
  • the object of the present disclosure is to obtain a semiconductor device capable of suppressing deterioration of electrical characteristics.
  • the semiconductor device includes a semiconductor layer having an active region in which a MOSFET is formed, a terminal region surrounding the active region in a plan view, a gate electrode provided on the upper surface of the semiconductor layer, and the semiconductor.
  • a source electrode provided on the upper surface of the layer and a drain electrode provided on a surface opposite to the upper surface of the semiconductor layer are provided, and the semiconductor layer includes a first conductive type first semiconductor layer and the first semiconductor layer.
  • a second semiconductor layer which is provided on the upper surface of one semiconductor layer and is the first conductive type and has a lower impurity concentration than the first semiconductor layer, and is provided on the upper surface side of the second semiconductor layer in the active region.
  • It is a conductive type and includes a high concentration region having a higher impurity concentration than the well region, the gate electrode is provided directly above the well region, and the source electrode is provided with the source region and the high concentration region. Electrically connected, the impurity concentration of the first semiconductor layer is 4 ⁇ 10 18 cm -3 or more, and the thickness is 4 ⁇ m or more.
  • the hole density in the active region can be suppressed, and the deterioration of the electrical characteristics of the semiconductor device can be suppressed.
  • FIG. 1 is a cross-sectional view taken along the line AA of FIG. It is BB sectional view of FIG. It is a figure explaining the relationship between the 1st semiconductor layer and the hole density. It is a top view of the semiconductor device which concerns on Embodiment 2.
  • FIG. 5 is a sectional view taken along the line CC of FIG.
  • FIG. 1 is a plan view of the semiconductor device 100 according to the first embodiment.
  • the n-type is the first conductive type
  • the p-type is the second conductive type.
  • the n-type may be the second conductive type and the p-type may be the first conductive type.
  • the active region indicates a region in which the main current of the semiconductor device flows.
  • the terminal region indicates a region provided around the active region.
  • a part of the electrode and the insulating film is omitted.
  • the semiconductor device 100 is rectangular in a plan view.
  • the semiconductor device 100 constitutes a semiconductor chip.
  • an active region 101 in which a SiC- MOSFET (Metal-Oxide-Semiconductor Field-Effective Transistor) is formed is provided in the central portion of the semiconductor device 100.
  • a terminal region 102 is provided on the outer peripheral portion of the semiconductor device 100.
  • a gate wiring 25 is provided in the terminal region 102 so as to surround the active region 101.
  • a p-type high concentration region 20 is provided so as to surround the active region 101.
  • the unit cell UC is represented in the area 80 for convenience. In the actual device structure, a plurality of unit cells UC are provided in the active region 101. The source regions of the plurality of unit cells UC are electrically connected in parallel.
  • FIG. 2 is a sectional view taken along the line AA of FIG.
  • FIG. 3 is a cross-sectional view taken along the line BB of FIG.
  • the semiconductor device 100 includes a semiconductor layer 11, a plurality of gate electrodes 24 provided on the upper surface of the semiconductor layer 11, a source electrode 28 provided on the upper surface of the semiconductor layer 11, and a surface opposite to the upper surface of the semiconductor layer 11.
  • the drain electrode 30 provided in the above is provided.
  • the semiconductor layer 11 has an active region 101 on which a MOSFET is formed and a terminal region 102 surrounding the active region 101 in a plan view.
  • the semiconductor layer 11 is formed of silicon carbide.
  • the semiconductor layer 11 has a substrate 10 containing n-type impurities and formed of SiC.
  • the first semiconductor layer 12 is provided on the upper surface of the substrate 10.
  • the first semiconductor layer 12 is an epitaxial growth layer containing n + type impurities.
  • the first semiconductor layer 12 has a higher concentration than the substrate 10.
  • the impurity concentration of the first semiconductor layer 12 is, for example, 4 ⁇ 10 18 cm -3 or more, and the thickness is 4 ⁇ m or more.
  • the first semiconductor layer 12 has a function as a buffer layer.
  • a second semiconductor layer 14 having a lower impurity concentration than the first semiconductor layer 12 is provided on the upper surface of the first semiconductor layer 12.
  • the second semiconductor layer 14 is an epitaxial growth layer containing n-type impurities.
  • a p-type well region 16 is provided on the upper surface side of the second semiconductor layer 14.
  • the impurity concentration of the well region 16 is, for example, 1 ⁇ 10 18 cm -3 .
  • a plurality of well regions 16 are selectively provided on the outermost surface of the second semiconductor layer 14.
  • An n-type source region 18 is provided on the upper surface side of the well region 16.
  • a p-type high concentration region 20 is provided between the adjacent source regions 18.
  • the high concentration region 20 is also called a well contact region.
  • the impurity concentration in the high concentration region 20 is, for example, 1 ⁇ 10 20 cm -3 .
  • the well region 16 is provided on the upper surface side of the second semiconductor layer 14.
  • a high concentration region 20 which is p-type and has a higher impurity concentration than the well region 16 is provided on the upper surface side of the well region 16.
  • the high-concentration region 20 of the active region 101 and the high-concentration region 20 of the terminal region 102 are the same layer.
  • the high concentration region 20 is formed simultaneously in the active region 101 and the terminal region 102.
  • a withstand voltage holding region 32 is provided on the upper surface side of the second semiconductor layer 14 in the terminal region 102.
  • the impurity concentration of the pressure resistance holding region 32 is, for example, 1 ⁇ 10 18 cm -3 .
  • the high concentration region 20 has a higher impurity concentration than the pressure resistance holding region 32.
  • the pressure resistance holding region 32 is provided on the outer periphery of the well region 16 in the terminal region 102. The arrangement of the withstand voltage holding region 32 and the impurity concentration are changed depending on the required withstand voltage class.
  • a gate insulating film 22 is provided on the upper surface of the second semiconductor layer 14.
  • the gate insulating film 22 is provided from the upper surface of the portion of the second semiconductor layer 14 sandwiched between the well regions 16 to the upper surface of the edge portion of the source region 18 through the upper surface of the well region 16.
  • a gate electrode 24 is provided on the gate insulating film 22.
  • the gate electrode 24 is provided directly above the portion of the second semiconductor layer 14, sandwiched between the well regions 16, the well region 16, and the source region 18.
  • the gate insulating film 22 and the gate electrode 24 are covered with the interlayer insulating film 26.
  • the interlayer insulating film 26 is covered with the source electrode 28.
  • the source electrode 28 is in contact with and electrically connected to the portion of the source region 18 that is not covered with the interlayer insulating film 26 and the high concentration region 20.
  • the gate electrode 24 is provided directly above the high concentration region 20 via the insulating film.
  • one of the plurality of gate electrodes 24 is provided in the portion of the second semiconductor layer 14 sandwiched between the well region 16 and the withstand voltage holding region 32, directly above the well region 16 and the high concentration region 20. Be done.
  • the source electrode 28 is extended to the terminal region 102. In the terminal region 102, the source electrode 28 is in contact with the portion of the high concentration region 20 that is not covered with the interlayer insulating film 26 and is electrically connected. The source electrode 28 is electrically connected to the high concentration region 20 by passing between the gate electrodes 24 provided above the termination region 102 and adjacent to each other.
  • the semiconductor device 100 When the main current is energized in the semiconductor device 100, a current flows from the drain electrode 30 toward the source electrode 28. At this time, the semiconductor device 100 operates as a MOSFET. Further, when the reverse current is energized, a current flows from the source electrode 28 toward the drain electrode 30. At this time, the semiconductor device 100 operates as a PN diode.
  • the PN diode that parasitizes inside the semiconductor device 100 is also called a body diode.
  • BPD Basal Plane Dislocation
  • the p-type high concentration region 20 is provided in the terminal region 102.
  • a region having a high hole density that causes expansion of crystal defects can be formed in the terminal region 102, and a hole current can be easily passed through the terminal region 102. Therefore, it is possible to suppress the expansion of crystal defects to the active region 101 and suppress the deterioration of the electrical characteristics of the semiconductor device 100.
  • the high concentration region 20 comes into contact with the source electrode 28.
  • a PN diode different from the active region 101 can be formed in the terminal region 102, and the current path from the source electrode 28 can be concentrated in the terminal region 102. Therefore, the region where the Hall current flows can be further limited.
  • FIG. 4 is a diagram illustrating the relationship between the first semiconductor layer 12 and the hole density.
  • FIG. 4 shows a simulation result of the hole density around the boundary between the active region 101 and the terminal region 102 when a reverse current is passed through the semiconductor device 100.
  • the region where X is positive is the terminal region 102, and the region where X is negative is the active region 101.
  • the hole density indicates the hole density in the vicinity of the interface with the first semiconductor layer 12 in the substrate 10.
  • the solid line in FIG. 4 shows the results when the impurity concentration of the first semiconductor layer 12 is 4 ⁇ 10 18 cm -3 and the thickness is 4 ⁇ m.
  • the broken line in FIG. 4 shows the result when the impurity concentration of the first semiconductor layer 12 is 1 ⁇ 10 18 cm -3 and the thickness is 1 ⁇ m.
  • the impurity concentration of the first semiconductor layer 12 is 4 ⁇ 10 18 cm -3 and the thickness is 4 ⁇ m
  • the impurity concentration is 1 ⁇ 10 18 cm -3 and the thickness is 1 ⁇ m.
  • the hole density in the active region 101 can be reduced as compared to the case.
  • the first semiconductor layer 12 has a function of damming the Hall current flowing with the current during operation of the PN diode in the active region 101. Therefore, the hole density of the active region 101 can be reduced by the first semiconductor layer 12.
  • the hole density of the terminal region 102 is about 1.5 times or more the hole density of the active region 101. At this time, in particular, the expansion of crystal defects to the active region 101 can be sufficiently suppressed, and the deterioration of the electrical characteristics of the semiconductor device 100 can be suppressed.
  • the gate electrode 24 is also provided in the terminal region 102.
  • the potential of the terminal region 102 can be stabilized.
  • the potential around the well region 16 can be stabilized.
  • the characteristics of the PN diode in the terminal region 102 can be stabilized, and the hole density can be stably controlled. Therefore, deterioration of the electrical characteristics of the semiconductor device 100 can be suppressed.
  • the structure of the semiconductor device 100 is not limited to that described above.
  • the semiconductor device 100 may be a MOSFET having a parasitic diode.
  • concentration of each layer is an example. Further, if there is no problem in the characteristics of the PN diode in the terminal region 102, the gate electrode 24 may not be provided in the terminal region 102.
  • FIG. 5 is a plan view of the semiconductor device 200 according to the second embodiment.
  • the position where the high concentration region 20 is formed is different from that of the semiconductor device 100.
  • Other structures are the same as those of the semiconductor device 100.
  • the high-concentration region 20 in the terminal region 102 of the semiconductor device 200 is formed only on the side along the ⁇ 1-100> direction among the four sides of the terminal region 102 surrounding the active region 101 in a plan view.
  • FIG. 6 is a sectional view taken along the line CC of FIG.
  • a high concentration region 20 which is a p + type impurity injection region is not formed on the side of the terminal region 102 along the ⁇ 11-20> direction.
  • Such a high density region 20 can be formed by using a photolithography technique.
  • the high-concentration region 20 is a p-type impurity in the semiconductor layer 11 using a resist mask that closes on the side along the ⁇ 11-20> direction and opens on the side along the ⁇ 1-100> direction.
  • the growth direction of the defect is the ⁇ 1-100> direction shown in FIG. Therefore, when the high-concentration region 20 is formed on two sides of the terminal region 102 parallel to the ⁇ 11-20> direction, the defect may expand to the active region 101 starting from the BPD generated in the terminal region 102. be.
  • the high concentration region 20 is not formed on the two sides parallel to the ⁇ 11-20> direction. Therefore, the region that is the starting point of the expansion of the crystal defect can be limited. Therefore, it is possible to suppress the expansion of crystal defects toward the central portion of the active region 101, and further suppress the deterioration of the electrical characteristics of the semiconductor device 200.

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Abstract

本開示に係る半導体装置は、第１導電型の第１半導体層と、第１半導体層の上面に設けられ、第１導電型であり、第１半導体層よりも不純物濃度が低い第２半導体層と、活性領域で第２半導体層の上面側に設けられ、第２導電型であるウェル領域と、ウェル領域の上面側に設けられ、第１導電型であるソース領域と、終端領域で第２半導体層の上面側に設けられ、第２導電型であり、ウェル領域よりも不純物濃度が高い高濃度領域とウェル領域の直上に設けられたゲート電極と、ソース領域および高濃度領域と電気的に接続されたソース電極と、を備え、第１半導体層の不純物濃度は４×１０１８ｃｍ－３以上であり、厚さは４μｍ以上である。

Description

半導体装置
　本開示は、半導体装置に関する。
　特許文献１には、炭化ケイ素を含む六方晶系半導体基板であるｎ型の基板を備えた半導体装置が開示されている。基板上には、ｎ型のドリフト層を含む半導体層が形成される。素子領域を囲むターミネーション領域において、半導体層の上面にはｐ型の第１半導体領域が形成される。第１半導体領域の上面にはシリサイド層が形成される。コンタクトプラグは、シリサイド層を介して第１半導体領域に接続される。平面視において、第１半導体領域は、第１方向に延在する第１延在部、第２方向に延在する第２延在部、第３方向に延在する第３延在部および第４方向に延在する第４延在部を繋げた環状構造を有する。
日本特開２０１７－１１２１７１号公報
　特許文献１では、終端領域に流れるｐｎ電流の分布を改善し、積層欠陥の拡張を抑制している。しかし、活性領域でのホール密度については考慮されておらず、電気特性の低下の抑制が十分にできない可能性がある。
　本開示は、電気特性の低下を抑制できる半導体装置を得ることを目的とする。
　本開示に係る半導体装置は、ＭＯＳＦＥＴが形成された活性領域と、平面視で該活性領域を囲む終端領域と、を有する半導体層と、該半導体層の上面に設けられたゲート電極と、該半導体層の上面に設けられたソース電極と、該半導体層の上面と反対側の面に設けられたドレイン電極と、を備え、該半導体層は、第１導電型の第１半導体層と、該第１半導体層の上面に設けられ、該第１導電型であり、該第１半導体層よりも不純物濃度が低い第２半導体層と、該活性領域で該第２半導体層の上面側に設けられ、第２導電型であるウェル領域と、該ウェル領域の上面側に設けられ、該第１導電型であるソース領域と、該終端領域で該第２半導体層の上面側に設けられ、該第２導電型であり、該ウェル領域よりも不純物濃度が高い高濃度領域と、を備え、該ゲート電極は、該ウェル領域の直上に設けられ、該ソース電極は、該ソース領域および該高濃度領域と電気的に接続され、該第１半導体層の不純物濃度は４×１０１８ｃｍ－３以上であり、厚さは４μｍ以上である。
　本開示に係る半導体装置では、第１半導体層を設けることで活性領域のホール密度を抑制でき、半導体装置の電気特性の低下を抑制できる。
実施の形態１に係る半導体装置の平面図である。 図１のＡ－Ａ断面図である。 図１のＢ－Ｂ断面図である。 第１半導体層とホール密度の関係を説明する図である。 実施の形態２に係る半導体装置の平面図である。 図５のＣ－Ｃ断面図である。
　各実施の形態に係る半導体装置について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
実施の形態１．
　図１は、実施の形態１に係る半導体装置１００の平面図である。以下ではｎ型が第１導電型であり、ｐ型が第２導電型である。これに限らず、ｎ型が第２導電型であり、ｐ型が第１導電型であっても良い。また、活性領域とは半導体装置の主電流が流れる領域を示す。また、終端領域は活性領域の周辺に設けられる領域を示す。なお、図１では半導体装置１００の構造を説明するため、電極、絶縁膜の一部が省略されている。
　半導体装置１００は平面視で矩形である。半導体装置１００は半導体チップを構成する。半導体装置１００の中央部には、ＳｉＣ－ＭＯＳＦＥＴ（Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ－Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）が形成された活性領域１０１が設けられる。半導体装置１００の外周部には終端領域１０２が設けられる。終端領域１０２には、活性領域１０１を囲むようにゲート配線２５が設けられる。ゲート配線２５の外側には、活性領域１０１を囲むようにｐ型の高濃度領域２０が設けられる。
　領域８０には、便宜的にユニットセルＵＣが表されている。実際の素子構造では、複数のユニットセルＵＣが活性領域１０１内に設けられる。複数のユニットセルＵＣのソース領域は、電気的に並列に接続される。
　図２は、図１のＡ－Ａ断面図である。図３は、図１のＢ－Ｂ断面図である。半導体装置１００は、半導体層１１と、半導体層１１の上面に設けられた複数のゲート電極２４と、半導体層１１の上面に設けられたソース電極２８と、半導体層１１の上面と反対側の面に設けられたドレイン電極３０とを備える。半導体層１１は、ＭＯＳＦＥＴが形成された活性領域１０１と、平面視で活性領域１０１を囲む終端領域１０２とを有する。半導体層１１は炭化ケイ素から形成される。
　半導体層１１は、ｎ型の不純物を含みＳｉＣから形成される基板１０を有する。基板１０の上面には第１半導体層１２が設けられる。第１半導体層１２はｎ＋型の不純物を含むエピタキシャル成長層である。第１半導体層１２は基板１０よりも高濃度である。第１半導体層１２の不純物濃度は例えば４×１０１８ｃｍ－３以上であり、厚さは４μｍ以上である。第１半導体層１２はバッファ層としての機能を有している。第１半導体層１２の上面には、第１半導体層１２よりも不純物濃度が低い第２半導体層１４が設けられる。第２半導体層１４はｎ型の不純物を含むエピタキシャル成長層である。
　活性領域１０１において、第２半導体層１４の上面側にはｐ型であるウェル領域１６が設けられる。ウェル領域１６の不純物濃度は例えば１×１０１８ｃｍ－３である。複数のウェル領域１６が、第２半導体層１４の最表面に選択的に設けられる。ウェル領域１６の上面側には、ｎ型のソース領域１８が設けられる。また、ウェル領域１６の上面側には、隣接するソース領域１８の間にｐ型の高濃度領域２０が設けられる。高濃度領域２０はウェルコンタクト領域とも呼ばれる。高濃度領域２０の不純物濃度は例えば１×１０２０ｃｍ－３である。
　終端領域１０２においても、第２半導体層１４の上面側にウェル領域１６が設けられる。終端領域１０２で、ウェル領域１６の上面側には、ｐ型でありウェル領域１６よりも不純物濃度が高い高濃度領域２０が設けられる。活性領域１０１の高濃度領域２０と終端領域１０２の高濃度領域２０は同じ層である。高濃度領域２０は活性領域１０１と終端領域１０２で同時に形成される。
　終端領域１０２で第２半導体層１４の上面側には、耐圧保持領域３２が設けられる。耐圧保持領域３２の不純物濃度は例えば１×１０１８ｃｍ－３である。高濃度領域２０は、耐圧保持領域３２よりも不純物濃度が高い。耐圧保持領域３２は、終端領域１０２においてウェル領域１６の外周に設けられる。耐圧保持領域３２の配置および不純物濃度は、必要とされる耐圧クラスによって変更される。
　活性領域１０１において、第２半導体層１４の上面にはゲート絶縁膜２２が設けられる。活性領域１０１においてゲート絶縁膜２２は、第２半導体層１４のうちウェル領域１６に挟まれた部分の上面から、ウェル領域１６の上面を通りソース領域１８の端縁部の上面まで設けられる。ゲート絶縁膜２２上にはゲート電極２４が設けられる。ゲート電極２４は、第２半導体層１４のうちウェル領域１６に挟まれた部分、ウェル領域１６およびソース領域１８の直上に設けられる。ゲート絶縁膜２２およびゲート電極２４は、層間絶縁膜２６で覆われている。層間絶縁膜２６はソース電極２８に覆われる。活性領域１０１においてソース電極２８は、ソース領域１８のうち層間絶縁膜２６で覆われていない部分および高濃度領域２０と接触し、電気的に接続されている。
　終端領域１０２において、ゲート電極２４は絶縁膜を介して高濃度領域２０の直上に設けられる。図３の例では、複数のゲート電極２４のうち１つは、第２半導体層１４のうちウェル領域１６と耐圧保持領域３２に挟まれた部分、ウェル領域１６および高濃度領域２０の直上に設けられる。また、ソース電極２８は終端領域１０２まで延長されている。終端領域１０２においてソース電極２８は、高濃度領域２０のうち層間絶縁膜２６で覆われていない部分と接触し、電気的に接続されている。終端領域１０２の上に設けられ互いに隣接するゲート電極２４の間を通り、ソース電極２８は高濃度領域２０と電気的に接続される。
　半導体装置１００において主電流の通電時には、ドレイン電極３０からソース電極２８に向かう方向へ電流が流れる。このとき、半導体装置１００はＭＯＳＦＥＴとして動作する。また、逆電流の通電時には、ソース電極２８からドレイン電極３０に向かう方向へ電流が流れる。このとき、半導体装置１００はＰＮダイオードとして動作する。半導体装置１００の内部に寄生するＰＮダイオードはボディダイオードとも呼ばれる。
　ＰＮダイオードの動作時には、通電時間の増加とともに半導体装置の電気特性の劣化が生じることがある。ＳｉＣ基板中のエピタキシャル成長層にＢＰＤ（Ｂａｓａｌ　Ｐｌａｎｅ　Ｄｉｓｌｏｃａｔｉｏｎ、規定面転位）が形成されることがある。一般にＢＰＤが形成された領域にホール電流が流れると、ＢＰＤが成長して積層欠陥が生じる。これにより、オン状態の抵抗値の増加および素子耐圧の低下等が生じる可能性がある。
　この現象を防ぐためには、ＢＰＤ自体を減らすか、ＢＰＤが成長する原因である一定以上のホール密度の電流を通電しないことが考えられる。
　これに対し本実施の形態では、終端領域１０２内にｐ型の高濃度領域２０が設けられる。これにより、結晶欠陥の拡張の原因となるホール密度の高い領域を終端領域１０２に形成でき、ホール電流を終端領域１０２に流し易くできる。従って、活性領域１０１への結晶欠陥の拡張を抑制し、半導体装置１００の電気特性の低下を抑制できる。
　また、終端領域１０２において高濃度領域２０はソース電極２８と接触する。これにより、終端領域１０２に活性領域１０１とは別のＰＮダイオードを形成でき、ソース電極２８からの電流経路を終端領域１０２に集中させることができる。従って、ホール電流の流れる領域をさらに限定できる。
　図４は、第１半導体層１２とホール密度の関係を説明する図である。図４には、半導体装置１００に逆電流を流した際の、活性領域１０１と終端領域１０２の境界周辺のホール密度のシミュレーション結果が示されている。Ｘ＝０の地点が活性領域１０１と終端領域１０２の界面に対応する。Ｘが正の領域は終端領域１０２であり、Ｘが負の領域は活性領域１０１である。ホール密度は、基板１０のうち第１半導体層１２との界面付近におけるホール密度を示す。
　図４における実線は、第１半導体層１２の不純物濃度が４×１０１８ｃｍ－３、厚さが４μｍのときの結果を示す。図４における破線は、第１半導体層１２の不純物濃度が１×１０１８ｃｍ－３、厚さが１μｍのときの結果を示す。
　図４に示されるように、第１半導体層１２の不純物濃度が４×１０１８ｃｍ－３であり厚さが４μｍのとき、不純物濃度が１×１０１８ｃｍ－３であり厚さが１μｍのときと比較して、活性領域１０１内のホール密度を下げることができる。第１半導体層１２の不純物濃度を濃くするほど、または、第１半導体層１２を厚くするほど、ホール密度を低減させる効果は大きくなる。第１半導体層１２は、活性領域１０１においてＰＮダイオード動作時の電流に伴って流れるホール電流をせき止める機能を有する。このため、第１半導体層１２により活性領域１０１のホール密度を低減させることができる。
　第１半導体層１２の不純物濃度が４×１０１８ｃｍ－３であり厚さが４μｍのとき、終端領域１０２のホール密度は活性領域１０１のホール密度の約１．５倍以上となる。このとき、特に活性領域１０１への結晶欠陥の拡張を十分に抑制し、半導体装置１００の電気特性の低下を抑制できる。
　また、本実施の形態では終端領域１０２においてもゲート電極２４が設けられる。終端領域１０２において、高濃度領域２０、ウェル領域１６の直上にゲート電極２４が設けられることで、終端領域１０２の電位を安定化させることができる。特にウェル領域１６周辺の電位を安定化させることができる。これにより、終端領域１０２内のＰＮダイオードの特性を安定させることができ、ホール密度を安定して制御できる。従って、半導体装置１００の電気特性の低下を抑制できる。
　半導体装置１００の構造は上述したものに限定されない。半導体装置１００は、寄生ダイオードを有するＭＯＳＦＥＴであれば良い。また、各層の濃度は一例である。また、終端領域１０２のＰＮダイオードの特性に問題がなければ、終端領域１０２にゲート電極２４は設けられなくても良い。
　これらの変形は、以下の実施の形態に係る半導体装置について適宜応用することができる。なお、以下の実施の形態に係る半導体装置については実施の形態１との共通点が多いので、実施の形態１との相違点を中心に説明する。
実施の形態２．
　図５は、実施の形態２に係る半導体装置２００の平面図である。半導体装置２００では、高濃度領域２０が形成される位置が半導体装置１００と異なる。他の構造は半導体装置１００と同様である。半導体装置２００の終端領域１０２における高濃度領域２０は、平面視で活性領域１０１を囲む終端領域１０２の４辺のうち、＜１－１００＞方向に沿った辺にのみ形成される。
　図６は、図５のＣ－Ｃ断面図である。終端領域１０２の＜１１－２０＞方向に沿った辺には、ｐ＋型の不純物注入領域である高濃度領域２０が形成されない。
　このような高濃度領域２０は、フォトリソグラフィ技術を用いて形成できる。高濃度領域２０は、＜１１－２０＞方向に沿った辺の上では閉口し、＜１－１００＞方向に沿った辺の上では開口するレジストマスクを用いて、半導体層１１にｐ型不純物をイオン注入することで形成できる。
　欠陥の成長方向は図５に示される＜１－１００＞方向である。このため、終端領域１０２のうち＜１１－２０＞方向と平行な２辺に高濃度領域２０を形成した場合、終端領域１０２に発生したＢＰＤを起点として活性領域１０１へ欠陥が拡張する可能性がある。本実施の形態では、＜１１－２０＞方向と平行な２辺に高濃度領域２０が形成されない。このため、結晶欠陥の拡張の起点となる領域を限定できる。従って、活性領域１０１の中心部に向かう結晶欠陥の拡張を抑制でき、半導体装置２００の電気特性の低下をさらに抑制できる。
　各実施の形態で説明した技術的特徴は適宜に組み合わせて用いても良い。
　１０　基板、１１　半導体層、１２　第１半導体層、１４　第２半導体層、１６　ウェル領域、１８　ソース領域、２０　高濃度領域、２２　ゲート絶縁膜、２４　ゲート電極、２５　ゲート配線、２６　層間絶縁膜、２８　ソース電極、３０　ドレイン電極、３２　耐圧保持領域、１００　半導体装置、１０１　活性領域、１０２　終端領域、２００　半導体装置、ＵＣ　ユニットセル

Claims (5)

  1. 　ＭＯＳＦＥＴが形成された活性領域と、平面視で前記活性領域を囲む終端領域と、を有する半導体層と、
    　前記半導体層の上面に設けられたゲート電極と、
    　前記半導体層の上面に設けられたソース電極と、
    　前記半導体層の上面と反対側の面に設けられたドレイン電極と、
    　を備え、
    　前記半導体層は、
    　第１導電型の第１半導体層と、
    　前記第１半導体層の上面に設けられ、前記第１導電型であり、前記第１半導体層よりも不純物濃度が低い第２半導体層と、
    　前記活性領域で前記第２半導体層の上面側に設けられ、第２導電型であるウェル領域と、
    　前記ウェル領域の上面側に設けられ、前記第１導電型であるソース領域と、
    　前記終端領域で前記第２半導体層の上面側に設けられ、前記第２導電型であり、前記ウェル領域よりも不純物濃度が高い高濃度領域と、
    　を備え、
    　前記ゲート電極は、前記ウェル領域の直上に設けられ、
    　前記ソース電極は、前記ソース領域および前記高濃度領域と電気的に接続され、
    　前記第１半導体層の不純物濃度は４×１０１８ｃｍ－３以上であり、厚さは４μｍ以上であることを特徴とする半導体装置。
  2. 　前記ゲート電極を複数備え、
    　前記複数のゲート電極のうち前記終端領域の上に設けられ互いに隣接するゲート電極の間を通り、前記ソース電極は前記高濃度領域と電気的に接続されることを特徴とする請求項１に記載の半導体装置。
  3. 　前記終端領域で前記第２半導体層の上面側に設けられた耐圧保持領域を備え、
    　前記高濃度領域は、前記耐圧保持領域よりも不純物濃度が高いことを特徴とする請求項１または２に記載の半導体装置。
  4. 　前記半導体層は、炭化ケイ素から形成されることを特徴とする請求項１から３の何れか１項に記載の半導体装置。
  5. 　前記高濃度領域は、平面視で前記活性領域を囲む前記終端領域の４辺のうち、＜１－１００＞方向に沿った辺にのみ形成されることを特徴とする請求項１から４の何れか１項に記載の半導体装置。
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JP2015056644A (ja) * 2013-09-13 2015-03-23 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
JP2017112171A (ja) * 2015-12-15 2017-06-22 株式会社日立製作所 半導体装置、パワーモジュール、電力変換装置、自動車および鉄道車両
JP2020141130A (ja) * 2019-02-27 2020-09-03 株式会社デンソー 炭化珪素半導体装置およびその製造方法
WO2020208761A1 (ja) * 2019-04-11 2020-10-15 三菱電機株式会社 半導体装置および電力変換装置

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JP4185215B2 (ja) 1999-05-07 2008-11-26 弘之 松波 ＳｉＣウエハ、ＳｉＣ半導体デバイス、および、ＳｉＣウエハの製造方法
JP4224253B2 (ja) 2002-04-24 2009-02-12 パナソニック株式会社 半導体装置及びその製造方法

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JP2015056644A (ja) * 2013-09-13 2015-03-23 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
JP2017112171A (ja) * 2015-12-15 2017-06-22 株式会社日立製作所 半導体装置、パワーモジュール、電力変換装置、自動車および鉄道車両
JP2020141130A (ja) * 2019-02-27 2020-09-03 株式会社デンソー 炭化珪素半導体装置およびその製造方法
WO2020208761A1 (ja) * 2019-04-11 2020-10-15 三菱電機株式会社 半導体装置および電力変換装置

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