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WO2021189669A1 - 显示基板及其制备方法、显示母板和显示装置 - Google Patents

显示基板及其制备方法、显示母板和显示装置 Download PDF

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Publication number
WO2021189669A1
WO2021189669A1 PCT/CN2020/095426 CN2020095426W WO2021189669A1 WO 2021189669 A1 WO2021189669 A1 WO 2021189669A1 CN 2020095426 W CN2020095426 W CN 2020095426W WO 2021189669 A1 WO2021189669 A1 WO 2021189669A1
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WIPO (PCT)
Prior art keywords
layer
insulating layer
area
substrate
edge
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Application number
PCT/CN2020/095426
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English (en)
French (fr)
Inventor
韩林宏
于鹏飞
刘庭良
张毅
秦世开
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080000959.9A priority Critical patent/CN113711290B/zh
Priority to EP20904243.1A priority patent/EP4131217A4/en
Priority to JP2021569177A priority patent/JP7515520B2/ja
Priority to EP24153913.9A priority patent/EP4340579A3/en
Priority to US17/266,622 priority patent/US20220115473A1/en
Publication of WO2021189669A1 publication Critical patent/WO2021189669A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/80—Manufacture or treatment specially adapted for the organic devices covered by this subclass using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/851—Division of substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, in particular to a display substrate and a preparation method thereof, a display motherboard and a display device.
  • OLED Organic Light Emitting Diode
  • FIG. 1 is a schematic diagram of the arrangement of a plurality of display substrates on a display mother board.
  • the multiple substrate areas 300 on the display motherboard 100 are regularly arranged periodically, and the cutting area 400 is located outside the substrate area 300.
  • the substrate area 300 includes at least a display area 310 and a binding area 302.
  • the display area 310 includes a plurality of pixels arranged in a matrix.
  • the binding area 302 includes a fan-out area and a driving circuit.
  • the binding area 302 is disposed on one side of the display area 310.
  • the cutting area 400 is provided with a first cutting lane 701 and a second cutting lane 702. After all the film layers of the display mother board are prepared, the cutting device performs rough cutting and cutting along the first cutting lane 701 and the second cutting lane 702 respectively. Fine cutting to form a display substrate.
  • the display substrate has problems such as poor dark spots, which affects the display quality.
  • the present disclosure provides a display substrate including a flexible base and a composite insulating layer disposed on the flexible base, and the edge region of the display substrate includes a step structure formed by the composite insulating layer; the step The height of the step in the structure increases from the edge of the display substrate to the direction inside the display substrate; the edge area also includes a first flat layer covering the step structure, and the edge of the first flat layer is connected to the edge of the flexible substrate. The edges are flush.
  • the step structure includes a first step, a second step, and a third step, the thickness of the first step is greater than the thickness of the second step, and the thickness of the first step is greater than the thickness of the first step.
  • the thickness of the third step is described.
  • the thickness of the first step is 15 ⁇ m to 20.7 ⁇ m
  • the thickness of the second step is 0.2 ⁇ m to 1.3 ⁇ m
  • the thickness of the third step is 0.5 ⁇ m to 1.4 ⁇ m.
  • the edge area of the display substrate further includes a second flat layer disposed on the first flat layer, and the orthographic projection of the second flat layer on the flexible substrate is similar to the The orthographic projections of the first step and the second step on the flexible substrate partially overlap.
  • the orthographic projection of the second flat layer on the flexible substrate overlaps the orthographic projection of the first step on the flexible substrate
  • the width of which is 10 ⁇ m to 20 ⁇ m
  • the overlapping width of the orthographic projection of the second flat layer on the flexible substrate and the orthographic projection of the second step on the flexible substrate is 20 ⁇ m to 30 ⁇ m.
  • the substrate area of the display substrate includes: a first insulating layer disposed on the flexible base, an active layer disposed on the first insulating layer, and covering the active layer
  • the metal conductive layer on the flat layer covers the second flat layer of the metal conductive layer.
  • the flexible substrate includes a first flexible layer, a first barrier layer, an amorphous silicon layer, a second flexible layer, and a second barrier layer that are sequentially stacked
  • the composite insulating layer includes The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer are stacked on the second barrier layer; the first flexible layer, the first barrier layer, and the amorphous silicon layer
  • the total thickness of the second and second flexible layer is 15 ⁇ m to 20 ⁇ m
  • the thickness of the second barrier layer is 0.4 ⁇ m to 0.7 ⁇ m
  • the thickness of the first insulating layer is 0.2 ⁇ m to 0.6 ⁇ m.
  • the second barrier layer includes a first sub-layer and a second sub-layer stacked on the second flexible layer;
  • the first step includes the first flexible layer, the second sub-layer A barrier layer, an amorphous silicon layer, a second flexible layer and a first sublayer of the second barrier layer,
  • the second step includes the second sublayer of the second barrier layer and the first insulating layer, so
  • the third step includes the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer;
  • the distance between the upper surface of the first step and the reference plane is 0.05 ⁇ m to 0.06 ⁇ m, so The distance between the upper surface of the second step and the reference surface is 0.75 ⁇ m to 0.95 ⁇ m, the distance between the upper surface of the third step and the reference surface may be 1.40 ⁇ m to 1.80 ⁇ m, and the reference surface is The first sub-layer is adjacent to the surface on one side of the second flexible layer.
  • the sidewalls of the second step and the third step are slope surfaces, and the angle between the bus bar of the slope surface and the normal direction of the display substrate is 20° to 50°.
  • the distance from the edge of the first step to the edge of the second step is greater than the distance from the edge of the second step to the edge of the third step, and the distance from the edge of the first step to the edge of the second step is greater than The distance from the edge of the third step to the edge of the crack dam.
  • the distance from the edge of the first step to the edge of the second step is 55 ⁇ m to 210 ⁇ m
  • the distance from the edge of the second step to the edge of the third step is 5 ⁇ m to 40 ⁇ m
  • the distance from the edge of the third step to the The distance between the edges of the crack dam is 5 ⁇ m to 15 ⁇ m.
  • a crack dam is further provided on the composite insulating layer in the edge region, and the crack dam includes a plurality of spaced apart cracks, and the cracks expose the first insulating layer; A flat layer covers the crack dam.
  • the edge area of the display substrate includes a peripheral area and an inner cutting area, and the cutting inner area is located on a side of the peripheral area away from the substrate area; the step structure is provided in the cutting Zone, the crack dam is arranged in the peripheral zone.
  • the substrate area of the display substrate includes a display area and a binding area provided on one side of the display area, and an edge area on the side of the binding area away from the display area forms a stepped structure
  • the stepped structure includes a first step and a second step, the first step is formed by a flexible substrate and a composite insulating layer, and the second step is formed by the first and second flat layers; in addition to the The binding area is away from the edge area on one side of the display area, and the step structure is arranged in the display area and other edge areas of the binding area.
  • the present disclosure also provides a display mother board, which includes a plurality of substrate areas and a cutting area surrounding the substrate area; the display mother board includes: a driving structure layer disposed in the substrate area and the cutting area , A first flat layer disposed on the driving structure layer; the driving structure layer of the cutting area includes a composite insulating layer, the composite insulating layer is provided with a groove, and the first flat layer fills the groove.
  • the drive structure layer of the substrate area includes: a first insulating layer disposed on a flexible substrate, an active layer disposed on the first insulating layer, and an active layer covering the active layer.
  • the layers include: a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer stacked on a flexible substrate;
  • the flexible substrate includes a first flexible layer, a first The barrier layer, the amorphous silicon layer, the second flexible layer and the second barrier layer; the total thickness of the
  • the second barrier layer includes a first sublayer and a second sublayer stacked on the second flexible layer;
  • the groove includes a first groove and a second groove ,
  • the first groove is disposed on the second sublayer of the first insulating layer and the second barrier layer, the first groove exposes the first sublayer of the second barrier layer, and the first Two grooves are provided on the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer.
  • the second groove exposes the gap between the first insulating layer and the second barrier layer.
  • the first sub-layer, the orthographic projection of the second groove on the flexible substrate includes the orthographic projection of the first groove on the flexible substrate; the depth of the first groove is 0.2 ⁇ m to 1.3 ⁇ m, the The depth of the second groove is 0.5 ⁇ m to 1.4 ⁇ m.
  • the present disclosure also provides a method for preparing a display substrate, including:
  • the driving structure layer of the cutting area includes a composite insulating layer disposed on a flexible substrate, and the composite insulating layer forms a groove of a stepped structure;
  • Cutting is performed in the cutting area to form a display substrate, and a step structure is formed in the edge area of the display substrate; the height of the step in the step structure increases from the edge of the display substrate to the direction inside the display substrate; the first flat A layer covers the step structure, and the edge of the first flat layer is flush with the edge of the flexible substrate.
  • forming a driving structure layer in the cutting area includes:
  • a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer are sequentially formed on the flexible substrate;
  • the first insulating layer is formed on On the second sub-layer of the second barrier layer;
  • a first groove exposing the first sub-layer of the second barrier layer is formed on the first insulating layer and the second sub-layer of the second barrier layer in the second groove ,
  • the second groove exposes the first groove.
  • the present disclosure also provides a display device including the aforementioned display substrate.
  • FIG. 1 is a schematic diagram of the arrangement of multiple display substrates on a display motherboard
  • Figure 2 is a schematic diagram showing the remaining metal block in the cutting area of the mother board
  • FIG. 3 is a schematic diagram of the structure of the display motherboard of the present disclosure.
  • Figure 4 is a schematic diagram of the disclosure after forming a flexible substrate
  • FIG. 5 is a schematic diagram of the present disclosure after forming a pattern of a driving structure layer
  • Figure 6 is a schematic diagram of the present disclosure after forming grooves and crack dams
  • FIG. 7 is a schematic diagram after the first flat layer pattern is formed in the present disclosure.
  • FIG. 8 is a schematic diagram of the present disclosure after forming a pattern of a metal conductive layer
  • FIG. 9 is a schematic diagram of the present disclosure after forming a second flat layer pattern
  • FIG. 10 is a schematic diagram after the anode and the third connecting electrode pattern are formed in the present disclosure.
  • FIG. 11 is a schematic diagram of the present disclosure after forming a pixel definition layer and a dam base pattern
  • FIG. 12 is a schematic diagram of the present disclosure after forming a pattern of isolation pillars
  • FIG. 13 is a schematic diagram of the present disclosure after forming an organic light-emitting layer and a cathode pattern
  • FIG. 14 is a schematic diagram of the present disclosure after forming an encapsulation layer pattern
  • Figure 15 is a schematic diagram of the present disclosure after attaching the back film
  • Figure 16 is a schematic diagram of cutting in the present disclosure.
  • FIG. 17 is a schematic diagram showing the structure of the edge area of the substrate according to the present disclosure.
  • FIG. 18 is a schematic diagram of the structure of the binding area of the disclosure.
  • Figure 19 is a cross-sectional view taken along the line B-B in Figure 18;
  • Fig. 20 is a cross-sectional view taken along the line C-C in Fig. 18.
  • 10B the first barrier layer
  • 10C amorphous silicon layer
  • 10D the second flexible layer
  • 10E the second barrier layer
  • 11 the first insulating layer
  • 12A the first active layer
  • 12B the second active layer
  • 12C the third active layer
  • 13 the second insulating layer
  • 14A the first gate electrode
  • 14B the second gate electrode
  • 14C the third gate electrode
  • 17B Second source electrode
  • 17C Tin-Third source electrode
  • 18A First drain electrode
  • 18B the second drain electrode
  • 18C the third drain electrode
  • 19 the fifth insulating layer
  • 24-pixel definition layer 25-organic light-emitting layer; 26-cathode;
  • 42 The second capacitor electrode
  • 42A The third capacitor electrode
  • 42B The fourth capacitor electrode
  • 100 display motherboard; 101—first transistor; 102—second transistor;
  • 105 low voltage line
  • 106 first connecting electrode
  • 107 second connecting electrode
  • 303 the first fan-out area
  • 304 the bending area
  • 305 the second fan-out area
  • 306 Anti-static area
  • 307 Drive chip area
  • 308 Body needle area
  • 310 display area
  • 320 peripheral circuit area
  • 330 peripheral area
  • 701 The first cutting line
  • 702 The second cutting line
  • 311 Bridged circuit area
  • connection should be interpreted broadly. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate piece, or internal communication between two components.
  • connection should be interpreted broadly. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate piece, or internal communication between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged.
  • electrical connection includes the case where constituent elements are connected together by elements having a certain electrical function.
  • An element having a certain electrical function is not particularly limited as long as it can transmit and receive electrical signals between connected constituent elements.
  • elements having a certain electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore, it also includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore, also includes a state where an angle of 85° or more and 95° or less is included.
  • film and “layer” can be interchanged.
  • the “conductive layer” can be replaced by the “conductive film.”
  • the “insulating film” can sometimes be replaced with an “insulating layer.”
  • a preparation process for a cutting area of a display substrate includes: sequentially forming a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer on a flexible substrate.
  • the cutting area The above-mentioned insulating layer is provided with a groove exposing the flexible material layer in the flexible substrate. Then a flat layer is formed, and part of the flat layer in the cutting area is removed, exposing the groove.
  • the above-mentioned film layer in the cutting area forms a stepped groove structure, and the side wall of the groove is a slope surface.
  • a metal thin film is deposited, and the metal thin film is patterned through a patterning process to form a metal conductive layer pattern on the flat layer. Since the cutting area is formed with step-shaped grooves, not only the height of the deposited metal film is different, but also the metal film has a large height difference, resulting in incomplete etching of the metal film during the patterning process, and the grooves after the patterning process The metal block a remains on the bottom surface and the step surface, as shown in Figure 2.
  • the metal film adopts a titanium/aluminum/titanium (Ti/Al/Ti) laminated structure
  • the remaining metal block 50 will replace the Ag particles, and the Ag particles will be mixed in the etching
  • the liquid flows and adheres everywhere.
  • Ag particles adhere to the display area it will cause defects such as poor dark spots in the display area.
  • the metal and the organic material chemically react and produce particles. The particles not only pollute the equipment, but also mix in the etching solution everywhere. Flow and adhesion.
  • the present disclosure provides a display substrate, the display substrate includes a flexible base and a composite insulating layer disposed on the flexible base, and the edge region of the display substrate includes a step structure formed by the composite insulating layer; The height of the steps in the step structure increases from the edge of the display substrate to the direction inside the display substrate; the edge area further includes a first flat layer covering the step structure, and the edge of the first flat layer is connected to the flexible substrate The edges are flush.
  • the step structure includes a first step, a second step, and a third step, the thickness of the first step is greater than the thickness of the second step, and the thickness of the first step is greater than that of the The thickness of the third step.
  • the thickness of the first step is 15 ⁇ m to 20.7 ⁇ m
  • the thickness of the second step is 0.2 ⁇ m to 1.3 ⁇ m
  • the thickness of the third step is 0.5 ⁇ m to 1.4 ⁇ m.
  • the substrate area of the display substrate includes: a first insulating layer disposed on the flexible base, an active layer disposed on the first insulating layer, and a portion covering the active layer A second insulating layer, a first gate metal layer disposed on the second insulating layer, a third insulating layer covering the first gate metal layer, and a second gate metal layer disposed on the third insulating layer , A fourth insulating layer covering the second gate metal layer, a source-drain metal layer provided on the fourth insulating layer, and a fifth insulating layer covering the source-drain metal layer; the first flat layer is provided On the fifth insulating layer.
  • the substrate area of the display substrate further includes: a metal conductive layer disposed on the first flat layer, and a second flat layer covering the metal conductive layer.
  • the flexible substrate includes a first flexible layer, a first barrier layer, an amorphous silicon layer, a second flexible layer, and a second barrier layer that are sequentially stacked.
  • the composite insulating layer includes a first insulating layer and a second insulating layer stacked on the second sublayer of the second barrier layer , The third insulating layer, the fourth insulating layer, and the fifth insulating layer;
  • the total thickness of the first flexible layer, the first barrier layer, the amorphous silicon layer, and the second flexible layer is 15 ⁇ m to 20 ⁇ m, and the second barrier
  • the thickness of the layer is 0.4 ⁇ m to 0.7 ⁇ m, the thickness of the first insulating layer is 0.2 ⁇ m to 0.6 ⁇ m;
  • the step structure includes the first flexible layer, the first barrier layer, the amorphous silicon layer, and the second The first step formed by the flexible layer and the first sublayer of the second barrier layer, the
  • the distance between the upper surface of the first step and the reference surface is 0.05 ⁇ m to 0.06 ⁇ m, and the distance between the upper surface of the second step and the reference surface is 0.75 ⁇ m to 0.95 ⁇ m
  • the distance between the upper surface of the third step and the reference surface may be 1.40 ⁇ m to 1.80 ⁇ m, and the reference surface is the surface of the first sub-layer adjacent to the second flexible layer.
  • the side walls of the second step and the third step are slope surfaces, and the included angle between the bus bar of the slope surface and the normal direction of the display substrate is 20° to 50°.
  • a crack dam is further provided on the composite insulating layer in the edge region, the crack dam includes a plurality of spaced apart cracks, and the cracks expose the first insulating layer;
  • the flat layer covers the crack dam.
  • the display substrate includes a substrate area and an edge area, the edge area includes a peripheral area and a cut inner area, and the cut inner area is located on a side of the peripheral area away from the substrate area; the step The structure is arranged in the cutting inner zone, and the crack dam is arranged in the peripheral zone.
  • the substrate area includes a display area and a binding area provided on one side of the display area, and an edge area of the binding area away from the display area forms a stepped structure.
  • the structure includes a first step and a second step, the first step is formed by a flexible substrate and a composite insulating layer, and the second step is formed by the first and second flat layers; except that the binding area is far away In the edge area on one side of the display area, the step structure is arranged in the other edge areas of the display area and the binding area.
  • Fig. 3 is a schematic diagram of the structure of the display substrate of the present disclosure, and is a cross-sectional view along the line A-A in Fig. 1, illustrating the cross-sectional structure of the substrate area and the cutting area of the dual source-drain metal layer (dual SD or 2SD) structure.
  • the display substrate includes a display area 310, a peripheral circuit area 320, and an edge area 500.
  • the edge area 500 includes a peripheral area 330 and a cut inner area 420.
  • the cut inner area 420 is located in the peripheral area 330 away from the display area 310. On the side. As shown in FIG.
  • the display substrate of the present disclosure includes a flexible base 10, a driving structure layer disposed on the flexible base 10, a first flat layer 20 disposed on the driving structure layer, and The metal conductive layer on the first flat layer 20 and the second flat layer 21 covering the metal conductive layer.
  • the driving structure layer of the display area 310 includes a plurality of transistors forming a pixel driving circuit
  • the driving structure layer of the peripheral circuit area 320 includes a plurality of transistors and storage capacitors forming a peripheral circuit. In FIG. 3, three transistors and two storage capacitors are used as Example to illustrate.
  • the driving structure layer of the edge area 500 includes a composite insulating layer composed of a plurality of inorganic insulating layers, the composite insulating layer is provided with a step structure and a crack dam, and the first flat layer 20 of the edge area 500 covers and fills the step structure and the crack dam.
  • the driving structure layer of the display area 310 and the peripheral circuit area 320 may include: a first insulating layer 11 disposed on the flexible substrate 10, an active layer disposed on the first insulating layer 11, covered with The second insulating layer 13 of the source layer, the first gate metal layer disposed on the second insulating layer 13, the third insulating layer 15 covering the first gate metal layer, the second gate metal disposed on the third insulating layer 15 Layer, the fourth insulating layer 16 covering the second gate metal layer, the source/drain metal layer disposed on the fourth insulating layer 16, and the fifth insulating layer 19 covering the source/drain metal layer.
  • the active layer includes at least a first active layer, a second active layer, and a third active layer
  • the first gate metal layer includes at least a first gate electrode, a second gate electrode, a third gate electrode, a first capacitor electrode
  • the second capacitor electrode, the second gate metal layer includes at least a third capacitor electrode and a fourth capacitor electrode
  • the source-drain metal layer includes at least a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, and a third capacitor electrode.
  • the source electrode, the third drain electrode and the low voltage line 105, the first active layer, the first gate electrode, the first source electrode and the first drain electrode constitute the first transistor 101, the second active layer, the second gate electrode and the first transistor 101
  • the two source electrodes and the second drain electrode constitute the second transistor 102
  • the third active layer, the third gate electrode, the third source electrode and the third drain electrode constitute the third transistor 103
  • the first capacitor electrode and the third capacitor electrode constitute The first storage capacitor 104A, the second capacitor electrode and the fourth capacitor electrode constitute the second storage capacitor 104B.
  • the display area 310 and the peripheral circuit area 320 also include a light-emitting structure layer.
  • the light-emitting structure layer includes a metal conductive layer disposed on the first flat layer 20, a second flat layer 21 covering the metal conductive layer, and a second flat layer 21.
  • the metal conductive layer includes at least a first connection electrode 106 and a second connection electrode 107.
  • the driving structure layer of the edge area 500 may include a first insulating layer 11, a second insulating layer 13, a third insulating layer 15, a fourth insulating layer 16, and a first insulating layer 11, a second insulating layer 13, a third insulating layer 16 and a second insulating layer sequentially stacked on the flexible substrate 10.
  • Five insulating layers 19, the above-mentioned insulating layers are all inorganic insulating layers, as the composite insulating layer of the present disclosure.
  • the step structure is arranged in the cutting inner zone 420, and the crack dam is arranged in the peripheral zone 330. In the cut inner region 420 in the edge region 500, the flexible substrate 10 and the composite insulating layer together form the step structure of the present disclosure.
  • the step structure includes a first step 51 formed by the first flexible layer 10A of the flexible substrate 10, the first barrier layer 10B, the amorphous silicon layer 10C, the second flexible layer 10D, and the first sublayer of the second barrier layer 10E.
  • the second step 52 formed by the second sublayer of the second barrier layer 10E and the first insulating layer 11, and the second step 52 formed by the second insulating layer 13, the third insulating layer 15, the fourth insulating layer 16, and the fifth insulating layer 19
  • the third step 53, the heights of the first step 51, the second step 52 and the third step 53 increase in order from the cutting inner area 420 (the edge of the display substrate) to the display area 310 (inside the display substrate), that is, along the first step In the direction from one step 51 to the third step 53, the heights of the first step 51, the second step 52 and the third step 53 increase in order.
  • the height of the step refers to the distance between the surface of the step and the lower surface of the flexible substrate.
  • the first flat layer 20 of the cut inner region 420 covers the above-mentioned step structure, and the edge of the first flat layer 20 away from the display area 310 is flush with the edge of the flexible substrate 10.
  • the composite insulating layer is provided with a crack dam 33, which includes a plurality of spaced cracks opened in the composite insulating layer, and the second insulating layer 13 and the third insulating layer in the cracks 15.
  • the fourth insulating layer 16 and the fifth insulating layer 19 are removed, exposing the surface of the first insulating layer 11.
  • the first flat layer 20 of the peripheral area 330 covers the crack dam 33 and fills a plurality of spaced cracks in the crack dam 33.
  • the surface is basically flush.
  • the "patterning process” referred to in the present disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, developing, etching, and stripping the photoresist.
  • the deposition can be any one or more selected from sputtering, evaporation and chemical vapor deposition
  • the coating can be any one or more selected from spraying and spin coating
  • the etching can be selected from dry etching. Any one or more of wet engraving.
  • Thin film refers to a layer of film made by depositing or coating a certain material on a substrate.
  • the "film” can also be referred to as a "layer”.
  • the "thin film” needs a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • a and B are arranged in the same layer means that A and B are formed at the same time through the same patterning process.
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.
  • the display mother board includes a substrate area 300 and a cutting area 400 located at the periphery of the substrate area 300.
  • the flexible substrate 10 includes a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on the glass carrier 1.
  • the materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film, etc.
  • the first and second inorganic materials The material of the layer can be silicon nitride (SiNx) or silicon oxide (SiOx) to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier layers.
  • the material can be amorphous silicon (a-si).
  • the preparation process may include: first coating a layer of polyimide on the glass carrier 1 and curing it to After the film is formed, a first flexible (PI1) layer 10A is formed; then a barrier film is deposited on the first flexible layer 10A to form a first barrier (Barrier1) layer 10B covering the first flexible layer 10A; and then on the first barrier layer 10B A layer of amorphous silicon film is deposited on it to form an amorphous silicon (a-si) layer 10C covering the first barrier layer 10B; then a layer of polyimide is coated on the amorphous silicon layer 10C, and the film is cured A second flexible (PI2) layer 10D is formed; then a barrier film is deposited on the second flexible layer 10D to form a second barrier (Barrier2) layer 10E covering the second flexible layer 10D, and the preparation of the flexible substrate 10 is completed, as shown in the figure 4 shown. After this
  • the total thickness of the first flexible layer 10A, the first barrier layer 10B, the amorphous silicon layer 10C, and the second flexible layer 10D may be 15 ⁇ m to 20 ⁇ m, and the thickness of the second barrier layer 10E may be 0.4 ⁇ m To 0.7 ⁇ m.
  • the total thickness of the first flexible layer 10A, the first barrier layer 10B, the amorphous silicon layer 10C, and the second flexible layer 10D may be 17.6 ⁇ m, and the thickness of the second barrier layer 10E may be 0.55 ⁇ m .
  • the thickness refers to the distance between the upper surface and the lower surface of the film layer.
  • the driving structure layer of the substrate area 300 includes the first transistor 101, the second transistor 102, the third transistor 103, the first storage capacitor 104A, the first storage capacitor 104B, and the low voltage line 105 that constitute the pixel driving circuit.
  • the driving structure of the cutting area 400 includes a composite insulating layer composed of a plurality of inorganic insulating layers, on which a groove exposing the second flexible layer 10D of the flexible substrate 10 is formed.
  • the manufacturing process of the driving structure layer may include:
  • a first insulating film and an active layer film are sequentially deposited on the flexible substrate 10, and the active layer film is patterned through a patterning process to form a first insulating layer 11 covering the entire flexible substrate 10, and set on the first insulating layer 11
  • the active layer pattern is formed in the substrate area 300 and includes at least the first active layer 12A, the second active layer 12B, and the third active layer 12C.
  • the cutting area 400 includes the first insulating layer 11 disposed on the flexible substrate 10.
  • the thickness of the first insulating layer 11 may be 0.2 ⁇ m to 0.6 ⁇ m. In some possible implementations, the thickness of the first insulating layer 11 may be 0.4 ⁇ m.
  • the first gate metal layer pattern is formed in the substrate area 300 and includes at least a first gate electrode 14A, a second gate electrode 14B, a third gate electrode 14C, a first capacitor electrode 41A, and a second capacitor electrode 41B.
  • the cutting area 400 includes the first insulating layer 11 and the second insulating layer 13 stacked on the flexible substrate 10.
  • a third insulating film and a second metal film are sequentially deposited, and the second metal film is patterned through a patterning process to form a third insulating layer 15 covering the first gate metal layer, and a second insulating layer 15 disposed on the third insulating layer 15
  • the second gate metal layer pattern is formed on the substrate area 300, and includes at least the third capacitor electrode 42A, the fourth capacitor electrode 42B and the second gate lead (not shown).
  • the position of the third capacitor electrode 42A is the same as The position of the first capacitor electrode 41A corresponds to the position of the fourth capacitor electrode 42B and the position of the second capacitor electrode 41B.
  • the cutting area 400 includes the first insulating layer 11, the second insulating layer 13, and the third insulating layer 15 stacked on the flexible substrate 10.
  • a fourth insulating film is deposited, and the fourth insulating film is patterned through a patterning process to form a pattern of the fourth insulating layer 16 covering the second gate metal layer.
  • the fourth insulating layer 16 is provided with a plurality of first via holes.
  • the first via holes are formed in the substrate area 300, and their positions correspond to the positions of the two ends of the first active layer 12A, the second active layer 12B, and the third active layer 12C, respectively.
  • the fourth insulating layer 16, the third insulating layer 15 and the second insulating layer 13 are etched away, exposing the surfaces of the first active layer 12A, the second active layer 12B, and the third active layer 12C, respectively.
  • the cutting area 400 includes the first insulating layer 11, the second insulating layer 13, the third insulating layer 15 and the fourth insulating layer 16 stacked on the flexible substrate 10.
  • the source-drain metal layer is formed in the substrate area 300 and includes at least the first source electrode 17A , The first drain electrode 18A, the second source electrode 17B, the second drain electrode 17B, the third source electrode 17C, the third drain electrode 17C, the low voltage (VSS) line 105, a plurality of data lines (not shown) and a plurality of In the data lead pattern, the first source electrode 17A and the first drain electrode 18A are respectively connected to the first active layer 12A through the first via hole, and the second source electrode 17B and the second drain electrode 17B are respectively connected through the first via hole and the second The active layer 12B is connected, and the third source electrode 17C and the third drain electrode 17C are respectively connected to the third active layer 12C through the first via hole.
  • the source-drain metal layer may further include any one or more of a power supply line (VDD), a compensation line, and an auxiliary cathode.
  • the source-drain metal layer is also referred to as a first source Drain metal layer (SD1).
  • SD1 first source Drain metal layer
  • the cutting area 400 includes a composite insulating layer disposed on the flexible substrate 10.
  • the composite insulating layer includes a first insulating layer 11, a second insulating layer 13, a third insulating layer 15, and a fourth insulating layer. 16 and a fifth insulating layer 19.
  • the driving structure layer pattern is prepared on the flexible substrate 10, as shown in FIG. 5.
  • the first active layer 12A, the first gate electrode 14A, the first source electrode 17A, and the first drain electrode 18A constitute the first transistor 101
  • the two drain electrodes 18B constitute the second transistor 102
  • the third active layer 12C, the third gate electrode 14C, the third source electrode 17C and the third drain electrode 18C constitute the third transistor 103
  • the first capacitor electrode 41A and the third capacitor electrode 42A constitutes the first storage capacitor 104A
  • the second capacitor electrode 42B and the fourth capacitor electrode 42B constitute the second storage capacitor 104B
  • multiple gate leads and data leads constitute the gate driver on the array substrate (Gate Driver on Array, GOA for short).
  • the first transistor 101 may be a driving transistor in a pixel driving circuit
  • the second transistor 102 may be a scan transistor that outputs a scan (SCAN) signal in GOA
  • the third transistor 103 may be an output transistor in GOA.
  • the enabling transistor of the energy (EM) signal, the driving transistor, the scanning transistor, and the enabling transistor may all be thin film transistors (TFTs for short).
  • the substrate area 300 can be divided into a display area 310, a peripheral circuit area 320, and a peripheral area 330.
  • the peripheral area 330 is adjacent to the cutting area 400.
  • the display area 310 is located on the side of the peripheral area 330 away from the cutting area 400.
  • the peripheral circuit area 320 Located between the display area 310 and the peripheral area 330.
  • the cutting area 400 can be divided into a cutting pass area 410, a cutting inner area 420, and a cutting outer area 430.
  • the cutting pass area 410 is located in the middle of the cutting area 400 and is the area where the cut is formed when cutting the display motherboard.
  • the cutting inner area 420 is located in the cutting pass.
  • the area 410 is adjacent to one side of the substrate area 300, and the cutting outer area 430 is located on the side of the scribe lane area 410 away from the substrate area 300.
  • the dicing bead area 410 and the cutting outer area 430 are cut away, and the cutting inner area 420 is retained.
  • the peripheral area 330 of the substrate area 300 and the cut inner area 420 of the cutting area 400 constitute the edge area 500 of the display substrate, as shown in FIG. 6.
  • the first groove 31 and the second groove 32 are formed in the cutting area 400
  • the first groove 31 exposes the second barrier layer 10E of the flexible substrate 10
  • the second groove 32 exposes the first groove.
  • the groove 31, that is, the orthographic projection of the first groove 31 on the flexible substrate 10 includes the orthographic projection of the second groove 32 on the flexible substrate 10.
  • the first groove 31 and the second groove 32 are referred to as grooves.
  • the crack dam 33 is formed in the peripheral area 330 of the substrate area 300, that is, in the edge area 500.
  • the crack dam 33 includes a plurality of spaced cracks, and each crack exposes the surface of the first insulating layer 11, as shown in FIG.
  • the cutting area 400 includes a composite insulating layer provided on the flexible substrate 10 with grooves.
  • the widths of the first groove 31 and the second groove 32 in the grooves are both larger than the width of the scribe track area 410.
  • two patterning processes may be used to form the first groove 31, the second groove 32, and the crack dam 33.
  • the fifth insulating layer 19, the fourth insulating layer 16, the third insulating layer 15 and the second insulating layer 13 of the cutting area 400 and the peripheral area 330 are etched through the first mask (Etch Bending A MASK, EBA MASK),
  • a second groove 32 is formed on the second insulating layer 13, the third insulating layer 15, the fourth insulating layer 16 and the fifth insulating layer 19 of the cutting area 400, and the second insulating layer 13, the third insulating layer
  • the insulating layer 15, the fourth insulating layer 16 and the fifth insulating layer 19 are formed with a crack dam 33, the second groove 32 and the fifth insulating layer 19, the fourth insulating layer 16, the third insulating layer 15 and the inside of the crack dam 33
  • the second insulating layer 13 is etched away, exposing the surface of the first insulating layer 11.
  • first insulating layer 11 in the second groove 32 in the cutting area 400 and the second sub-layer of the second barrier layer 10E of the flexible substrate 10 are etched through a second mask (Etch Bending B MASK, EBB MASK for short) , A first groove 31 is formed on the second sub-layer of the second barrier layer 10E and the first insulating layer 11, and the first insulating layer 11 in the first groove 31 and the second sub-layer of the second barrier layer 10E are covered by It is etched away to expose the surface of the first sub-layer of the second barrier layer 10E of the flexible substrate 10.
  • a second mask Etch Bending B MASK, EBB MASK for short
  • the second groove 32 exposes the first groove 31, that is, the first insulating layer 11 and the first sublayer of the second barrier layer 10E of the flexible substrate are exposed, and the first groove 31 is exposed
  • the first sublayer of the second barrier layer 10E of the flexible substrate 10 forms a stepped groove structure.
  • the second barrier layer 10E can be understood to be composed of a first sublayer and a second sublayer that are stacked, the first sublayer is disposed on the second flexible layer 10D, and the second sublayer is disposed on the first sublayer. On one sub-layer, the first insulating layer 11 is arranged on the second sub-layer.
  • the second sub-layer in the second groove 32 is etched away, and the first sub-layer is retained, that is, the formed first groove 31 is opened in the first insulating layer 11 and part of the thickness On the second barrier layer 10E.
  • the first sublayer is referred to as the remaining part of the second barrier layer 10E
  • the second sublayer is referred to as the etched part of the second barrier layer 10E.
  • a plurality of spaced apart cracks expose the surface of the first insulating layer 11, forming a concave-convex crack dam structure.
  • the EBA MASK and EBB MASK processes are patterning processes for grooving the bending area of the display mother board to reduce the thickness of the bending area.
  • the uneven crack dam structure formed in the peripheral area 330 is used to avoid affecting the film structure of the display area 310 and the peripheral circuit area 320 during the cutting process of the display mother board.
  • the force of the small display area 310 and the peripheral circuit area 320 can be cut off and the cracks can be transmitted to the display area 310 and the peripheral circuit area 320.
  • the inner sidewalls of the first groove 31 and the second groove 32 may be set by setting process parameters.
  • the slope, the angle ⁇ between the bus bar of the slope and the normal direction of the display substrate is 20° to 50°.
  • the depth h1 of the first groove 31 is smaller than the depth h2 of the second groove 32.
  • the depth h1 of the first groove 31 (that is, the thickness of the second step) may be 0.2 ⁇ m to 1.3 ⁇ m
  • the depth h2 of the second groove 32 (that is, the thickness of the third step) may be 0.5 ⁇ m to 1.4 ⁇ m.
  • the first flat layer 20 is developed away, exposing the surface of the fifth insulating layer 19. In the peripheral area 330 of the substrate area 300, the first flat layer 20 completely fills the cracks in the crack dam 33. In the cutting area 400, the first flat layer 20 completely fills the first groove 31 and the second groove 32, and has a relatively flat surface, that is, the surface of the first flat layer 20 of the cutting area 400 away from the flexible substrate 10 is relatively flat Qi-like, as shown in Figure 7. In an exemplary embodiment, the thickness of the first flat layer 20 may be 0.8 ⁇ m to 1.5 ⁇ m.
  • the cutting area 400 includes a composite insulating layer provided on the flexible substrate 10 with grooves and a first flat layer 20 provided on the composite insulating layer and filling the grooves.
  • the inorganic layer in the packaging layer directly contacts the fifth insulating layer 19 and the fourth insulating layer 16 to ensure the packaging effect and process quality.
  • a fourth metal film is deposited on the flexible substrate forming the aforementioned pattern, and the fourth metal film is patterned through a patterning process to form a metal conductive layer pattern on the first flat layer 20, and the metal conductive layer includes at least the first connecting electrode 106 and the second connection electrode 107.
  • the first connection electrode 106 is arranged in the display area 310 and is connected to the first drain electrode of the first transistor 101 through the second via hole.
  • the second connection electrode 107 is arranged in the peripheral circuit area 320 and passes through the The three vias are connected to the low voltage line 105 and extend toward the peripheral area 330 to cover the first flat layer 20 between the third via and the partition, as shown in FIG. 8.
  • the metal conductive layer is also referred to as the second source/drain metal layer (SD2).
  • the metal conductive layer may also include any one of a power line, a power lead, a low voltage lead, and an auxiliary cathode.
  • the cutting area 400 can also be provided with a metal conductive layer, such as a signal line for testing. In this patterning process, since the grooves of the cutting area 400 are filled with the first flat layer 20, the fourth metal film is formed on the flat surface of the first flat layer 20, eliminating the positions of the fourth metal film in the cutting area 400 The height difference of the metal film is avoided, and the metal film will not be etched completely, and there will be no metal block residue after the patterning process.
  • the second flat layer 21 of the second flat layer 21 in the fifth via hole close to the sidewall of the via is developed, exposing the second connecting electrode 107
  • the gap 34 is arranged between the fourth via hole and the fifth via hole, and the first flat layer 20 and the second flat layer 21 in the gap 34 are developed away, exposing the surface of the fifth insulating layer 19.
  • the area where the crack dam 33 is located and the second flat layer 21 in the area where the partition is located are developed, exposing the first flat layer 20 and the partition.
  • the second flat layer 21 is provided in a part of the cutting inner region 420 and a part of the cutting outer region 430, and the second flat layer 21 in other positions is developed to expose the surface of the first flat layer 20, As shown in Figure 9.
  • the thickness of the second flat layer 21 may be 0.8 ⁇ m to 1.5 ⁇ m.
  • the position of the second flat layer 21 in the cutting area 400 will be described in detail later.
  • the orthographic projection of the opening of the second flat layer 21 on the flexible substrate 10 includes the opening of the first flat layer 20, that is, the opening width of the second flat layer 21 is greater than the opening width of the first flat layer 20.
  • the opening of a flat layer 20 exposes the fifth insulating layer 19, and the opening of the second flat layer 21 exposes the opening of the first flat layer 20.
  • a step is formed on the sidewall of the gap 34, so that the subsequently formed cathode also has a step Shape to ensure a reliable connection between the cathode and the third connecting electrode.
  • the cutting area 400 includes a composite insulating layer provided on the flexible substrate 10 with grooves and a first flat layer 20 provided on the composite insulating layer and filling the grooves.
  • the gap 34 formed in the peripheral circuit area 320 is used to discharge the gas generated during the process of the planarization (PLN) film layer, and to improve the process quality.
  • the third connection electrode 108 provided in the slit 34 is also stepped. After this patterning process, the film structure of the cutting area 400 and the peripheral area 330 (the area where the crack dam 33 is located) has not changed.
  • the definition layer 24 is formed in the display area 310, and a pixel opening is opened thereon, and the pixel definition film in the pixel opening is developed, exposing the surface of the anode 23.
  • the first dam foundation 201 and the second dam foundation 202 are formed in the peripheral circuit area 320, the first dam foundation 201 is disposed on the third connection electrode 108 in the fifth via hole, and the second dam foundation 202 is disposed between the fifth via hole and the partition.
  • the cross-sectional shapes of the first dam foundation 201 and the second dam foundation 202 are trapezoidal, as shown in FIG. 11.
  • the first dam foundation 201 and the second dam foundation 202 are used to form two supporting dams. After this patterning process, the film structure of the cutting area 400 and the peripheral area 330 (the area where the crack dam 33 is located) has not changed.
  • the organic light emitting layer 25 includes a stacked hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer, and is formed in the pixel opening of the substrate area 300 to realize the connection between the organic light emitting layer 25 and the anode 23. Since the anode 23 is connected to the first connection electrode 106, and the first connection electrode 106 is connected to the drain electrode of the first transistor 101, the light emission control of the organic light emitting layer 25 is realized.
  • a part of the cathode 26 is formed on the organic light-emitting layer 25, the cathode 26 is connected to the organic light-emitting layer 25, and the other part of the cathode 26 is formed in the area between the pixel opening and the fifth via hole.
  • the cathode 26 passes through the gap 34 and the fifth via hole. It is connected to the third connection electrode 108. Since the third connection electrode 108 is connected to the second connection electrode 107, and the second connection electrode 107 is connected to the low voltage line 105, the cathode 26 and the low voltage line 105 are connected.
  • the formed cathode 26 also has a stepped shape and contacts the third connecting electrode 108 on different steps, ensuring reliable connection between the cathode and the third connecting electrode 108 .
  • the film structure of the cutting area 400 and the peripheral area 330 (the area where the crack dam 33 is located) has not changed.
  • An encapsulation layer 27 is formed on the basis of forming the aforementioned pattern.
  • the encapsulation layer 27 is formed in the display area 310 and the peripheral circuit area 320 of the substrate area 300.
  • the laminated structure of inorganic material/organic material/inorganic material is adopted.
  • the material layer is arranged in the display area 310 and the peripheral circuit area 320, wrapping the first supporting dam and the second supporting dam, and the organic material layer is arranged between the two inorganic material layers on the side of the first supporting dam away from the peripheral area 330, As shown in Figure 14.
  • the first flat layer 20 is formed with a partition exposing the surface of the fifth insulating layer 19
  • two inorganic material layers are directly formed on the fifth insulating layer 19 in the partition to ensure the packaging effect and process quality.
  • the film structure of the cutting area 400 and the peripheral area 330 has not changed.
  • the display mother board is peeled off from the glass carrier 1 by a peeling process, and then the display mother board is laminated on the back of the display mother board (the side surface of the flexible substrate 10 away from the film layer).
  • the cutting device cuts along the cutting lane area 410 of the cutting area 400, and the cutting bar L separates the display mother board from the disclosed display substrate, as shown in FIG. 16. After the cutting is completed, the cutting lane area 410 and the cutting outer area 430 of the cutting area 400 are cut away, and the cutting inner area 420 remains.
  • the peripheral area 330 of the substrate area 300 and the cutting inner area 420 of the cutting area 400 constitute the display substrate of the present disclosure.
  • the edge area 500 is shown in FIG. 3.
  • the edge area 500 of the substrate includes a flexible substrate 10 and a composite insulating layer disposed on the flexible substrate 10.
  • the composite insulating layer is composed of a plurality of inorganic insulating layers, including stacking on the flexible substrate 10.
  • the first insulating layer 11, the second insulating layer 13, the third insulating layer 15, the fourth insulating layer 16 and the fifth insulating layer 19 are included.
  • the flexible substrate 10 and the composite insulating layer form a step structure, and the step structure includes a first flexible layer 10A, a first barrier layer 10B, an amorphous silicon layer 10C, and a second flexible substrate 10 of the flexible substrate 10
  • the third step 53 formed by the layer 13, the third insulating layer 15, the fourth insulating layer 16 and the fifth insulating layer 19, the height of the first step 51, the second step 52 and the third step 53 is from the cutting inner region 420 to the periphery
  • the direction of the area 330 increases sequentially, that is, the direction from the first step 51 to the third step 53 increases sequentially.
  • the cutting inner area 420 also includes a first flat layer 20 and a second flat layer 21 disposed on the first flat layer 20.
  • the first flat layer 20 covers the above-mentioned step structure.
  • the outer edge of the first flat layer 20 (away from the peripheral area 330) The end surface on one side) is substantially flush with the outer edge of the flexible substrate 10, and the second flat layer 21 is provided at the junction area of the first step 51 and the second step 52.
  • the composite insulating layer is formed with a crack dam 33 and a first flat layer 20 covering the crack dam 33.
  • the crack dam 33 includes a plurality of spaced cracks arranged in the composite insulating layer.
  • the second insulating layer 13, the third insulating layer 15, the fourth insulating layer 16 and the fifth insulating layer 19 are removed, exposing the surface of the first insulating layer 11.
  • the first flat layer 20 of the peripheral area 330 covers the crack dam 33 and fills a plurality of spaced cracks in the crack dam 33.
  • the surface of the first flat layer 20 of the peripheral region 330 is substantially flush with the surface of the first flat layer 20 of the cut inner region 420.
  • FIG. 17 is a schematic diagram showing the structure of the edge region of the substrate according to the present disclosure.
  • the side walls of the second step 52 and the third step 53 are slope surfaces, and the included angle ⁇ between the bus bar of the slope surface and the normal direction of the display substrate is 20° to 50°.
  • the thickness h0 of the first step 51 is greater than the thickness h2 of the third step 53, and the thickness h0 of the first step 51 is greater than the thickness h1 of the second step 52.
  • the thickness h2 of the third step 53 may be greater than the thickness h1 of the second step 52.
  • the thickness of the step refers to the distance between the upper surface of the step and the lower surface of the step.
  • the thickness h0 of the first step 51 may be 15 ⁇ m to 20.7 ⁇ m
  • the thickness h1 of the second step 52 may be 0.2 ⁇ m to 1.3 ⁇ m
  • the thickness h2 of the third step 53 may be 0.5 ⁇ m to 1.4 ⁇ m
  • the thickness h0 of the first step 51 may be 17.654 ⁇ m
  • the thickness h1 of the second step 52 may be 0.76 ⁇ m
  • the thickness h2 of the third step 53 may be 0.80 ⁇ m.
  • the thickness of the first sub-layer may be 0.05 ⁇ m to 0.06 ⁇ m
  • the thickness of the second sub-layer may be 0.44 ⁇ m to 0.55 ⁇ m, that is, in the second barrier layer 10E having a thickness of 0.4 ⁇ m to 0.7 ⁇ m
  • the etched thickness can be 0.44 ⁇ m to 0.55 ⁇ m, and the remaining thickness can be 0.05 ⁇ m to 0.06 ⁇ m.
  • the thickness of the second barrier layer 10E may be 0.55 ⁇ m
  • the thickness of the first sub-layer may be 0.054 ⁇ m
  • the thickness of the second sub-layer may be 0.496 ⁇ m.
  • the surface of the first sub-layer adjacent to the second flexible layer (the surface of the second barrier layer adjacent to the second flexible layer, or the surface of the second flexible layer adjacent to the second barrier layer ) Is the reference surface
  • the distance between the upper surface of the first step 51 and the reference surface may be 0.05 ⁇ m to 0.06 ⁇ m
  • the distance between the upper surface of the second step 52 and the reference surface may be 0.75 ⁇ m to 0.95 ⁇ m
  • the distance between the upper surface of the three steps 53 and the reference surface may be 1.40 ⁇ m to 1.80 ⁇ m.
  • the distance between the upper surface of the first step 51 and the reference surface may be 0.054 ⁇ m
  • the distance between the upper surface of the second step 52 and the reference surface may be 0.812 ⁇ m
  • the distance between the upper surface of the second step 52 and the reference surface may be 0.812 ⁇ m.
  • the distance between the upper surface and the reference surface can be 1.614 ⁇ m.
  • the distance from the edge of the first step 51 to the edge of the second step 52 is s1, s1 is referred to as the width of the first step 51, and the distance from the edge of the second step 52 to the edge of the third step 53 S2 is referred to as the width of the second step 52, the distance from the edge of the third step 53 to the edge of the crack dam is s3, and s3 is referred to as the width of the third step 53.
  • the width s1 of the first step 51 is greater than the width s2 of the second step 52, and the width s1 of the first step 51 is greater than the width s3 of the third step 53.
  • the width s1 of the first step 51 may be 55 ⁇ m to 210 ⁇ m
  • the width s2 of the second step 52 may be 5 ⁇ m to 40 ⁇ m
  • the width s3 of the third step 53 may be 5 ⁇ m to 15 ⁇ m
  • the width s3 of the second step 52 may be 5 ⁇ m to 15 ⁇ m.
  • the width s2 of the third step 53 may be greater than or equal to the width s3 of the third step 53.
  • the width s1 of the first step 51 may be 105 ⁇ m. In other possible implementation manners, the width s1 of the first step 51 may be 160 ⁇ m.
  • the width s2 of the second step 52 may be 35 ⁇ m, and the width s3 of the third step 53 may be 6 ⁇ m. In some possible implementations, the width s2 of the second step 52 may be 10 ⁇ m, and the width s3 of the third step 53 may be 10 ⁇ m.
  • the orthographic projection of the second flat layer 21 of the edge region 500 on the flexible substrate 10 partially overlaps the orthographic projection of the first step 51 and the second step 52 on the flexible substrate 10, that is, the second flat layer
  • the orthographic projection of 21 on the flexible substrate 10 overlaps with the orthographic projection of part of the second step 52 on the flexible substrate 10 and overlaps with the orthographic projection of part of the first step 51 on the flexible substrate 10.
  • the distance from the edge of the second flat layer 21 of the edge area 500 away from the display area to the edge of the second step 52 is s4, and s4 is called the second flat layer 21 covering the width of the first step 51, that is, the second flat layer 21 is flexible
  • the distance between the second flat layer 21 of the edge area 500 adjacent to the edge of the display area and the edge of the second step 52 is s5, and s5 is called the second flat layer 21 covering the width of the second step 52, that is, the second flat layer 21 is flexible
  • the width s4 of the second flat layer 21 covering the first step 51 may be 10 ⁇ m to 20 ⁇ m, and the width s5 of the second flat layer 21 covering the second step 52 may be 20 ⁇ m to 30 ⁇ m.
  • the width s4 of the second flat layer 21 covering the first step 51 may be 15 ⁇ m, and the width s5 of the second flat layer 21 covering the second step 52 may be 25 ⁇ m.
  • the width s6 of the second flat layer 21 of the edge area 500 may be 30 ⁇ m to 50 ⁇ m.
  • the width s6 of the second flat layer 21 of the edge region 500 may be 40 ⁇ m.
  • the second flat layer 21 by disposing the second flat layer 21 in the boundary area between the first step 51 and the second step 52, the second flat layer 21 covers the area where the slope sidewall of the second step 52 is located, and in the subsequent In the patterning process of forming the pattern of the anode 23 and the third connecting electrode 108, the etching residue of the transparent conductive film can be avoided, and the process quality can be improved.
  • the substrate area may further include a touch layer or a touch panel provided on the encapsulation layer and a protective layer (OC) covering the touch layer or the touch panel.
  • the display substrate area may further include a protective film (Temporary Protect Film, TPF for short), the protective film is attached to the packaging layer, and the protective film is used to protect the film structure of the display substrate. The back film operation is performed after attaching the protective film. After the cutting is completed, the protective film is first removed, and then a touch layer and a cover plate are sequentially arranged on the packaging layer to form a touch display panel; or a cover plate is directly arranged on the packaging layer to form a display panel.
  • TPF Temporary Protect Film
  • the first insulating film, the second insulating film, the third insulating film, the fourth insulating film, and the fifth insulating film may be silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) Any one or more of these may be a single layer, a multi-layer or a composite layer.
  • the first insulating layer is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate
  • the second and third insulating layers are called gate insulating (GI) layers
  • the fourth insulating layer is called a layer
  • the fifth insulation layer is called the passivation (PVX) layer.
  • Organic materials may be used for the first flat layer and the second flat layer.
  • the first metal film, the second metal film, the third metal film, and the fourth metal film can be made of metal materials, such as any one of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo) or More kinds, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can have a single-layer structure or a multilayer composite structure, such as Mo/Cu/Mo.
  • the cathode can be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or made of any one or more of the above metals Alloy.
  • the active layer film can use amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si) , Hexathiophene, polythiophene and other materials, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology.
  • the transparent conductive film can be indium tin oxide ITO or indium zinc oxide IZO, and the pixel definition layer can be polyimide, acrylic or polyethylene terephthalate.
  • the display substrate provided by the present disclosure includes:
  • the flexible substrate 10 includes a first flexible layer 10A, a first barrier layer 10B, an amorphous silicon (a-si) layer 10C, a second flexible layer 10D, and a second barrier layer 10E that are sequentially stacked;
  • a-si amorphous silicon
  • the first insulating layer 11 disposed on the flexible substrate 10;
  • the fourth insulating layer 16 covering the second gate metal layer, the display area 310 and the fourth insulating layer 16 of the peripheral circuit area 320 are provided with a plurality of first vias, and the plurality of first vias respectively expose the first active Layer 12A, second active layer 12B and third active layer 12C;
  • the source and drain metal layers are provided on the fourth insulating layer 16, the source and drain metal layers are provided in the display area 310 and the peripheral circuit area 320, and the source and drain metal layers include at least the first source electrode 17A and the first drain electrode 18A of the display area 310 , And the second source electrode 17B, the second drain electrode 18B, the third source electrode 17C, the third drain electrode 18C and the low voltage line 105 of the peripheral circuit area 320, the first source electrode 17A and the first drain electrode 18A respectively pass through the first
  • the via hole is connected to the first active layer 12A, the second source electrode 17B and the second drain electrode 18B are respectively connected to the second active layer 12B through the first via hole, and the third source electrode 17C and the third drain electrode 18C respectively pass through The first via is connected to the third active layer 12C;
  • the fifth insulating layer 19 covering the source and drain metal layers is provided in the display area 310 and part of the peripheral circuit area 320; the composite insulating layer formed in the peripheral area 330 is provided with a crack dam 33, which includes a plurality of spaces
  • the first insulating layer 11 is exposed by the cracks; the composite insulating layer formed by the cutting area 400 is provided with grooves, and the grooves expose the first sublayer of the second barrier layer 10E of the flexible substrate 10, and the grooves include the first sublayer of the second barrier layer 10E.
  • the groove 31 and the second groove 32, the first groove 31 is provided on the second sub-layer of the second barrier layer 10E and the first insulating layer 11, exposing the first sub-layer of the second barrier layer 10E of the flexible substrate 10 Layer, the second groove 32 is provided on the second insulating layer 13, the third insulating layer 15, the fourth insulating layer 16, and the fifth insulating layer 19, exposing the first groove 31;
  • the first planar layer 20 Covering the first planar layer 20 of the foregoing structure; in the display area 310, the first planar layer 20 is provided with a second via hole, and in the peripheral circuit area 320, the first planar layer 20 is provided with a third via and a partition.
  • the second via hole exposes the first drain electrode 18A
  • the third via hole exposes the low voltage line 105
  • the partition exposes the fifth insulating layer 19
  • in the peripheral area 330 the first flat layer 20 completely fills the crack dam 33, in the cutting area 400 , The first flat layer 20 completely fills the groove;
  • the first drain electrode 18A is connected, and the second connection electrode 107 is connected to the low voltage line 105 through a third via;
  • the four via holes expose the first connection electrode 106, the fifth via hole exposes the second connection electrode 107, and the gap 34 exposes the fifth insulating layer 19;
  • the anode 23 and the third connection electrode 108 are arranged on the second flat layer 23.
  • the anode 23 is formed in the display area 310, the third connection electrode 108 is formed in the peripheral circuit area 320, and the anode 23 is connected to the first connection electrode through the fourth via hole.
  • 106 is connected, and the third connection electrode 108 is connected to the second connection electrode 107 through the fifth via;
  • the pixel definition layer 24 of the display area 310 and the first dam base 201 and the second dam base 202 of the peripheral circuit area 320 are provided.
  • the pixel definition layer 24 is provided with a pixel opening, and the pixel opening exposes the anode 23.
  • the first dam base 201 is provided on the On the third connection electrode 108 in the five via holes, the second dam base 202 is arranged on the side of the first dam base 201 adjacent to the cutting area 400;
  • the organic light-emitting layer 25 is arranged in the display area 310, and the organic light-emitting layer 25 is connected to the anode 23;
  • the cathode 26 is arranged in the display area 310 and the peripheral circuit area 320, and the cathode 26 is connected to the organic light-emitting layer 25 and the third connecting electrode 108, respectively;
  • the encapsulation layer 27 is provided in the display area 310 and the peripheral circuit area 320.
  • FIG. 18 is a schematic diagram of the structure of the binding area of the disclosure.
  • the binding area 302 in a plane parallel to the display substrate, the binding area 302 is located on one side of the display area 310, and the binding area 302 includes a first fan-out area 303, a bending area 304, and a second fan-out area 305.
  • Anti-static area 306, driver chip area 307, binding needle area 308, and the composite insulating layer of the bending area 304 are removed by EBA MASK and EBB MASK processes to reduce the thickness of the bending area.
  • the aforementioned process of forming the first groove and the second groove and the process of removing the composite insulating layer in the bending region 304 are performed simultaneously.
  • the binding area 302 is far away from the display area 310, and an array test unit 600 is also provided.
  • the array test unit 600 is connected to the binding pin area 308 through a signal line and is configured to The display substrate is tested to check whether there is a short circuit, open circuit, etc.
  • the outer side of the binding area 302 is provided with a first cutting line 701 and a second cutting line 702.
  • the second cutting line 702 is a fine cutting line and located at the periphery of the binding area 302.
  • the shape of the second cutting line 702 is the same as that of the binding area 302.
  • the first cutting line 701 is a thick cutting line and is located at the periphery of the second cutting line 702.
  • the shape of the first cutting line 701 is the same as the contour of the second cutting line 702, but the binding area 302 is the same as the array test unit Only the second cutting line 702 is set between 600. On the side of the array test unit 600 away from the binding area 302, at least one first cutting line 701 is also provided. After completing the film layer process of the display mother board, the cutting device cuts the display mother board along the first cutting line 701 (thick cutting line) to form a plurality of substrate areas. After the display substrate test is completed, the cutting device cuts along the second Line 702 (fine cutting line) cuts the substrate area to form a display substrate.
  • Fig. 19 is a cross-sectional view taken along the line B-B in Fig. 18.
  • the binding area 302 includes: a first insulating layer 11 arranged on the flexible base 10, a second insulating layer 13 arranged on the first insulating layer 11, and a second insulating layer 13 arranged on the second insulating layer 13.
  • a plurality of first leads are arranged in the same layer as the aforementioned source and drain metal layers and are formed simultaneously through the same patterning process, and a plurality of second leads are arranged in the same layer as the aforementioned metal conductive layer and are formed at the same time through the same patterning process.
  • the bonding area 302 may further include a wire provided in the same layer as the aforementioned first gate metal layer, or may include a wire provided in the same layer as the aforementioned second gate metal layer.
  • the cutting area located outside the binding area includes a composite insulating layer disposed on the flexible substrate 10 and a first flat layer 20.
  • the composite insulating layer is provided with a stepped groove, and the first flat layer 20 fills the groove.
  • Figure 19 illustrates the structure of the groove.
  • the right side of the groove is the step structure of the edge area
  • the left side of the groove is the step structure of the cutting outer area 430.
  • the cutting outer area 430 is called a dummy area.
  • the double dashed line in the middle part represents the cutting line.
  • the characteristics of the step structure of the edge area and the corresponding geometric parameters have been described in detail in FIG. 17, and will not be repeated here.
  • the side walls of the second step 52' of the virtual area and the third step 53' of the virtual area are slope surfaces, and the bus bar of the slope surface is sandwiched by the normal direction of the display substrate.
  • the angle ⁇ is 20° to 50°.
  • the thickness h0 of the first step 51' of the virtual area is greater than the thickness h2 of the third step 53' of the virtual area, and the thickness h0 of the first step 51' of the virtual area is greater than that of the second step 52 of the virtual area. 'The thickness h1.
  • the thickness h2 of the third step 53' of the dummy area may be greater than the thickness h1 of the second step 52' of the dummy area.
  • the thickness h0 of the first step 51' of the dummy area may be 15 ⁇ m to 20.7 ⁇ m
  • the thickness h1 of the second step 52' of the dummy area may be 0.2 ⁇ m to 1.3 ⁇ m
  • the third step of the dummy area The thickness h2 of 53' may be 0.5 ⁇ m to 1.4 ⁇ m.
  • the thickness h0 of the first step 51' of the virtual area may be 17.654 ⁇ m
  • the thickness h1 of the second step 52' of the virtual area may be 0.76 ⁇ m
  • the thickness of the third step 53' of the virtual area h2 can be 0.80 ⁇ m.
  • the distance from the edge of the first step 51' of the virtual area to the edge of the second step 52' of the virtual area is s1', and s1' is referred to as the width of the first step 51' of the virtual area.
  • the distance from the edge of the second step 52' of the area to the edge of the third step 53' of the virtual area is s2', s2' is called the width of the second step 52' of the virtual area, and the distance of the first step 51' of the virtual area
  • the width s1' is greater than the width s2' of the second step 52 of the dummy area.
  • the width s1 ′ of the first step 51 ′ of the dummy area is 55 ⁇ m to 155 ⁇ m, and the width s2 ′ of the second step 52 ′ of the dummy area is 5 ⁇ m to 15 ⁇ m.
  • the width s1 ′ of the first step 51 ′ of the dummy area is 105 ⁇ m.
  • the width s2' of the second step 52' of the dummy area is 10 ⁇ m.
  • the orthographic projection of the second flat layer 21 of the virtual area on the flexible substrate 10 includes the orthographic projection of the second step 52' and the third step 53' of the virtual area on the flexible substrate 10, including part of the virtual area.
  • the width s4 ′ of the first step 51 ′ of the second flat layer 21 covering the dummy area is 10 ⁇ m to 20 ⁇ m. In some possible implementations, the width s4 ′ of the first step 51 ′ of the second flat layer 21 covering the dummy area is 15 ⁇ m.
  • Fig. 20 is a cross-sectional view taken along the line C-C in Fig. 18.
  • the binding area 302 includes a binding circuit area 311 and a binding cutting area 312, a first fan-out area 303, a bending area 304, and a second fan
  • the exit area 305, the anti-static area 306, the driver chip area 307 and the binding needle area 308 are arranged in the binding circuit area 311, and the second cutting line 702 between the binding area 302 and the array test unit 600 is arranged in the binding cutting area 312.
  • the first flat layer 20 and the second flat layer 21 When the first flat layer 20 and the second flat layer 21 are formed, the first flat layer 20 and the second flat layer 21 in the area where the cutting area 312 and the array test unit 600 are located are removed, that is, along the distance away from the display area 310 In the direction, the first flat layer 20 and the second flat layer 21 extend to the boundary between the bonding circuit area 311 and the bonding cutting area 312. Since multiple signal lines are arranged between the bonding area 302 and the array test unit 600, the composite insulating layer of the bonding and cutting area 312 does not have a first groove and a second groove. After the display substrate test is completed, after the cutting device cuts the substrate area along the second cutting line 702, the edge area of the binding area 302 away from the display area forms a stepped structure.
  • the stepped structure includes a first step and a second step.
  • the step is composed of a flexible substrate and a composite insulating layer. The end faces of the flexible substrate and the composite insulating layer away from the display area are flush.
  • the second step is composed of a first flat layer and a second flat layer. The first flat layer and the second flat layer The end face on the side away from the display area is basically flush.
  • the edge area of the binding area 302 away from the display area 310 is formed with a stepped structure, except for the edge area of the binding area 302 away from the display area 310, steps are formed in the display area and other edge areas of the binding area. structure.
  • the display substrate provided by the present disclosure is provided with a first flat layer to completely fill the grooves in the cutting area, thereby avoiding metal block residues in the patterning process of the metal conductive layer.
  • the subsequent process neither Ag particles and particles will appear, nor will Ag particles and particles adhere everywhere, which effectively avoids the appearance of dark spots on the display substrate and improves the display quality.
  • the composite insulating layer and the first flat layer in the cutting area are provided with grooves exposing the substrate. Since the total depth of the groove is the sum of the thicknesses of the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the first flat layer, it not only makes the deposited metal film in each position The height of the metal film is different, and the metal film has a large height difference, resulting in incomplete etching of the metal film in the patterning process, and there are metal blocks remaining on the bottom surface of the groove and the step surface after the patterning process.
  • the first flat layer of the present disclosure is set to completely fill the grooves of the composite insulating layer, and the height of the groove area is eliminated by the first flat layer. Difference.
  • the metal film is subsequently deposited, since the cutting area has a flat surface, the height of the deposited metal film at each position is similar, so that metal lump residues in the metal film patterning process are avoided, and no Ag particles will appear in the subsequent process. , There will be no Ag particles attached everywhere.
  • the subsequently deposited metal film does not directly contact the flexible substrate, which not only avoids the chemical reaction between the metal and the organic material to produce particles, but also protects the flexible substrate from corrosion by the metal.
  • the preparation process of the present disclosure can be realized by using existing mature preparation equipment, has little improvement to the existing process, can be well compatible with the existing preparation process, is simple to implement, easy to implement, high production efficiency, and low production cost. High yield rate. In a word, the present disclosure effectively avoids dark spots caused by metal lump residues and particle contamination, ensures product yield, and improves product quality.
  • the present disclosure shows that the structure of the substrate and the preparation process thereof are only an exemplary description.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the OLED may be a top emission structure, or may be a bottom emission structure.
  • the driving transistor may be a top gate structure, or may be a bottom gate structure, may be a single gate structure, or may be a double gate structure.
  • other electrodes, leads, and structural film layers may also be provided in the driving structure layer, which is not specifically limited in the present disclosure.
  • the present disclosure also provides a display motherboard.
  • the display motherboard includes a substrate area 300 and a cutting area 400 located at the periphery of the substrate area 300.
  • the display motherboard includes: a driving structure layer disposed on the substrate area and a cutting area, a first flat layer disposed on the driving structure layer; and driving of the cutting area
  • the structural layer includes a composite insulating layer, the composite insulating layer is provided with a groove, and the first flat layer fills the groove.
  • the composite insulating layer includes a plurality of stacked inorganic insulating layers, and the groove exposes the flexible substrate.
  • the driving structure layer of the substrate region includes: a first insulating layer disposed on a flexible substrate, an active layer disposed on the first insulating layer, and a second insulating layer covering the active layer.
  • the driving structure layer of the cutting area includes: a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer stacked on a flexible substrate;
  • the flexible substrate includes a stacked first flexible layer, a first barrier layer, an amorphous silicon layer, a second flexible layer, and a second barrier layer.
  • the first insulating layer is disposed on the second barrier layer.
  • the groove exposes the second barrier layer of the flexible substrate.
  • the total thickness of the first flexible layer, the first barrier layer, the amorphous silicon layer, and the second flexible layer may be 15 ⁇ m to 20 ⁇ m, and the thickness of the second barrier layer may be 0.4 ⁇ m to 0.7 ⁇ m, the thickness of the first insulating layer may be 0.2 ⁇ m to 0.6 ⁇ m.
  • the second barrier layer includes a first sublayer and a second sublayer stacked on the second flexible layer;
  • the groove includes a first groove and a second groove,
  • the first groove is disposed on the second sublayer of the first insulating layer and the second barrier layer, and the first groove exposes the first sublayer of the second barrier layer of the flexible substrate, so
  • the second groove is disposed on the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer, and the second groove exposes the gap between the first insulating layer and the flexible substrate.
  • the first sublayer of the second barrier layer, the orthographic projection of the second groove on the flexible substrate includes the orthographic projection of the first groove on the flexible substrate.
  • the display motherboard further includes: a metal conductive layer disposed on the first flat layer, and a second flat layer covering the metal conductive layer.
  • the depth of the first groove may be 0.2 ⁇ m to 1.3 ⁇ m, and the depth of the second groove may be 0.5 ⁇ m to 1.4 ⁇ m.
  • the present disclosure also provides a method for preparing the display substrate.
  • the method of preparing the display substrate may include:
  • a drive structure layer is formed in a plurality of substrate areas and a cutting area surrounding the substrate area.
  • the drive structure layer of the cutting area includes a composite insulating layer disposed on a flexible substrate, and the composite insulating layer forms a step structure concave groove;
  • the composite insulating layer may include a plurality of stacked inorganic insulating layers, and the groove may expose the flexible substrate.
  • forming a driving structure layer in the cutting area in step S1 may include:
  • the flexible substrate may include a first flexible layer, a first barrier layer, an amorphous silicon layer, a second flexible layer, and a second barrier layer that are stacked, and the second barrier layer may include The first sub-layer and the second sub-layer are stacked on the second flexible layer; the first insulating layer may be formed on the second sub-layer of the second barrier layer; step S12 includes:
  • the first insulating layer and the second sublayer of the second barrier layer in the second groove are formed to expose the first sublayer of the second barrier layer of the flexible substrate.
  • a groove, and the second groove exposes the first groove.
  • the present disclosure provides a method for preparing a display substrate.
  • a method for preparing a display substrate By setting a first flat layer to completely fill the grooves in the cutting area, metal block residues during the patterning process of the metal conductive layer are avoided, and no Ag particles will appear in the subsequent processes. And particles, there will be no Ag particles and particles attached everywhere, effectively avoiding dark spots on the display substrate.
  • the preparation process of the present disclosure can be realized by using existing mature preparation equipment, has little improvement to the existing process, can be well compatible with the existing preparation process, is simple to implement, easy to implement, high production efficiency, and low production cost. High yield rate.
  • the present disclosure also provides a display device including the display substrate of the foregoing embodiment.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and so on.

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Abstract

提供一种显示基板，包括柔性基底（10）和设置在柔性基底（10）上的复合绝缘层，显示基板的边缘区域（500）包括由柔性基底（10）和复合绝缘层形成的台阶结构；台阶结构中台阶的高度从显示基板边缘到显示基板内部的方向依次增大；边缘区域（500）还包括覆盖台阶结构的第一平坦层（20），第一平坦层（20）的边缘与柔性基底（10）的边缘平齐。还提供显示基板的制备方法、显示母板和显示装置。

Description

显示基板及其制备方法、显示母板和显示装置
本申请要求于2020年3月23日提交中国受理局、申请号为PCT/CN2020/080700、发明名称为显示基板及其制备方法、显示母板和显示装置的PCT国际专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示母板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有自发光、广视角、高对比度、较低耗电、极高反应速度等优点。随着显示技术的不断发展，OLED技术越来越多的应用于柔性显示装置中。
目前，制备柔性OLED显示装置是先制备显示母板，然后对显示母板进行切割，从而使显示母板被分隔成多个显示基板，分开的显示基板均可以用于形成单个OLED显示装置。图1为显示母板上包括多个显示基板的排布示意图。如图1所示，显示母板100上的多个基板区域300呈周期性规则排布，切割区域400位于基板区域300的外侧。基板区域300至少包括显示区域310和绑定区域302，显示区域310包括矩阵排列的多个像素，绑定区域302包括扇出区和驱动电路，绑定区域302设置在显示区域310的一侧。切割区域400内设置有第一切割道701和第二切割道702，在显示母板的所有膜层制备完成后，切割设备分别沿着第一切割道701和第二切割道702进行粗切割和精切割，形成显示基板。
现有生产中，显示基板存在暗点不良等问题，影响了显示品质。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括柔性基底和设置在所述柔性基底上的复合绝缘层，所述显示基板的边缘区域包括由所述复合绝缘层形成的台阶结构；所述台阶结构中台阶的高度从显示基板边缘到显示基板内部的方向依次增大；所述边缘区域还包括覆盖所述台阶结构的第一平坦层，所述第一平坦层的边缘与所述柔性基板的边缘平齐。
在一些可能的实现方式中，所述台阶结构包括第一台阶、第二台阶和第三台阶，所述第一台阶的厚度大于所述第二台阶的厚度，所述第一台阶的厚度大于所述第三台阶的厚度。
在一些可能的实现方式中，所述第一台阶的厚度为15μm到20.7μm，所述第二台阶的厚度为0.2μm到1.3μm，所述第三台阶的厚度为0.5μm到1.4μm。
在一些可能的实现方式中，所述显示基板的边缘区域还包括设置在所述第一平坦层上的第二平坦层，所述第二平坦层在所述柔性基底上的正投影与所述第一台阶和第二台阶在所述柔性基底上的正投影部分重叠。
在一些可能的实现方式中，在显示基板内部到显示基板边缘的方向，所述第二平坦层在所述柔性基底上的正投影与所述第一台阶在所述柔性基底上的正投影重叠的宽度为10μm到20μm，所述第二平坦层在所述柔性基底上的正投影与所述第二台阶在所述柔性基底上的正投影重叠的宽度为20μm到30μm。
在一些可能的实现方式中，所述显示基板的基板区域包括：设置在所述柔性基底上的第一绝缘层，设置在所述第一绝缘层上的有源层，覆盖所述有源层的第二绝缘层，设置在所述第二绝缘层上的第一栅金属层，覆盖所述第一栅金属层的第三绝缘层，设置在所述第三绝缘层上的第二栅金属层，覆盖所述第二栅金属层的第四绝缘层，设置在所述第四绝缘层上的源漏金属层，覆盖所述源漏金属层的第五绝缘层，设置在所述第一平坦层上的金属导电 层，覆盖所述金属导电层的第二平坦层。
在一些可能的实现方式中，所述柔性基底包括依次叠设的第一柔性层、第一阻挡层、非晶硅层、第二柔性层和第二阻挡层，所述复合绝缘层包括在所述第二阻挡层上叠设的第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层；所述第一柔性层、第一阻挡层、非晶硅层和第二柔性层的总厚度为15μm到20μm，所述第二阻挡层的厚度为0.4μm到0.7μm，所述第一绝缘层的厚度为0.2μm到0.6μm。
在一些可能的实现方式中，所述第二阻挡层包括在所述第二柔性层上叠设的第一子层和第二子层；所述第一台阶包括所述第一柔性层、第一阻挡层、非晶硅层、第二柔性层和所述第二阻挡层的第一子层，所述第二台阶包括所述第二阻挡层的第二子层和第一绝缘层，所述第三台阶包括所述第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层；所述第一台阶的上表面与参考面之间的距离为0.05μm到0.06μm，所述第二台阶的上表面与参考面之间的距离为0.75μm到0.95μm，所述第三台阶的上表面与参考面之间的距离可以为1.40μm到1.80μm，所述参考面为所述第一子层邻近所述第二柔性层一侧的表面。
在一些可能的实现方式中，所述第二台阶和第三台阶的侧壁为坡面，所述坡面的母线与所述显示基板的法线方向的夹角为20°到50°。
在一些可能的实现方式中，第一台阶的边缘到第二台阶的边缘的距离大于第二台阶的边缘到第三台阶的边缘的距离，第一台阶的边缘到第二台阶的边缘的距离大于第三台阶的边缘到裂缝坝的边缘的距离。
在一些可能的实现方式中，第一台阶的边缘到第二台阶的边缘的距离为55μm到210μm，第二台阶的边缘到第三台阶的边缘的距离为5μm到40μm，第三台阶的边缘到裂缝坝的边缘的距离为5μm到15μm。
在一些可能的实现方式中，所述边缘区域的复合绝缘层上还设置有裂缝坝，所述裂缝坝包括多个间隔设置的裂缝，所述裂缝暴露出所述第一绝缘层；所述第一平坦层覆盖所述裂缝坝。
在一些可能的实现方式中，所述显示基板的边缘区域包括周边区和切割内区，所述切割内区位于所述周边区远离基板区域的一侧；所述台阶结构设 置在所述切割内区，所述裂缝坝设置在所述周边区。
在一些可能的实现方式中，所述显示基板的基板区域包括显示区域和设置在所述显示区域一侧的绑定区域，所述绑定区域远离所述显示区域一侧的边缘区域形成阶梯结构，所述阶梯结构包括第一阶梯和第二阶梯，所述第一阶梯由柔性基底和复合绝缘层形成，所述第二阶梯由所述第一平坦层和第二平坦层形成；除了所述绑定区域远离所述显示区域一侧的边缘区域，所述台阶结构设置在所述显示区域和绑定区域的其它边缘区域中。
另一方面，本公开还提供了一种显示母板，包括多个基板区域和围绕所述基板区域的切割区域；所述显示母板包括：设置在所述基板区域和切割区域的驱动结构层，设置在所述驱动结构层上的第一平坦层；所述切割区域的驱动结构层包括复合绝缘层，所述复合绝缘层设置有凹槽，所述第一平坦层填充所述凹槽。
在一些可能的实现方式中，所述基板区域的驱动结构层包括：设置在柔性基底上的第一绝缘层，设置在所述第一绝缘层上的有源层，覆盖所述有源层的第二绝缘层，设置在所述第二绝缘层上的第一栅金属层，覆盖所述第一栅金属层的第三绝缘层，设置在所述第三绝缘层上的第二栅金属层，覆盖所述第二栅金属层的第四绝缘层，设置在所述第四绝缘层上的源漏金属层，覆盖所述源漏金属层的第五绝缘层；所述切割区域的驱动结构层包括：在柔性基底上叠设的第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层；所述柔性基底包括叠设的第一柔性层、第一阻挡层、非晶硅层、第二柔性层和第二阻挡层；所述第一柔性层、第一阻挡层、非晶硅层和第二柔性层的总厚度为15μm到20μm，所述第二阻挡层的厚度为0.4μm到0.7μm，所述第一绝缘层的厚度为0.2μm到0.6μm。
在一些可能的实现方式中，所述第二阻挡层包括在所述第二柔性层上叠设的第一子层和第二子层；所述凹槽包括第一凹槽和第二凹槽，所述第一凹槽设置在所述第一绝缘层和第二阻挡层的第二子层上，所述第一凹槽暴露出所述第二阻挡层的第一子层，所述第二凹槽设置在所述第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层上，所述第二凹槽暴露出所述第一绝缘层和所述第二阻挡层的第一子层，所述第二凹槽在柔性基底上的正投影包含所述 第一凹槽在柔性基底上的正投影；所述第一凹槽的深度为0.2μm到1.3μm，所述第二凹槽的深度为0.5μm到1.4μm。
又一方面，本公开还提供了一种显示基板的制备方法，包括：
在多个基板区域和围绕所述基板区域的切割区域形成驱动结构层，所述切割区域的驱动结构层包括设置在柔性基底上的复合绝缘层，所述复合绝缘层形成台阶结构的凹槽；
形成覆盖所述驱动结构层的第一平坦层，所述第一平坦层填充所述凹槽；
在所述切割区域进行切割形成显示基板，在所述显示基板的边缘区域形成台阶结构；所述台阶结构中台阶的高度从显示基板边缘到显示基板内部的方向依次增大；所述第一平坦层覆盖所述台阶结构，所述第一平坦层的边缘与所述柔性基板的边缘平齐。
在一些可能的实现方式中，在切割区域形成驱动结构层，包括：
在柔性基底上依次形成第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层；所述柔性基底包括叠设的第一柔性层、第一阻挡层、非晶硅层、第二柔性层和第二阻挡层，所述第二阻挡层包括在所述第二柔性层上叠设的第一子层和第二子层；所述第一绝缘层形成在所述第二阻挡层的第二子层上；
通过第一次构图工艺，在所述第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层上形成暴露出所述第一绝缘层的第二凹槽；
通过第二次构图工艺，在所述第二凹槽内的第一绝缘层和第二阻挡层的第二子层上形成暴露出所述第二阻挡层的第一子层的第一凹槽，所述第二凹槽暴露出所述第一凹槽。
又一方面，本公开还提供了一种显示装置，包括前述的显示基板。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为显示母板上包括多个显示基板的排布示意图；
图2为显示母板切割区域金属块残留的示意图；
图3为本公开显示母板的结构示意图；
图4为本公开形成柔性基底后的示意图；
图5为本公开形成驱动结构层图案后的示意图；
图6为本公开形成凹槽和裂缝坝后的示意图；
图7为本公开形成第一平坦层图案后的示意图；
图8为本公开形成金属导电层图案后的示意图；
图9为本公开形成第二平坦层图案后的示意图；
图10为本公开形成阳极和第三连接电极图案后的示意图；
图11为本公开形成像素定义层和坝基图案后的示意图；
图12为本公开形成隔离柱图案后的示意图；
图13为本公开形成有机发光层和阴极图案后的示意图；
图14为本公开形成封装层图案后的示意图；
图15为本公开贴附背膜后的示意图；
图16为本公开切割的示意图；
图17为本公开显示基板边缘区域的结构示意图；
图18为本公开绑定区域的结构示意图；
图19为图18中B-B向的剖视图；
图20为图18中C-C向的剖视图。
附图标记说明:
1—玻璃载板；           10—柔性基底；          10A—第一柔性层；
10B—第一阻挡层；       10C—非晶硅层；         10D—第二柔性层；
10E—第二阻挡层；       11—第一绝缘层；        12A—第一有源层；
12B—第二有源层；       12C—第三有源层；       13—第二绝缘层；
14A—第一栅电极；       14B—第二栅电极；       14C—第三栅电极；
15—第三绝缘层；        16—第四绝缘层；        17A—第一源电极；
17B—第二源电极；       17C—第三源电极；       18A—第一漏电极；
18B—第二漏电极；       18C—第三漏电极；       19—第五绝缘层；
20—第一平坦层；        21—第二平坦层；        23—阳极；
24—像素定义层；        25—有机发光层；        26—阴极；
27—封装层；            31—第一凹槽；          32—第二凹槽；
33—裂缝坝；            34—缝隙；              41A—第一电容电极；
42—第二电容电极；      42A—第三电容电极；     42B—第四电容电极；
51—第一台阶；          52—第二台阶；          53—第三台阶；
100—显示母板；         101—第一晶体管；       102—第二晶体管；
103—第三晶体管；       104A—第一存储电容；    104B—第二存储电容；
105—低压线；           106—第一连接电极；     107—第二连接电极；
108—第三连接电极；     201—第一坝基；         202—第二坝基；
203—隔离柱；           300—基板区域；         302—绑定区域；
303—第一扇出区；       304—弯折区；           305—第二扇出区；
306—防静电区；         307—驱动芯片区；       308—绑定针区；
310—显示区域；         320—外围电路区；       330—周边区；
400—切割区域；         410—切割道区；         420—切割内区；
430—切割外区；         500—边缘区域；         600—阵列测试单元；
701—第一切割线；       702—第二切割线；       311—绑定电路区域；
312—绑定切割区域。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源 电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
经研究发现，显示基板存在暗点不良等问题，是由于制备过程中切割区域存在金属残留和颗粒污染等因素造成的。一种显示基板切割区域的制备过程包括：在柔性基底上依次形成第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层，为了减少后续切割工艺的切割厚度和难度，切割区域的上述绝缘层上开设有暴露出柔性基底中柔性材料层的凹槽。随后形成平坦层，切割区域的部分平坦层被去除，暴露出该凹槽。这样，切割区域的上述膜层形成台阶状的凹槽结构，凹槽的侧壁为坡面。随后沉积金属薄膜，通过构图工艺对金属薄膜进行构图，在平坦层上形成金属导电层图案。由于切割区域形成有台阶状的凹槽，不仅所沉积的金属薄膜各个位置的高度不一样，而且金属薄膜具有较大的高度差，导致构图工艺中刻蚀金属薄膜不完全，构图工艺后凹槽底面和台阶面上残留有金属块a，如图2所示。由于金属薄膜采用钛/铝/ 钛(Ti/Al/Ti)叠层结构，因此当后续工艺的刻蚀液含有银Ag离子时，残留的金属块50会置换出Ag粒子，Ag粒子混在刻蚀液中随处流动和附着，当Ag粒子附着在显示区域时，则导致显示区域出现暗点不良等缺陷。此外，由于沉积的金属薄膜和残留的金属块与柔性基底的柔性材料层直接接触，金属与有机材料发生化学反应并产生颗粒(particle)，颗粒不仅污染设备，而且也会混在刻蚀液中随处流动和附着。
本公开提供了一种显示基板，所述显示基板包括柔性基底和设置在所述柔性基底上的复合绝缘层，所述显示基板的边缘区域包括由所述复合绝缘层形成的台阶结构；所述台阶结构中台阶的高度从显示基板边缘到显示基板内部的方向依次增大；所述边缘区域还包括覆盖所述台阶结构的第一平坦层，所述第一平坦层的边缘与所述柔性基板的边缘平齐。
在示例性实施方式中，所述台阶结构包括第一台阶、第二台阶和第三台阶，所述第一台阶的厚度大于所述第二台阶的厚度，所述第一台阶的厚度大于所述第三台阶的厚度。
在示例性实施方式中，所述第一台阶的厚度为15μm到20.7μm，所述第二台阶的厚度为0.2μm到1.3μm，所述第三台阶的厚度为0.5μm到1.4μm。
在示例性实施方式中，所述显示基板的基板区域包括：设置在所述柔性基底上的第一绝缘层，设置在所述第一绝缘层上的有源层，覆盖所述有源层的第二绝缘层，设置在所述第二绝缘层上的第一栅金属层，覆盖所述第一栅金属层的第三绝缘层，设置在所述第三绝缘层上的第二栅金属层，覆盖所述第二栅金属层的第四绝缘层，设置在所述第四绝缘层上的源漏金属层，覆盖所述源漏金属层的第五绝缘层；所述第一平坦层设置在所述第五绝缘层上。
在示例性实施方式中，所述显示基板的基板区域还包括：设置在所述第一平坦层上的金属导电层，覆盖所述金属导电层的第二平坦层。
在示例性实施方式中，所述柔性基底包括依次叠设的第一柔性层、第一阻挡层、非晶硅层、第二柔性层和第二阻挡层，所述第二阻挡层包括在所述第二柔性层上叠设的第一子层和第二子层；所述复合绝缘层包括在所述第二阻挡层的第二子层上叠设的第一绝缘层、第二绝缘层、第三绝缘层、第四绝 缘层和第五绝缘层；所述第一柔性层、第一阻挡层、非晶硅层和第二柔性层的总厚度为15μm到20μm，所述第二阻挡层的厚度为0.4μm到0.7μm，所述第一绝缘层的厚度为0.2μm到0.6μm；所述台阶结构包括由所述第一柔性层、第一阻挡层、非晶硅层、第二柔性层和第二阻挡层的第一子层形成的第一台阶，由所述第二阻挡层的第二子层和第一绝缘层形成的第二台阶，以及由所述第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层形成的第三台阶，所述第一台阶、第二台阶和第三台阶的高度从所述第一台阶到第三台阶的方向依次增大。
在示例性实施方式中，所述第一台阶的上表面与参考面之间的距离为0.05μm到0.06μm，所述第二台阶的上表面与参考面之间的距离为0.75μm到0.95μm，所述第三台阶的上表面与参考面之间的距离可以为1.40μm到1.80μm，所述参考面为所述第一子层邻近所述第二柔性层一侧的表面。
在示例性实施方式中，所述第二台阶和第三台阶的侧壁为坡面，所述坡面的母线与所述显示基板的法线方向的夹角为20°到50°。
在示例性实施方式中，所述边缘区域的复合绝缘层上还设置有裂缝坝，所述裂缝坝包括多个间隔设置的裂缝，所述裂缝暴露出所述第一绝缘层；所述第一平坦层覆盖所述裂缝坝。
在示例性实施方式中，所述显示基板包括基板区域和边缘区域，所述边缘区域包括周边区和切割内区，所述切割内区位于所述周边区远离基板区域的一侧；所述台阶结构设置在所述切割内区，所述裂缝坝设置在所述周边区。
在示例性实施方式中，所述基板区域包括显示区域和设置在所述显示区域一侧的绑定区域，所述绑定区域远离所述显示区域一侧的边缘区域形成阶梯结构，所述阶梯结构包括第一阶梯和第二阶梯，所述第一阶梯由柔性基底和复合绝缘层形成，所述第二阶梯由所述第一平坦层和第二平坦层形成；除了所述绑定区域远离所述显示区域一侧的边缘区域，所述台阶结构设置在所述显示区域和绑定区域的其它边缘区域中。
图3为本公开显示基板的结构示意图，为图1中A-A向的剖视图，示意 了双源漏金属层(双SD或2SD)结构基板区域和切割区域的剖面结构。在平行于显示基板的平面方向，显示基板包括显示区域310、外围电路区320和边缘区域500，边缘区域500包括周边区330和切割内区420，切割内区420位于周边区330远离显示区域310的一侧。如图3所示，在垂直于显示基板的平面方向，本公开显示基板包括柔性基底10、设置在柔性基底10上的驱动结构层、设置在驱动结构层上的第一平坦层20、设置在第一平坦层20上的金属导电层以及覆盖金属导电层的第二平坦层21。显示区域310的驱动结构层包括形成像素驱动电路的多个晶体管，外围电路区320的驱动结构层包括形成外围电路的多个晶体管和存储电容，图3中以三个晶体管和二个存储电容为例进行示意。边缘区域500的驱动结构层包括由多个无机绝缘层组成的复合绝缘层，复合绝缘层设置有台阶结构和裂缝坝，边缘区域500的第一平坦层20覆盖并填充台阶结构和裂缝坝。
在示例性实施方式中，显示区域310和外围电路区320的驱动结构层可以包括：设置在柔性基底10上的第一绝缘层11，设置在第一绝缘层11上的有源层，覆盖有源层的第二绝缘层13，设置在第二绝缘层13上的第一栅金属层，覆盖第一栅金属层的第三绝缘层15，设置在第三绝缘层15上的第二栅金属层，覆盖第二栅金属层的第四绝缘层16，设置在第四绝缘层16上的源漏金属层，覆盖源漏金属层的第五绝缘层19。有源层至少包括第一有源层、第二有源层和第三有源层，第一栅金属层至少包括第一栅电极、第二栅电极、第三栅电极、第一电容电极和第二电容电极，第二栅金属层至少包括第三电容电极和第四电容电极，源漏金属层至少包括第一源电极、第一漏电极、第二源电极、第二漏电极、第三源电极、第三漏电极和低压线105，第一有源层、第一栅电极、第一源电极和第一漏电极组成第一晶体管101，第二有源层、第二栅电极、第二源电极和第二漏电极组成第二晶体管102，第三有源层、第三栅电极、第三源电极和第三漏电极组成第三晶体管103，第一电容电极和第三电容电极组成第一存储电容104A，第二电容电极和第四电容电极组成第二存储电容104B。显示区域310和外围电路区320还包括发光结构层，发光结构层包括：设置在第一平坦层20上的金属导电层，覆盖金属导电层的第二平坦层21，设置在第二平坦层21上的阳极23和第三连接电极108，以及像素定义层24、有机发光层25、阴极26和封装层27。金属 导电层至少包括第一连接电极106和第二连接电极107。
在示例性实施方式中，边缘区域500的驱动结构层可以包括在柔性基底10上依次叠设的第一绝缘层11、第二绝缘层13、第三绝缘层15、第四绝缘层16和第五绝缘层19，上述绝缘层均为无机绝缘层，作为本公开的复合绝缘层。台阶结构设置在切割内区420，裂缝坝设置在周边区330。在边缘区域500中的切割内区420，柔性基板10和复合绝缘层一起形成本公开的台阶结构。台阶结构包括由柔性基板10的第一柔性层10A、第一阻挡层10B、非晶硅层10C、第二柔性层10D和第二阻挡层10E的第一子层形成的第一台阶51，由第二阻挡层10E的第二子层和第一绝缘层11形成的第二台阶52，以及由第二绝缘层13、第三绝缘层15、第四绝缘层16和第五绝缘层19形成的第三台阶53，第一台阶51、第二台阶52和第三台阶53的高度从切割内区420(显示基板边缘)到显示区域310(显示基板内部)的方向依次增大，即沿着第一台阶51到第三台阶53的方向，第一台阶51、第二台阶52和第三台阶53的高度依次增大。本公开中，台阶的高度是指台阶表面距离柔性基底下表面的距离。切割内区420的第一平坦层20覆盖上述台阶结构，且第一平坦层20远离显示区域310一侧的边缘与柔性基板10的边缘平齐。在边缘区域500中的周边区330，复合绝缘层设置有裂缝坝33，裂缝坝33包括在复合绝缘层中开设的多个间隔设置的裂缝，裂缝中的第二绝缘层13、第三绝缘层15、第四绝缘层16和第五绝缘层19被去掉，暴露出第一绝缘层11的表面。周边区330的第一平坦层20覆盖裂缝坝33，填充裂缝坝33中的多个间隔设置的裂缝，周边区330的第一平坦层20的表面与切割内区420的第一平坦层20的表面基本平齐。
下面通过显示基板的制备过程的示例说明本公开显示基板的结构。本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶等处理。沉积可以采用选自溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用选自喷涂和旋涂中的任意一种或多种，刻蚀可以采用选自干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。当在整个制作过程当中该“薄 膜”还需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。本公开中所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成。“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
由于本公开显示基板的制备过程是先制备显示母板，然后将显示母板切割成个显示基板，因此下述描述中，切割前的基板称之为显示母板，切割后的基板称之为显示基板。显示母板包括基板区域300和位于基板区域300外围的切割区域400。
(1)在玻璃载板1上制备柔性基底10。本公开中，柔性基底10包括在玻璃载板1上叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称之为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。在一示例性实施方式中，以叠层结构PI1/Barrier1/a-si/PI2/Barrier2为例，其制备过程可以包括：先在玻璃载板1上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层10A；随后在第一柔性层10A上沉积一层阻挡薄膜，形成覆盖第一柔性层10A的第一阻挡(Barrier1)层10B；然后在第一阻挡层10B上沉积一层非晶硅薄膜，形成覆盖第一阻挡层10B的非晶硅(a-si)层10C；然后在非晶硅层10C上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层10D；然后在第二柔性层10D上沉积一层阻挡薄膜，形成覆盖第二柔性层10D的第二阻挡(Barrier2)层10E，完成柔性基底10的制备，如图4所示。本次工艺后，基板区域300和切割区域400均包括柔性基底10。
在示例性实施方式中，第一柔性层10A、第一阻挡层10B、非晶硅层10C和第二柔性层10D的总厚度可以为15μm到20μm，第二阻挡层10E的厚度可以为0.4μm到0.7μm。在一些可能的实现方式中，第一柔性层10A、第一阻挡层10B、非晶硅层10C和第二柔性层10D的总厚度可以为17.6μm，第 二阻挡层10E的厚度可以为0.55μm。本公开中，厚度是指膜层上表面与下表面之间的距离。
(2)在柔性基底10上制备驱动结构层图案。基板区域300的驱动结构层包括构成像素驱动电路的第一晶体管101、第二晶体管102、第三晶体管103、第一存储电容104A、第一存储电容104B和低压线105，切割区域400的驱动结构层包括多个无机绝缘层构成的复合绝缘层，其上形成有暴露出柔性基底10的第二柔性层10D的凹槽。在一示例性实施方式中，驱动结构层的制备过程可以包括：
在柔性基底10上依次沉积第一绝缘薄膜和有源层薄膜，通过构图工艺对有源层薄膜进行构图，形成覆盖整个柔性基底10的第一绝缘层11，以及设置在第一绝缘层11上的有源层图案，有源层图案形成在基板区域300，至少包括第一有源层12A、第二有源层12B和第三有源层12C。本次构图工艺后，切割区域400包括设置在柔性基底10上的第一绝缘层11。
在示例性实施方式中，第一绝缘层11的厚度可以为0.2μm到0.6μm。在一些可能的实现方式中，第一绝缘层11的厚度可以为0.4μm。
随后，依次沉积第二绝缘薄膜和第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成覆盖有源层图案的第二绝缘层13，以及设置在第二绝缘层13上的第一栅金属层图案，第一栅金属层图案形成在基板区域300，至少包括第一栅电极14A、第二栅电极14B、第三栅电极14C、第一电容电极41A和第二电容电极41B、多条栅线(未示出)和多条栅引线(未示出)。本次构图工艺后，切割区域400包括在柔性基底10叠设的第一绝缘层11和第二绝缘层13。
随后，依次沉积第三绝缘薄膜和第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成覆盖第一栅金属层的第三绝缘层15，以及设置在第三绝缘层15上的第二栅金属层图案，第二栅金属层图案形成在基板区域300，至少包括第三电容电极42A、第四电容电极42B和第二栅引线(未示出)，第三电容电极42A的位置与第一电容电极41A的位置相对应，第四电容电极42B的位置与第二电容电极41B的位置相对应。本次构图工艺后，切割区域400包括在柔性基底10叠设的第一绝缘层11、第二绝缘层13和第三 绝缘层15。
随后，沉积第四绝缘薄膜，通过构图工艺对第四绝缘薄膜进行构图，形成覆盖第二栅金属层的第四绝缘层16图案，第四绝缘层16上开设有多个第一过孔，多个第一过孔形成在基板区域300，其位置分别与第一有源层12A、第二有源层12B和第三有源层12C的两端位置相对应，多个第一过孔内的第四绝缘层16、第三绝缘层15和第二绝缘层13被刻蚀掉，分别暴露出第一有源层12A、第二有源层12B和第三有源层12C的表面。本次构图工艺后，切割区域400包括在柔性基底10上叠设的第一绝缘层11、第二绝缘层13、第三绝缘层15和第四绝缘层16。
随后，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，在第四绝缘层16上形成源漏金属层图案，源漏金属层形成在基板区域300，至少包括第一源电极17A、第一漏电极18A、第二源电极17B、第二漏电极17B、第三源电极17C、第三漏电极17C、低压(VSS)线105、多条数据线(未示出)和多条数据引线图案，第一源电极17A和第一漏电极18A分别通过第一过孔与第一有源层12A连接，第二源电极17B和第二漏电极17B分别通过第一过孔与第二有源层12B连接，第三源电极17C和第三漏电极17C分别通过第一过孔与第三有源层12C连接。在一示例性实施方式中，根据实际需要，源漏金属层还可以包括电源线(VDD)、补偿线和辅助阴极中的任意一种或多种，源漏金属层也称之为第一源漏金属层(SD1)。本次构图工艺后，切割区域400包括在柔性基底10上叠设的第一绝缘层11、第二绝缘层13、第三绝缘层15和第四绝缘层16。
随后，沉积第五绝缘薄膜，形成覆盖源漏金属层的第五绝缘层19图案。本次构图工艺后，切割区域400包括设置在柔性基底10上的复合绝缘层，复合绝缘层包括叠设的第一绝缘层11、第二绝缘层13、第三绝缘层15、第四绝缘层16和第五绝缘层19。
至此，在柔性基底10上制备完成驱动结构层图案，如图5所示。第一有源层12A、第一栅电极14A、第一源电极17A和第一漏电极18A组成第一晶体管101，第二有源层12B、第二栅电极14B、第二源电极17B和第二漏电极18B组成第二晶体管102，第三有源层12C、第三栅电极14C、第三源电 极17C和第三漏电极18C组成第三晶体管103，第一电容电极41A和第三电容电极42A组成第一存储电容104A，第二电容电极42B和第四电容电极42B组成第二存储电容104B，多条栅引线和数据引线组成阵列基板栅极驱动(Gate Driver on Array，简称GOA)的驱动引线。在一示例性实施方式中，第一晶体管101可以是像素驱动电路中的驱动晶体管，第二晶体管102可以是GOA中输出扫描(SCAN)信号的扫描晶体管，第三晶体管103可以是GOA中输出使能(EM)信号的使能晶体管，驱动晶体管、扫描晶体管和使能晶体管均可以是薄膜晶体管(Thin Film Transistor，简称TFT)。
(3)通过构图工艺对切割区域400、邻近切割区域400的基板区域300的复合绝缘层进行构图，在切割区域400形成第一凹槽31和第二凹槽32，在基板区域300形成裂缝坝33，如图6所示。本公开中，基板区域300可以划分为显示区域310、外围电路区320和周边区330，周边区330邻近切割区域400，显示区域310位于周边区330远离切割区域400的一侧，外围电路区320位于显示区域310与周边区330之间。切割区域400可以划分为切割道区410、切割内区420和切割外区430，切割道区410位于切割区域400的中部，是切割显示母板时形成切口的区域，切割内区420位于切割道区410邻近基板区域300的一侧，切割外区430位于切割道区410远离基板区域300的一侧。在切割显示母板形成显示基板后，切割道区410和切割外区430被切割掉，切割内区420被保留。这样，对于制备完成的显示基板，基板区域300的周边区330和切割区域400的切割内区420组成显示基板的边缘区域500，如图6所示。
本公开中，在切割区域400形成的第一凹槽31和第二凹槽32后，第一凹槽31暴露出柔性基底10的第二阻挡层10E，第二凹槽32暴露出第一凹槽31，即第一凹槽31在柔性基底10上的正投影包含第二凹槽32在柔性基底10上的正投影。后续描述中，第一凹槽31和第二凹槽32称之为凹槽。裂缝坝33形成在基板区域300的周边区330，即形成在边缘区域500，裂缝坝33包括多个间隔设置的裂缝，每个裂缝暴露出第一绝缘层11的表面，如图6所示。本次构图工艺后，切割区域400包括设置在柔性基底10上具有凹槽的复合绝缘层，凹槽中第一凹槽31和第二凹槽32的宽度均大于切割道区410 的宽度。
在示例性实施方式中，可以采用两次构图工艺形成第一凹槽31、第二凹槽32和裂缝坝33。通过第一次掩膜(Etch Bending A MASK，简称EBA MASK)刻蚀切割区域400和周边区330的第五绝缘层19、第四绝缘层16、第三绝缘层15和第二绝缘层13，在切割区域400的第二绝缘层13、第三绝缘层15和、第四绝缘层16和第五绝缘层19上形成第二凹槽32，在周边区330的第二绝缘层13、第三绝缘层15、第四绝缘层16和第五绝缘层19上形成裂缝坝33，第二凹槽32和裂缝坝33内的第五绝缘层19、第四绝缘层16、第三绝缘层15和第二绝缘层13被刻蚀掉，暴露出第一绝缘层11的表面。然后通过第二次掩膜(Etch Bending B MASK，简称EBB MASK)刻蚀切割区域400中第二凹槽32内的第一绝缘层11和柔性基底10的第二阻挡层10E的第二子层，在第二阻挡层10E的第二子层和第一绝缘层11上形成第一凹槽31，第一凹槽31内的第一绝缘层11和第二阻挡层10E的第二子层被刻蚀掉，暴露出柔性基底10的第二阻挡层10E的第一子层的表面。这样，在切割区域400，第二凹槽32暴露出第一凹槽31，即暴露出第一绝缘层11和柔性基底的第二阻挡层10E的第一子层，第一凹槽31暴露出柔性基底10的第二阻挡层10E的第一子层，形成台阶状的凹槽结构。在示例性实施方式中，第二阻挡层10E可以理解为由叠设的第一子层和第二子层组成，第一子层设置在第二柔性层10D上，第二子层设置在第一子层上，第一绝缘层11设置在第二子层上。在EBB MASK过程中，第二凹槽32内的第二子层被刻蚀掉，第一子层被保留，即所形成的第一凹槽31是开设在第一绝缘层11和部分厚度的第二阻挡层10E上。在一些可能的实现方式中，第一子层称为第二阻挡层10E的残留部分，第二子层称为第二阻挡层10E的被刻蚀掉部分。在周边区330，多个间隔设置的裂缝暴露出第一绝缘层11的表面，形成凹凸状的裂缝坝结构。EBA MASK和EBB MASK工艺是对显示母板的弯折区进行挖槽的构图工艺，以减少弯折区的厚度。本公开中，在周边区330形成凹凸状的裂缝坝结构，是用于避免在显示母板切割过程中影响显示区域310和外围电路区320的膜层结构，多个间隔设置的裂缝不仅能够减小显示区域310和外围电路区320的受力，而且能够截断裂纹向显示区域310和外围电路区320方向传递。
在示例性实施方式中，采用EBA MASK和EBB MASK工艺形成第一凹槽31和第二凹槽32过程中，可以通过设置工艺参数使第一凹槽31和第二凹槽32的内侧壁为坡面，坡面的母线与显示基板的法线方向的夹角θ为20°到50°。在示例性实施方式中，第一凹槽31的深度h1小于第二凹槽32的深度h2。在一些可能的实现方式中，第一凹槽31的深度h1(即第二台阶的厚度)可以为0.2μm到1.3μm，第二凹槽32的深度h2(即第三台阶的厚度)可以为0.5μm到1.4μm。
(4)在形成前述图案的柔性基底上涂覆第一平坦薄膜，形成覆盖整个柔性基底10的第一平坦化(PLN)层20，通过构图工艺在第一平坦层20上形成第二过孔、第三过孔和隔断，第二过孔内形成在显示区域310，第二过孔内的第一平坦层20和第五绝缘层19被刻蚀掉，暴露出第一晶体管101的第一漏电极的表面，第三过孔和隔断形成在外围电路区320，第三过孔内的第一平坦层20和第五绝缘层19被刻蚀掉，暴露出低压线105的表面，隔断内的第一平坦层20被显影掉，暴露出第五绝缘层19的表面。在基板区域300的周边区330，第一平坦层20完全填充裂缝坝33中的裂缝。在切割区域400，第一平坦层20完全填充第一凹槽31和第二凹槽32，具有较平坦的表面，即切割区域400的第一平坦层20远离柔性基底10一侧的表面较为平齐状，如图7所示。在示例性实施方式中，第一平坦层20的厚度可以为0.8μm到1.5μm。本次构图工艺后，切割区域400包括设置在柔性基底10上具有凹槽的复合绝缘层和设置在复合绝缘层并填充凹槽的第一平坦层20。本公开中，在基板区域300形成隔断是用于后续封装时，使封装层中的无机层直接接触第五绝缘层19第四绝缘层16，保证封装效果和工艺质量。
(5)在形成前述图案的柔性基底上沉积第四金属薄膜，通过构图工艺对第四金属薄膜进行构图，在第一平坦层20上形成金属导电层图案，金属导电层至少包括第一连接电极106和第二连接电极107，第一连接电极106设置在显示区域310，通过第二过孔与第一晶体管101的第一漏电极连接，第二连接电极107设置在外围电路区320，通过第三过孔与低压线105连接，并向周边区330方向延伸，覆盖第三过孔与隔断之间的第一平坦层20，如图8所示。在一示例性实施方式中，金属导电层也称之为第二源漏金属层 (SD2)，根据实际设计，金属导电层还可以包括电源线、电源引线、低压引线和辅助阴极中的任意一种或多种，切割区域400也可以设置金属导电层，如实现测试的信号线等。本次构图工艺中，由于切割区域400的凹槽被第一平坦层20填充，第四金属薄膜是形成在平坦的第一平坦层20表面上，消除了切割区域400中第四金属薄膜各个位置的高度差，因而避免了金属薄膜刻蚀不完全的情形，构图工艺后不会有金属块残留。
(6)在形成前述图案的柔性基底上涂覆第二平坦薄膜，通过掩膜、曝光、显影工艺，在第一平坦层20上形成第二平坦层21图案。在显示区域310，第二平坦层21上开设有第四过孔，第四过孔内的第二平坦层21被显影掉，暴露出第一连接电极106的表面，在外围电路区320，第二平坦层21上开设有第五过孔和缝隙34，第五过孔内的第二平坦层21靠近过孔侧壁部分的第二平坦层21被显影掉，暴露出第二连接电极107的表面，缝隙34设置在第四过孔与第五过孔之间，缝隙34内的第一平坦层20和第二平坦层21被显影掉，暴露出第五绝缘层19的表面。裂缝坝33所在区域以及隔断所在区域的第二平坦层21被显影掉，暴露出第一平坦层20和隔断。在切割区域400，切割内区420的部分位置和切割外区430的部分位置设置有第二平坦层21，其它位置的第二平坦层21被显影掉，暴露出第一平坦层20的表面，如图9所示。在示例性实施方式中，第二平坦层21的厚度可以为0.8μm到1.5μm。有关切割区域400中第二平坦层21的位置，后面详细说明。在缝隙34所在区域，第二平坦层21的开口在柔性基底10上的正投影包含第一平坦层20的开口，即第二平坦层21的开口宽度大于第一平坦层20的开口宽度，第一平坦层20的开口暴露出第五绝缘层19，第二平坦层21的开口暴露出第一平坦层20的开口，在缝隙34的侧壁上形成阶梯状，使后续形成的阴极也具有阶梯状，以保证阴极与第三连接电极的可靠连接。本次构图工艺后，切割区域400包括设置在柔性基底10上具有凹槽的复合绝缘层以及设置在复合绝缘层并填充凹槽的第一平坦层20。本公开中，在外围电路区320形成缝隙34是用于排放在工艺过程中平坦化(PLN)膜层产生的气体，提高工艺质量。
(7)在形成前述图案的基底上沉积透明导电薄膜，通过构图工艺对透明 导电薄膜进行构图，形成阳极23和第三连接电极108图案，阳极23形成在显示区域310的第二平坦层21上，通过第四过孔与第一连接电极106连接，第三连接电极108形成在外围电路区320的第二平坦层21上，第三连接电极108的一部分通过第五过孔与第二连接电极107连接，另一部分设置在缝隙34中，第五过孔与缝隙34之间的第三连接电极108上开设有多个第六过孔，如图10所示。由于缝隙34的侧壁为阶梯状，因此设置在缝隙34中的第三连接电极108也为阶梯状。本次构图工艺后，切割区域400和周边区330(裂缝坝33所在区域)的膜层结构没有变化。
(8)在形成前述图案的基底上涂覆像素定义薄膜，通过掩膜、曝光、显影工艺，在基板区域300形成像素定义(PDL)层24、第一坝基201和第二坝基202图案，像素定义层24形成在显示区域310，其上开设有像素开口，像素开口内的像素定义薄膜被显影掉，暴露出阳极23的表面。第一坝基201和第二坝基202形成在外围电路区320，第一坝基201设置在第五过孔内的第三连接电极108上，第二坝基202设置在第五过孔与隔断之间的第二平坦层21上，第一坝基201和第二坝基202的截面形状为梯形，如图11所示。本公开中，第一坝基201和第二坝基202是用于形成两个支撑坝(dam)。本次构图工艺后，切割区域400和周边区330(裂缝坝33所在区域)的膜层结构没有变化。
(9)在形成前述图案的基底上涂覆有机材料薄膜，通过掩膜、曝光、显影工艺，在外围电路区320形成多个隔离柱(PS)203图案，多个隔离柱203分别设置在第一坝基201、第二坝基202以及缝隙34两侧的位置，多个隔离柱203的截面形状为梯形，第一坝基201与其上的隔离柱203形成第一支撑坝，第二坝基202与其上的隔离柱203形成第二支撑坝，如图12所示。本次构图工艺后，切割区域400和周边区330(裂缝坝33所在区域)的膜层结构没有变化。
(10)在形成前述图案的基底上依次形成有机发光层25和阴极26，如图13所示。有机发光层25包括叠设的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层，形成在基板区域300的像素开口内，实现有机发光层25与阳极23连接。由于阳极23与第一连接电极106连接，第一连接电 极106与第一晶体管101的漏电极连接，因而实现了有机发光层25的发光控制。阴极26的一部分形成在有机发光层25上，阴极26与有机发光层25连接，阴极26的另一部分形成在像素开口与第五过孔之间的区域，阴极26通过缝隙34和第五过孔与第三连接电极108连接。由于第三连接电极108与第二连接电极107连接，第二连接电极107与低压线105连接，因而实现了阴极26与低压线105的连接。由于缝隙34位置的第三连接电极108为阶梯状，因此所形成的阴极26也具有阶梯状，在不同的台阶上与第三连接电极108接触，保证了阴极与第三连接电极108的可靠连接。本次构图工艺后，切割区域400和周边区330(裂缝坝33所在区域)的膜层结构没有变化。
(11)在形成前述图案的基础上形成封装层27，封装层27形成在基板区域300的显示区域310和外围电路区域320，采用无机材料/有机材料/无机材料的叠层结构，两个无机材料层设置在显示区域310和外围电路区域320，包裹第一支撑坝和第二支撑坝，有机材料层设置在两个无机材料层之间，位于第一支撑坝远离周边区330的一侧，如图14所示。本公开中，由于第一平坦层20形成有暴露出第五绝缘层19的表面的隔断，因而两个无机材料层直接形成在隔断内的第五绝缘层19上，保证封装效果和工艺质量。本次构图工艺后，切割区域400和周边区330(裂缝坝33所在区域)的膜层结构没有变化。
(12)在制备完成上述膜层结构后，先通过剥离工艺将显示母板从玻璃载板1上剥离，然后采用滚轮贴合方式在显示母板背面(柔性基底10远离膜层的一侧表面)贴附一层背膜2，完成显示母板的制备，如图15所示。
(13)切割设备沿着切割区域400的切割道区410进行切割，切割条L将显示母板分隔成本公开的显示基板，如图16所示。切割完成后，切割区域400的切割道区410和切割外区430被切割掉，切割内区420保留下来，基板区域300的周边区330和切割区域400的切割内区420组成本公开显示基板的边缘区域500，如图3所示。
结合图3到图16，本公开显示基板的边缘区域500包括柔性基板10和设置在柔性基板10上的复合绝缘层，复合绝缘层由多个无机绝缘层组成，包括在柔性基板10上叠设的第一绝缘层11、第二绝缘层13、第三绝缘层15 第四绝缘层16和第五绝缘层19。在边缘区域500中的切割内区420，柔性基板10和复合绝缘层形成台阶结构，台阶结构包括由柔性基板10的第一柔性层10A、第一阻挡层10B、非晶硅层10C、第二柔性层10D和第二阻挡层10E的第一子层形成的第一台阶51，由第二阻挡层10E的第二子层和第一绝缘层11形成的第二台阶52，以及由第二绝缘层13、第三绝缘层15、第四绝缘层16和第五绝缘层19形成的第三台阶53，第一台阶51、第二台阶52和第三台阶53的高度从切割内区420到周边区330的方向依次增大，即从第一台阶51到第三台阶53的方向依次增大。切割内区420还包括第一平坦层20和设置在第一平坦层20上的第二平坦层21，第一平坦层20覆盖上述台阶结构，第一平坦层20的外边缘(远离周边区330一侧的端面)与柔性基板10的外边缘基本平齐，第二平坦层21设置在第一台阶51和第二台阶52的交界区域。在边缘区域500中的周边区330，复合绝缘层形成有裂缝坝33和覆盖裂缝坝33的第一平坦层20，裂缝坝33包括设置在复合绝缘层中的多个间隔设置的裂缝，裂缝中的第二绝缘层13、第三绝缘层15、第四绝缘层16和第五绝缘层19被去掉，暴露出第一绝缘层11的表面。周边区330的第一平坦层20覆盖裂缝坝33，填充裂缝坝33中的多个间隔设置的裂缝。周边区330的第一平坦层20的表面与切割内区420的第一平坦层20的表面基本平齐。
图17为本公开显示基板边缘区域的结构示意图。如图17所示，本公开边缘区域的台阶结构中，第二台阶52和第三台阶53的侧壁为坡面，坡面的母线与显示基板的法线方向的夹角θ为20°到50°。
在示例性实施方式中，第一台阶51的厚度h0大于第三台阶53的厚度h2，第一台阶51的厚度h0大于第二台阶52的厚度h1。在一些可能的实现方式中，第三台阶53的厚度h2可以大于第二台阶52的厚度h1。本公开中，台阶的厚度是指台阶的上表面与台阶的下表面之间的距离。
在示例性实施方式中，第一台阶51的厚度h0可以为15μm到20.7μm，第二台阶52的厚度h1可以为0.2μm到1.3μm，第三台阶53的厚度h2可以为0.5μm到1.4μm。在一些可能的实现方式中，第一台阶51的厚度h0可以为17.654μm，第二台阶52的厚度h1可以为0.76μm，第三台阶53的厚度h2可以为0.80μm。
在示例性实施方式中，第一子层的厚度可以为0.05μm到0.06μm，第二子层的厚度可以为0.44μm到0.55μm，即厚度为0.4μm到0.7μm的第二阻挡层10E中，被刻蚀掉的厚度可以为0.44μm到0.55μm，残留的厚度可以为0.05μm到0.06μm。在一些可能的实现方式中，第二阻挡层10E的厚度可以为0.55μm，第一子层的厚度可以为0.054μm，第二子层的厚度可以为0.496μm。
在示例性实施方式中，以第一子层邻近第二柔性层一侧的表面(第二阻挡层邻近第二柔性层一侧的表面，或者第二柔性层邻近第二阻挡层一侧的表面)为参考面，第一台阶51的上表面与参考面之间的距离可以为0.05μm到0.06μm，第二台阶52的上表面与参考面之间的距离可以为0.75μm到0.95μm，第三台阶53的上表面与参考面之间的距离可以为1.40μm到1.80μm。在一些可能的实现方式中，第一台阶51的上表面与参考面之间的距离可以为0.054μm，第二台阶52的上表面与参考面之间的距离可以为0.812μm，第三台阶53的上表面与参考面之间的距离可以为1.614μm。
在示例性实施方式中，第一台阶51的边缘到第二台阶52的边缘的距离为s1，s1称为第一台阶51的宽度，第二台阶52的边缘到第三台阶53的边缘的距离为s2，s2称为第二台阶52的宽度，第三台阶53的边缘到裂缝坝的边缘的距离为s3，s3称为第三台阶53的宽度。第一台阶51的宽度s1大于第二台阶52的宽度s2，第一台阶51的宽度s1大于第三台阶53的宽度s3。
在示例性实施方式中，第一台阶51的宽度s1可以为55μm到210μm，第二台阶52的宽度s2可以为5μm到40μm，第三台阶53的宽度s3可以为5μm到15μm，第二台阶52的宽度s2可以大于或等于第三台阶53的宽度s3。在一些可能的实现方式中，第一台阶51的宽度s1可以为105μm。在另一些可能的实现方式中，第一台阶51的宽度s1可以为160μm。在一些可能的实现方式中，第二台阶52的宽度s2可以为35μm，第三台阶53的宽度s3可以为6μm。在一些可能的实现方式中，第二台阶52的宽度s2可以为10μm，第三台阶53的宽度s3可以为10μm。
在示例性实施方式中，边缘区域500的第二平坦层21在柔性基底10上的正投影与第一台阶51和第二台阶52在柔性基底10上的正投影部分重叠， 即第二平坦层21在柔性基底10上的正投影与部分第二台阶52在柔性基底10上的正投影重叠，与部分第一台阶51在柔性基底10上的正投影重叠。边缘区域500的第二平坦层21远离显示区域的边缘到第二台阶52的边缘的距离为s4，s4称为第二平坦层21覆盖第一台阶51的宽度，即第二平坦层21在柔性基底10上的正投影与第一台阶51在柔性基底10上的正投影重叠的宽度。边缘区域500的第二平坦层21邻近显示区域的边缘到第二台阶52的边缘的距离为s5，s5称为第二平坦层21覆盖第二台阶52的宽度，即第二平坦层21在柔性基底10上的正投影与第二台阶52在柔性基底10上的正投影重叠的宽度。在示例性实施方式中，第二平坦层21覆盖第一台阶51的宽度s4可以为10μm到20μm，第二平坦层21覆盖第二台阶52的宽度s5可以为20μm到30μm。在一些可能的实现方式中，第二平坦层21覆盖第一台阶51的宽度s4可以为15μm，第二平坦层21覆盖第二台阶52的宽度s5可以为25μm。在示例性实施方式中，沿着远离显示区域的方向，边缘区域500的第二平坦层21的宽度s6可以为30μm到50μm。在一些可能的实现方式中，边缘区域500的第二平坦层21的宽度s6可以为40μm。本公开示例性实施例中，通过将第二平坦层21设置在第一台阶51与第二台阶52的交界区域，第二平坦层21覆盖第二台阶52的坡面侧壁所在区域，在后续形成阳极23和第三连接电极108图案的构图工艺中，可以避免透明导电薄膜的刻蚀残留，提高工艺质量。
在一种示例性实施方式中，基板区域还可以包括设置在封装层上的触控层或触控面板以及覆盖触控层或触控面板的保护层(OC)。在另一种示例性实施方式中，显示基板区域还可以包括保护膜(Temporary Protect Film，简称TPF)，保护膜贴设在封装层上，保护膜用于保护显示基板的膜层结构，贴附背膜操作是在贴附保护膜后进行。完成切割后，先去除该保护膜，然后在封装层上依次设置触控层和盖板，形成触控显示面板；或者在封装层上直接设置盖板，形成显示面板。
本公开中，第一绝缘薄膜、第二绝缘薄膜、第三绝缘薄膜、第四绝缘薄膜和第五绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘 层称之为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称之为栅绝缘(GI)层，第四绝缘层称之为层间绝缘(ILD)层，第五绝缘层称之为钝化(PVX)层。第一平坦层和第二平坦层可以采用有机材料。第一金属薄膜、第二金属薄膜、第三金属薄膜和第四金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。阴极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或更多种，或采用上述金属中任意一种或多种制成的合金。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等各种材料，即本公开适用于基于氧化物Oxide技术、硅技术以及有机物技术制造的晶体管。透明导电薄膜可以采用氧化铟锡ITO或氧化铟锌IZO，像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等。
如图3～图16所示，本公开所提供的显示基板包括：
柔性基底10，柔性基底10包括依次叠设的第一柔性层10A、第一阻挡层10B、非晶硅(a-si)层10C、第二柔性层10D和第二阻挡层10E；
设置在柔性基底10上的第一绝缘层11；
设置在第一绝缘层11上的有源层图案，有源层图案设置在显示区域310，有源层图案至少包括第一有源层12A、第二有源层12B和第三有源层12C；
覆盖有源层的第二绝缘层13；
设置在第二绝缘层13上的第一栅金属层，第一栅金属层设置在显示区域310和外围电路区320，第一栅金属层至少包括显示区域310的第一栅电极14A以及外围电路区320的第二栅电极14B、第三栅电极14C、第一电容电极41A和第二电容电极41B；
覆盖第一栅金属层的第三绝缘层15；
设置在第三绝缘层15上的第二栅金属层，第二栅金属层设置在外围电 路区320，第二栅金属层至少包括第三电容电极42A和第四电容电极42B；
覆盖第二栅金属层的第四绝缘层16，显示区域310和外围电路区320的第四绝缘层16上开设有多个第一过孔，多个第一过孔分别暴露出第一有源层12A、第二有源层12B和第三有源层12C；
设置在第四绝缘层16上的源漏金属层，源漏金属层设置在显示区域310和外围电路区320，源漏金属层至少包括显示区域310的第一源电极17A和第一漏电极18A，以及外围电路区320的第二源电极17B、第二漏电极18B、第三源电极17C、第三漏电极18C和低压线105，第一源电极17A和第一漏电极18A分别通过第一过孔与第一有源层12A连接，第二源电极17B和第二漏电极18B分别通过第一过孔与第二有源层12B连接，第三源电极17C和第三漏电极18C分别通过第一过孔与第三有源层12C连接；
覆盖源漏金属层的第五绝缘层19，第五绝缘层19设置在显示区域310和部分外围电路区320；周边区330形成的复合绝缘层设置有裂缝坝33，裂缝坝33包括多个间隔设置的裂缝，裂缝暴露出第一绝缘层11；切割区域400形成的复合绝缘层设置有凹槽，凹槽暴露出柔性基底10的第二阻挡层10E的第一子层，凹槽包括第一凹槽31和第二凹槽32，第一凹槽31设置在第二阻挡层10E的第二子层和第一绝缘层11上，暴露出柔性基底10的第二阻挡层10E的第一子层，第二凹槽32设置在第二绝缘层13、第三绝缘层15、第四绝缘层16和第五绝缘层19上，暴露出第一凹槽31；
覆盖前述结构的第一平坦层20；在显示区域310，第一平坦层20上开设有第二过孔，在外围电路区320，第一平坦层20上开设有第三过孔和隔断，第二过孔暴露出第一漏电极18A，第三过孔暴露出低压线105，隔断暴露出第五绝缘层19；在周边区330，第一平坦层20完全填充裂缝坝33，在切割区域400，第一平坦层20完全填充凹槽；
设置在第一平坦层20上的金属导电层，金属导电层至少包括显示区域310的第一连接电极106和外围电路区320的第二连接电极107，第一连接电极106通过第二过孔与第一漏电极18A连接，第二连接电极107通过第三过孔与低压线105连接；
覆盖金属导电层的第二平坦层21；在显示区域310，第二平坦层21设置有第四过孔，在外围电路区320，第二平坦层21设置有第五过孔和缝隙34，第四过孔暴露出第一连接电极106，第五过孔暴露出第二连接电极107，缝隙34暴露出第五绝缘层19；
设置在第二平坦层23上的阳极23和第三连接电极108，阳极23形成在显示区域310，第三连接电极108形成在外围电路区320，阳极23通过第四过孔与第一连接电极106连接，第三连接电极108通过第五过孔与第二连接电极107连接；
设置在显示区域310的像素定义层24以及外围电路区320的第一坝基201和第二坝基202，像素定义层24上开设有像素开口，像素开口暴露出阳极23，第一坝基201设置在第五过孔内的第三连接电极108上，第二坝基202设置在第一坝基201邻近切割区域400的一侧；
设置在外围电路区320的多个隔离柱203；
设置在显示区域310的有机发光层25，有机发光层25与阳极23连接；
设置在显示区域310和外围电路区320的阴极26，阴极26与分别与有机发光层25和第三连接电极108连接；
设置在显示区域310和外围电路区320的封装层27。
图18为本公开绑定区域的结构示意图。如图18所示，在平行于显示基板的平面内，绑定区域302位于显示区域310的一侧，绑定区域302包括第一扇出区303、弯折区304、第二扇出区305、防静电区306、驱动芯片区307和绑定针区308，弯折区304的复合绝缘层采用EBA MASK和EBB MASK工艺去除，以减少弯折区的厚度。本公开中，前述形成第一凹槽和第二凹槽的工艺与弯折区304去除复合绝缘层的工艺是同步进行的。在制备显示母板过程中，绑定区域302远离显示区域310一侧，还设置有阵列测试(Array Test)单元600，阵列测试单元600通过信号线与绑定针区308连接，被配置为对显示基板进行测试，以检查是否有短路、断路等问题。绑定区域302的外侧设置有第一切割线701和第二切割线702，第二切割线702为精切割线，位于绑定区域302的外围，第二切割线702的形状与绑定区域302的 轮廓相同，第一切割线701为粗切割线，位于第二切割线702的外围，第一切割线701的形状与第二切割线702的的轮廓相同，但绑定区域302与阵列测试单元600之间仅设置第二切割线702。在阵列测试单元600远离绑定区域302的一侧，还设置有至少一条第一切割线701。在完成显示母板的膜层工艺后，切割设备沿着第一切割线701(粗切割线)切割显示母板，形成多个基板区域，在完成显示基板测试后，切割设备沿着第二切割线702(精切割线)切割基板区域，形成显示基板。
图19为图18中B-B向的剖视图。在垂直于显示基板的平面内，绑定区域302包括：设置在柔性基底10上的第一绝缘层11，设置在第一绝缘层11上的第二绝缘层13，设置在第二绝缘层13上的第三绝缘层15，设置在第三绝缘层15上的第四绝缘层16，设置在第四绝缘层16上的多个第一引线，覆盖多个第一引线的第五绝缘层19和第一平坦层20，设置在第一平坦层20上的多个第二引线(未示出)，覆盖多个第二引线的第二平坦层21。多个第一引线与前述的源漏金属层同层设置，且通过同一次构图工艺同时形成，多个第二引线与前述的金属导电层同层设置，且通过同一次构图工艺同时形成。在一些可能的实现方式中，绑定区域302还可以包括与前述第一栅金属层同层设置的引线，或者可以包括与前述第二栅金属层同层设置的引线。位于绑定区域之外的切割区域，包括设置在柔性基底10上的复合绝缘层和第一平坦层20，复合绝缘层设置有台阶结构的凹槽，第一平坦层20填充该凹槽。
图19示意了凹槽的结构，凹槽的右侧为边缘区域的台阶结构，凹槽的左侧为切割外区430的台阶结构，切割外区430称之为虚拟(Dummy)区，凹槽中间部分的双虚线表示切割线。边缘区域的台阶结构特点及其相应几何参数已在图17中详细说明，这里不再赘述。如图19所示，虚拟区的台阶结构中，虚拟区的第二台阶52′和虚拟区的第三台阶53′的侧壁为坡面，坡面的母线与显示基板的法线方向的夹角θ为20°到50°。
在示例性实施方式中，虚拟区的第一台阶51′的厚度h0大于虚拟区的第三台阶53′的厚度h2，虚拟区的第一台阶51′的厚度h0大于虚拟区的第二台阶52′的厚度h1。在一些可能的实现方式中，虚拟区的第三台阶53′的厚度h2可以大于虚拟区的第二台阶52′的厚度h1。
在示例性实施方式中，虚拟区的第一台阶51′的厚度h0可以为15μm到20.7μm，虚拟区的第二台阶52′的厚度h1可以为0.2μm到1.3μm，虚拟区的第三台阶53′的厚度h2可以为0.5μm到1.4μm。在一些可能的实现方式中，虚拟区的第一台阶51′的厚度h0可以为17.654μm，虚拟区的第二台阶52′的厚度h1可以为0.76μm，虚拟区的第三台阶53′的厚度h2可以为0.80μm。
在示例性实施方式中，虚拟区的第一台阶51′的边缘到虚拟区的第二台阶52′的边缘的距离为s1′，s1′称为虚拟区的第一台阶51′的宽度，虚拟区的第二台阶52′的边缘到虚拟区的第三台阶53′的边缘的距离为s2′，s2′称为虚拟区的第二台阶52′的宽度，虚拟区的第一台阶51′的宽度s1′大于虚拟区的第二台阶52的宽度s2′。
在示例性实施方式中，虚拟区的第一台阶51′的宽度s1′为55μm到155μm，虚拟区的第二台阶52′的宽度s2′为5μm到15μm。在一些可能的实现方式中，虚拟区的第一台阶51′的宽度s1′为105μm。在一些可能的实现方式中，虚拟区的第二台阶52′的宽度s2′为10μm。
在示例性实施方式中，虚拟区的第二平坦层21在柔性基底10上的正投影包含虚拟区的第二台阶52′和第三台阶53′在柔性基底10上的正投影，包含部分虚拟区的第一台阶51′在柔性基底10上的正投影。虚拟区的第二平坦层21邻近显示区域的边缘到虚拟区的第二台阶52′的边缘的距离为s4′，s4′称为第二平坦层21覆盖虚拟区的第一台阶51′的宽度。在示例性实施方式中，第二平坦层21覆盖虚拟区的第一台阶51′的宽度s4′为10μm到20μm。在一些可能的实现方式中，第二平坦层21覆盖虚拟区的第一台阶51′的宽度s4′为15μm。
图20为图18中C-C向的剖视图。如图18和图20所示，沿着远离显示区域310的方向，绑定区域302包括绑定电路区域311和绑定切割区域312，第一扇出区303、弯折区304、第二扇出区305、防静电区306、驱动芯片区307和绑定针区308设置在绑定电路区域311，绑定区域302与阵列测试单元600之间的第二切割线702设置在绑定切割区域312。在形成第一平坦层20和第二平坦层21时，绑定切割区域312以及阵列测试单元600所在区域的第一平坦层20和第二平坦层21被去掉，即沿着远离显示区域310的方向，第 一平坦层20和第二平坦层21延伸到绑定电路区域311与绑定切割区域312的边界。由于绑定区域302与阵列测试单元600之间设置有多条信号线，因此绑定切割区域312的复合绝缘层没有开设第一凹槽和第二凹槽。在完成显示基板测试后，切割设备沿着第二切割线702切割基板区域后，绑定区域302远离显示区域一侧的边缘区域形成阶梯结构，阶梯结构包括第一阶梯和第二阶梯，第一阶梯由柔性基底和复合绝缘层组成，柔性基底和复合绝缘层远离显示区域一侧的端面平齐，第二阶梯由第一平坦层和第二平坦层组成，第一平坦层和第二平坦层远离显示区域一侧的端面基本平齐。这样，绑定区域302远离显示区域310一侧的边缘区域形成有阶梯结构，除了绑定区域302远离显示区域310一侧的边缘区域，显示区域和绑定区域的其它边缘区域中均形成有台阶结构。
通过本公开显示基板的结构和制备流程可以看出，本公开所提供的显示基板，通过设置第一平坦层完全填充切割区域的凹槽，避免了金属导电层构图工艺中出现金属块残留，在后续工艺中既不会出现Ag粒子和颗粒，也不会出现Ag粒子和颗粒随处附着的情形，有效避免了显示基板出现暗点不良，提高了显示品质。
一种显示基板的结构中，为了减少后续切割工艺的切割厚度和难度，切割区域的复合绝缘层和第一平坦层上开设有暴露出基底的凹槽。由于凹槽的总深度为第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层和第一平坦层的厚度之和，不仅使得所沉积的金属薄膜各个位置的高度不一样，而且金属薄膜具有较大的高度差，导致构图工艺中金属薄膜刻蚀不完全，构图工艺后凹槽底面和台阶面上残留有金属块。此外，由于凹槽使得所沉积的金属薄膜直接与柔性基底接触，金属与有机材料发生化学反应并产生颗粒，因而存在颗粒污染设备的问题。本公开中，虽然切割区域的复合绝缘层上也开设有凹槽，但本公开的第一平坦层被设置成完全填充复合绝缘层的凹槽，利用第一平坦层消除了凹槽区域的高度差。后续沉积金属薄膜时，由于切割区域具有平坦的表面的，所沉积的金属薄膜在各个位置的高度相近，因此避免了在金属薄膜构图工艺中出现金属块残留，后续工艺中既不会出现Ag粒子，也不会出现Ag粒子随处附着的情形。此外，由于凹槽被第一平坦 层填充，后续沉积的金属薄膜没有与柔性基底直接接触，既避免了金属与有机材料发生化学反应产生颗粒，又保护了柔性基底不被金属腐蚀。本公开的制备工艺利用现有成熟的制备设备即可实现，对现有工艺改进较小，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。总之，本公开有效避免了因金属块残留和颗粒污染造成的暗点不良，保证了产品良率，提高了产品品质。
本公开显示基板的结构及其制备过程仅仅是一种示例性说明。在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，OLED可以是顶发射结构，或者可以是底发射结构。又如，驱动晶体管可以是顶栅结构，或者可以是底栅结构，可以是单栅结构，或者可以是双栅结构。再如，驱动结构层中还可以设置其它电极、引线和结构膜层，本公开在此不做具体的限定。
本公开还提供了一种显示母板，显示母板包括基板区域300和位于基板区域300外围的切割区域400。如图4到图16所示，所述显示母板包括：设置在所述基板区域和切割区域的驱动结构层，设置在所述驱动结构层上的第一平坦层；所述切割区域的驱动结构层包括复合绝缘层，所述复合绝缘层设置有凹槽，所述第一平坦层填充所述凹槽。
在示例性实施方式中，所述复合绝缘层包括多个叠设的无机绝缘层，所述凹槽暴露出所述柔性基底。
在示例性实施方式中，所述基板区域的驱动结构层包括：设置在柔性基底上的第一绝缘层，设置在所述第一绝缘层上的有源层，覆盖所述有源层的第二绝缘层，设置在所述第二绝缘层上的第一栅金属层，覆盖所述第一栅金属层的第三绝缘层，设置在所述第三绝缘层上的第二栅金属层，覆盖所述第二栅金属层的第四绝缘层，设置在所述第四绝缘层上的源漏金属层，覆盖所述源漏金属层的第五绝缘层。
在示例性实施方式中，所述切割区域的驱动结构层包括：在柔性基底上叠设的第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层；所述柔性基底包括叠设的第一柔性层、第一阻挡层、非晶硅层、第二柔性层和第二阻挡层，所述第一绝缘层设置在所述第二阻挡层上，所述凹槽暴露出 所述柔性基底的第二阻挡层。
在示例性实施方式中，所述第一柔性层、第一阻挡层、非晶硅层和第二柔性层的总厚度可以为15μm到20μm，所述第二阻挡层的厚度可以为0.4μm到0.7μm，所述第一绝缘层的厚度可以为0.2μm到0.6μm。
在示例性实施方式中，所述第二阻挡层包括在所述第二柔性层上叠设的第一子层和第二子层；所述凹槽包括第一凹槽和第二凹槽，所述第一凹槽设置在所述第一绝缘层和第二阻挡层的第二子层上，所述第一凹槽暴露出所述柔性基底的第二阻挡层的第一子层，所述第二凹槽设置在所述第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层上，所述第二凹槽暴露出所述第一绝缘层和所述柔性基底的第二阻挡层的第一子层，所述第二凹槽在柔性基底上的正投影包含所述第一凹槽在柔性基底上的正投影。
在示例性实施方式中，显示母板还包括：设置在所述第一平坦层上的金属导电层，覆盖所述金属导电层的第二平坦层。
在示例性实施方式中，所述第一凹槽的深度可以为0.2μm到1.3μm，所述第二凹槽的深度可以为0.5μm到1.4μm。
本公开还提供了一种显示基板的制备方法。在示例性实施方式中，显示基板的制备方法可以包括：
S1、在多个基板区域和围绕所述基板区域的切割区域形成驱动结构层，所述切割区域的驱动结构层包括设置在柔性基底上的复合绝缘层，所述复合绝缘层形成台阶结构的凹槽；
S2、形成覆盖所述驱动结构层的第一平坦层，所述第一平坦层填充所述凹槽；
S3、在所述切割区域进行切割形成显示基板，在所述显示基板的边缘区域形成台阶结构；所述台阶结构中台阶的高度从显示基板边缘到显示基板内部的方向依次增大；所述第一平坦层覆盖所述台阶结构，所述第一平坦层的边缘与所述柔性基板的边缘平齐。
在示例性实施方式中，所述复合绝缘层可以包括多个叠设的无机绝缘层，所述凹槽可以暴露出所述柔性基底。
在示例性实施方式中，步骤S1中在切割区域形成驱动结构层，可以包括：
S11、在柔性基底上依次形成第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层；
S12、对所述第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层进行构图，形成暴露出所述柔性基底的凹槽。
在示例性实施方式中，所述柔性基底可以包括叠设的第一柔性层、第一阻挡层、非晶硅层、第二柔性层和第二阻挡层，所述第二阻挡层可以包括在所述第二柔性层上叠设的第一子层和第二子层；所述第一绝缘层可以形成在所述第二阻挡层的第二子层上；步骤S12包括：
通过第一次构图工艺，在所述第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层上形成暴露出所述第一绝缘层的第二凹槽；
通过第二次构图工艺，在所述第二凹槽内的第一绝缘层和第二阻挡层的第二子层上形成暴露出所述柔性基底的第二阻挡层的第一子层的第一凹槽，所述第二凹槽暴露出所述第一凹槽。
本公开提供了一种显示基板的制备方法，通过设置第一平坦层完全填充切割区域的凹槽，避免了在金属导电层构图工艺中出现金属块残留，在后续工艺中既不会出现Ag粒子和颗粒，也不会出现Ag粒子和颗粒随处附着的情形，有效避免了显示基板出现暗点不良。本公开的制备工艺利用现有成熟的制备设备即可实现，对现有工艺改进较小，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本申请中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或 者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本申请的权利要求的范围当中。

Claims (20)

  1. 一种显示基板，包括柔性基底和设置在所述柔性基底上的复合绝缘层，所述显示基板的边缘区域包括由所述复合绝缘层形成的台阶结构；所述台阶结构中台阶的高度从显示基板边缘到显示基板内部的方向依次增大；所述边缘区域还包括覆盖所述台阶结构的第一平坦层，所述第一平坦层的边缘与所述柔性基板的边缘平齐。
  2. 根据权利要求1所述的显示基板，其中，所述台阶结构包括第一台阶、第二台阶和第三台阶，所述第一台阶的厚度大于所述第二台阶的厚度，所述第一台阶的厚度大于所述第三台阶的厚度。
  3. 根据权利要求2所述的显示基板，其中，所述第一台阶的厚度为15μm到20.7μm，所述第二台阶的厚度为0.2μm到1.3μm，所述第三台阶的厚度为0.5μm到1.4μm。
  4. 根据权利要求2所述的显示基板，其中，所述显示基板的边缘区域还包括设置在所述第一平坦层上的第二平坦层，所述第二平坦层在所述柔性基底上的正投影与所述第一台阶和第二台阶在所述柔性基底上的正投影部分重叠。
  5. 根据权利要求4所述的显示基板，其中，在显示基板内部到显示基板边缘的方向，所述第二平坦层在所述柔性基底上的正投影与所述第一台阶在所述柔性基底上的正投影重叠的宽度为10μm到20μm，所述第二平坦层在所述柔性基底上的正投影与所述第二台阶在所述柔性基底上的正投影重叠的宽度为20μm到30μm。
  6. 根据权利要求1到5任一项所述的显示基板，其中，所述显示基板的基板区域包括：设置在所述柔性基底上的第一绝缘层，设置在所述第一绝缘层上的有源层，覆盖所述有源层的第二绝缘层，设置在所述第二绝缘层上的第一栅金属层，覆盖所述第一栅金属层的第三绝缘层，设置在所述第三绝缘层上的第二栅金属层，覆盖所述第二栅金属层的第四绝缘层，设置在所述第四绝缘层上的源漏金属层，覆盖所述源漏金属层的第五绝缘层，设置在所述第一平坦层上的金属导电层，覆盖所述金属导电层的第二平坦层。
  7. 根据权利要求1到5任一项所述的显示基板，其中，所述柔性基底包括依次叠设的第一柔性层、第一阻挡层、非晶硅层、第二柔性层和第二阻挡层，所述复合绝缘层包括在所述第二阻挡层上叠设的第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层；所述第一柔性层、第一阻挡层、非晶硅层和第二柔性层的总厚度为15μm到20μm，所述第二阻挡层的厚度为0.4μm到0.7μm，所述第一绝缘层的厚度为0.2μm到0.6μm。
  8. 根据权利要求7所述的显示基板，其中，所述第二阻挡层包括在所述第二柔性层上叠设的第一子层和第二子层；所述第一台阶包括所述第一柔性层、第一阻挡层、非晶硅层、第二柔性层和所述第二阻挡层的第一子层，所述第二台阶包括所述第二阻挡层的第二子层和第一绝缘层，所述第三台阶包括所述第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层；所述第一台阶的上表面与参考面之间的距离为0.05μm到0.06μm，所述第二台阶的上表面与参考面之间的距离为0.75μm到0.95μm，所述第三台阶的上表面与参考面之间的距离可以为1.40μm到1.80μm，所述参考面为所述第一子层邻近所述第二柔性层一侧的表面。
  9. 根据权利要求1到5任一项所述的显示基板，其中，所述第二台阶和第三台阶的侧壁为坡面，所述坡面的母线与所述显示基板的法线方向的夹角为20°到50°。
  10. 根据权利要求1到5任一项所述的显示基板，其中，第一台阶的边缘到第二台阶的边缘的距离大于第二台阶的边缘到第三台阶的边缘的距离，第一台阶的边缘到第二台阶的边缘的距离大于第三台阶的边缘到裂缝坝的边缘的距离。
  11. 根据权利要求10所述的显示基板，第一台阶的边缘到第二台阶的边缘的距离为55μm到210μm，第二台阶的边缘到第三台阶的边缘的距离为5μm到40μm，第三台阶的边缘到裂缝坝的边缘的距离为5μm到15μm。
  12. 根据权利要求1到5任一项所述的显示基板，其中，所述边缘区域的复合绝缘层上还设置有裂缝坝，所述裂缝坝包括多个间隔设置的裂缝，所述裂缝暴露出所述第一绝缘层；所述第一平坦层覆盖所述裂缝坝。
  13. 根据权利要求1到5任一项所述的显示基板，其中，所述显示基板的边缘区域包括周边区和切割内区，所述切割内区位于所述周边区远离基板区域的一侧；所述台阶结构设置在所述切割内区，所述裂缝坝设置在所述周边区。
  14. 根据权利要求13所述的显示基板，其中，所述显示基板的基板区域包括显示区域和设置在所述显示区域一侧的绑定区域，所述绑定区域远离所述显示区域一侧的边缘区域形成阶梯结构，所述阶梯结构包括第一阶梯和第二阶梯，所述第一阶梯由柔性基底和复合绝缘层形成，所述第二阶梯由所述第一平坦层和第二平坦层形成；除了所述绑定区域远离所述显示区域一侧的边缘区域，所述台阶结构设置在所述显示区域和绑定区域的其它边缘区域中。
  15. 一种显示母板，包括多个基板区域和围绕所述基板区域的切割区域；所述显示母板包括：设置在所述基板区域和切割区域的驱动结构层，设置在所述驱动结构层上的第一平坦层；所述切割区域的驱动结构层包括复合绝缘层，所述复合绝缘层设置有凹槽，所述第一平坦层填充所述凹槽。
  16. 根据权利要求15所述的显示母板，其中，所述基板区域的驱动结构层包括：设置在柔性基底上的第一绝缘层，设置在所述第一绝缘层上的有源层，覆盖所述有源层的第二绝缘层，设置在所述第二绝缘层上的第一栅金属层，覆盖所述第一栅金属层的第三绝缘层，设置在所述第三绝缘层上的第二栅金属层，覆盖所述第二栅金属层的第四绝缘层，设置在所述第四绝缘层上的源漏金属层，覆盖所述源漏金属层的第五绝缘层；所述切割区域的驱动结构层包括：在柔性基底上叠设的第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层；所述柔性基底包括叠设的第一柔性层、第一阻挡层、非晶硅层、第二柔性层和第二阻挡层；所述第一柔性层、第一阻挡层、非晶硅层和第二柔性层的总厚度为15μm到20μm，所述第二阻挡层的厚度为0.4μm到0.7μm，所述第一绝缘层的厚度为0.2μm到0.6μm。
  17. 根据权利要求16所述的显示母板，其中，所述第二阻挡层包括在所述第二柔性层上叠设的第一子层和第二子层；所述凹槽包括第一凹槽和第二凹槽，所述第一凹槽设置在所述第一绝缘层和第二阻挡层的第二子层上， 所述第一凹槽暴露出所述第二阻挡层的第一子层，所述第二凹槽设置在所述第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层上，所述第二凹槽暴露出所述第一绝缘层和所述第二阻挡层的第一子层，所述第二凹槽在柔性基底上的正投影包含所述第一凹槽在柔性基底上的正投影；所述第一凹槽的深度为0.2μm到1.3μm，所述第二凹槽的深度为0.5μm到1.4μm。
  18. 一种显示基板的制备方法，包括：
    在多个基板区域和围绕所述基板区域的切割区域形成驱动结构层，所述切割区域的驱动结构层包括设置在柔性基底上的复合绝缘层，所述复合绝缘层形成台阶结构的凹槽；
    形成覆盖所述驱动结构层的第一平坦层，所述第一平坦层填充所述凹槽；
    在所述切割区域进行切割形成显示基板，在所述显示基板的边缘区域形成台阶结构；所述台阶结构中台阶的高度从显示基板边缘到显示基板内部的方向依次增大；所述第一平坦层覆盖所述台阶结构，所述第一平坦层的边缘与所述柔性基板的边缘平齐。
  19. 根据权利要求18所述的制备方法，其中，在切割区域形成驱动结构层，包括：
    在柔性基底上依次形成第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层；所述柔性基底包括叠设的第一柔性层、第一阻挡层、非晶硅层、第二柔性层和第二阻挡层，所述第二阻挡层包括在所述第二柔性层上叠设的第一子层和第二子层；所述第一绝缘层形成在所述第二阻挡层的第二子层上；
    通过第一次构图工艺，在所述第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层上形成暴露出所述第一绝缘层的第二凹槽；
    通过第二次构图工艺，在所述第二凹槽内的第一绝缘层和第二阻挡层的第二子层上形成暴露出所述第二阻挡层的第一子层的第一凹槽，所述第二凹槽暴露出所述第一凹槽。
  20. 一种显示装置，包括如权利要求1到14任一项所述的显示基板。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024103995A1 (zh) * 2022-11-17 2024-05-23 京东方科技集团股份有限公司 显示基板、显示装置

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230170353A1 (en) * 2020-06-18 2023-06-01 Sony Semiconductor Solutions Corporation Display apparatus, method of manufacturing display apparatus, and electronic apparatus
CN112396957B (zh) * 2020-11-06 2022-04-01 武汉华星光电半导体显示技术有限公司 一种显示终端及应用于显示终端中的显示面板
CN114300488B (zh) * 2021-12-30 2024-08-09 厦门天马微电子有限公司 显示面板及其制作方法、显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103794628A (zh) * 2012-10-31 2014-05-14 乐金显示有限公司 有机发光显示装置及其制造方法
US20150034935A1 (en) * 2013-07-31 2015-02-05 Samsung Display Co., Ltd. Flexible display device and manufacturing method thereof
CN108281570A (zh) * 2018-02-27 2018-07-13 京东方科技集团股份有限公司 一种显示面板及其制作方法
CN108807480A (zh) * 2018-06-11 2018-11-13 京东方科技集团股份有限公司 显示基板母板及其制作方法、和显示装置
CN109087999A (zh) * 2018-08-22 2018-12-25 京东方科技集团股份有限公司 柔性基底及其制备方法、柔性有机发光二极管显示基板
CN110796949A (zh) * 2019-11-08 2020-02-14 京东方科技集团股份有限公司 一种显示基板、其制作方法及母板、显示面板、显示装置

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000124459A (ja) * 1998-10-15 2000-04-28 Sony Corp 電気光学装置の製造方法及び電気光学装置用の駆動基板の製造方法
US7042024B2 (en) * 2001-11-09 2006-05-09 Semiconductor Energy Laboratory Co., Ltd. Light emitting apparatus and method for manufacturing the same
US7642711B2 (en) * 2004-07-06 2010-01-05 Fujifilm Corporation Functional layer having wiring connected to electrode and barrier metal between electrode and wiring
JP4680850B2 (ja) * 2005-11-16 2011-05-11 三星モバイルディスプレイ株式會社 薄膜トランジスタ及びその製造方法
KR101458901B1 (ko) * 2008-04-29 2014-11-10 삼성디스플레이 주식회사 가요성 표시 장치의 제조 방법
KR101267534B1 (ko) * 2009-10-30 2013-05-23 엘지디스플레이 주식회사 유기전계발광소자의 제조방법
KR101978783B1 (ko) 2012-11-09 2019-05-15 엘지디스플레이 주식회사 플렉서블 유기전계발광소자 및 그 제조방법
KR101971202B1 (ko) * 2012-11-22 2019-04-23 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 제조방법
TWI611582B (zh) * 2013-04-10 2018-01-11 半導體能源研究所股份有限公司 半導體裝置及其製造方法
KR102180037B1 (ko) * 2013-11-06 2020-11-18 삼성디스플레이 주식회사 가요성 표시 장치 및 그 제조 방법
KR102141209B1 (ko) * 2014-03-07 2020-08-05 삼성디스플레이 주식회사 디스플레이 장치 및 이의 제조 방법
JP2015195104A (ja) * 2014-03-31 2015-11-05 株式会社ジャパンディスプレイ 表示装置
KR102156781B1 (ko) * 2014-06-10 2020-09-17 엘지디스플레이 주식회사 유기전계발광표시장치
TWI553837B (zh) * 2014-06-17 2016-10-11 友達光電股份有限公司 製作顯示面板之方法
KR102271659B1 (ko) 2014-08-29 2021-06-30 엘지디스플레이 주식회사 터치 패널 내장형 유기 발광 표시 장치
US9287329B1 (en) * 2014-12-30 2016-03-15 Lg Display Co., Ltd. Flexible display device with chamfered polarization layer
KR102396295B1 (ko) 2015-08-04 2022-05-11 삼성디스플레이 주식회사 플렉서블 디스플레이 장치 및 그 제조방법
KR102631257B1 (ko) * 2016-11-18 2024-01-31 삼성디스플레이 주식회사 디스플레이 장치
CN106653820B (zh) * 2017-03-08 2019-04-05 京东方科技集团股份有限公司 一种柔性显示面板及制作方法、柔性显示装置
US10727424B2 (en) * 2017-04-27 2020-07-28 Sharp Kabushiki Kaisha Flexible display device
KR102333671B1 (ko) * 2017-05-29 2021-12-01 삼성디스플레이 주식회사 유기 발광 표시 장치 및 유기 발광 표시 장치의 제조 방법
CN107591498B (zh) * 2017-08-31 2019-05-10 京东方科技集团股份有限公司 Oled显示面板及其制作方法、oled显示装置
KR102427667B1 (ko) * 2017-09-26 2022-08-02 삼성디스플레이 주식회사 디스플레이 장치
KR102606570B1 (ko) * 2017-11-29 2023-11-30 삼성디스플레이 주식회사 표시패널 및 그 제조방법
KR102126552B1 (ko) * 2017-12-19 2020-06-24 엘지디스플레이 주식회사 표시 장치
CN108364987B (zh) * 2018-02-24 2021-01-26 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN108447872B (zh) 2018-03-14 2021-01-22 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置
KR102667164B1 (ko) * 2018-08-02 2024-05-23 삼성디스플레이 주식회사 표시 패널 및 이를 포함하는 전자 장치
KR102625708B1 (ko) * 2018-08-27 2024-01-16 삼성디스플레이 주식회사 표시 장치
CN109638050B (zh) * 2018-12-14 2020-11-10 武汉华星光电半导体显示技术有限公司 显示面板及其制作方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103794628A (zh) * 2012-10-31 2014-05-14 乐金显示有限公司 有机发光显示装置及其制造方法
US20150034935A1 (en) * 2013-07-31 2015-02-05 Samsung Display Co., Ltd. Flexible display device and manufacturing method thereof
CN108281570A (zh) * 2018-02-27 2018-07-13 京东方科技集团股份有限公司 一种显示面板及其制作方法
CN108807480A (zh) * 2018-06-11 2018-11-13 京东方科技集团股份有限公司 显示基板母板及其制作方法、和显示装置
CN109087999A (zh) * 2018-08-22 2018-12-25 京东方科技集团股份有限公司 柔性基底及其制备方法、柔性有机发光二极管显示基板
CN110796949A (zh) * 2019-11-08 2020-02-14 京东方科技集团股份有限公司 一种显示基板、其制作方法及母板、显示面板、显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4131217A4

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024103995A1 (zh) * 2022-11-17 2024-05-23 京东方科技集团股份有限公司 显示基板、显示装置

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