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WO2021147081A1 - 显示基板及其制备方法 - Google Patents

显示基板及其制备方法 Download PDF

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Publication number
WO2021147081A1
WO2021147081A1 PCT/CN2020/073993 CN2020073993W WO2021147081A1 WO 2021147081 A1 WO2021147081 A1 WO 2021147081A1 CN 2020073993 W CN2020073993 W CN 2020073993W WO 2021147081 A1 WO2021147081 A1 WO 2021147081A1
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WO
WIPO (PCT)
Prior art keywords
layer
display area
light
display
base substrate
Prior art date
Application number
PCT/CN2020/073993
Other languages
English (en)
French (fr)
Inventor
龙跃
邱远游
黄炜赟
黄耀
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to KR1020217038042A priority Critical patent/KR20220131490A/ko
Priority to JP2021566044A priority patent/JP7482900B2/ja
Priority to CN202080000319.8A priority patent/CN113439339B/zh
Priority to US17/288,823 priority patent/US12108647B2/en
Priority to EP20866970.5A priority patent/EP4095917A4/en
Priority to PCT/CN2020/073993 priority patent/WO2021147081A1/zh
Priority to CN202010130251.7A priority patent/CN111326560B/zh
Priority to US17/297,641 priority patent/US11968865B2/en
Priority to EP20891410.1A priority patent/EP4095921A4/en
Priority to PCT/CN2020/080182 priority patent/WO2021147160A1/zh
Priority to CN202080000311.1A priority patent/CN113508466B/zh
Priority to JP2022502521A priority patent/JP7575443B2/ja
Priority to KR1020217038802A priority patent/KR20220129999A/ko
Priority to US17/428,847 priority patent/US11980071B2/en
Priority to PCT/CN2021/073243 priority patent/WO2021147987A1/zh
Publication of WO2021147081A1 publication Critical patent/WO2021147081A1/zh
Priority to US18/390,381 priority patent/US20240172497A1/en
Priority to US18/396,840 priority patent/US20240138214A1/en
Priority to US18/758,322 priority patent/US20240357894A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/11—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/813—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the embodiment of the present disclosure relates to a display substrate and a preparation method thereof.
  • display screens used in electronic devices are developing towards larger screens and full screens, so as to enable users to have a better visual experience.
  • these electronic devices need to incorporate components such as cameras and light sensors, and these components usually occupy the display area of the display screen, which makes it difficult to realize a full-screen design for the display screen.
  • At least one embodiment of the present disclosure provides a display substrate having a first side for display and a second side opposite to the first side, the display substrate including a display area, wherein the display area Comprising a first display area and a second display area at least partially surrounding the first display area, the first display area allowing light from the first side to be at least partially transmitted to the second side; the display substrate It also includes at least one first connection trace in the first display area and the second display area, wherein the first connection trace includes a first portion located in the first display area and a first portion located in the first display area that are electrically connected to each other.
  • the second part of the second display area, the first part includes a first light-transmitting wiring layer, and the second part includes a metal wiring layer.
  • the first display area includes a plurality of first sub-pixels arranged in an array, each first sub-pixel includes a first light-emitting device, and the at least one first sub-pixel
  • the connecting wires include a plurality of first connecting wires;
  • the second display area includes a plurality of first pixel circuits, and the plurality of first pixel circuits are electrically connected to the plurality of pixels through the plurality of first connecting wires.
  • the first light emitting devices of the first sub-pixels are used to drive the first light emitting devices of the plurality of first sub-pixels.
  • the second part further includes a second light-transmitting wiring layer laminated with the metal wiring, and the second light-transmitting wiring layer is connected to the metal wiring layer.
  • the first light-transmitting wiring layer is arranged on the same layer and connected integrally.
  • the second part further includes an anti-oxidation protection layer laminated with the metal traces
  • the display substrate includes a base substrate
  • the second light-transmitting layer The wiring layer is located on the base substrate
  • the metal wiring layer is located on the side of the second light-transmitting wiring layer away from the base substrate
  • the anti-oxidation protection layer is located on the metal wiring The side of the layer away from the base substrate.
  • the material of the metal wiring layer includes Ag, Al, Mo, or Ti; the material of the anti-oxidation protection layer includes transparent oxide.
  • the first light emitting device includes a first anode structure, a first cathode structure, and a first anode structure between the first anode structure and the first cathode structure.
  • the first part is electrically connected to the first anode structure through a via hole.
  • the second display area further includes a plurality of second sub-pixels, and each second sub-pixel includes a second light-emitting device and is electrically connected to the second light-emitting device.
  • the second pixel circuit is configured to drive the second light-emitting device, and in the second display area, the plurality of second pixel circuits are arranged in a first array.
  • the plurality of first pixel circuits are arranged in the first array and are connected to the plurality of second pixel circuits.
  • the arrangement is the second array.
  • the second light emitting device includes a second anode structure, a second cathode structure, and a second light emitting device between the second anode structure and the second cathode structure.
  • Layer, the second anode structure is electrically connected to the second pixel circuit through a via hole.
  • the display area further includes a third display area at least partially surrounding the second display area, and the third display area includes a plurality of third display areas arranged in an array.
  • each third sub-pixel includes a third light-emitting device and a third pixel circuit electrically connected to the third light-emitting device, the third pixel circuit is configured to drive the third light-emitting device, the third The light emitting device includes a third anode structure, a third cathode structure, and a third light emitting layer between the third anode structure and the third cathode structure, and the third anode structure is connected to the third pixel circuit through a via hole. Electric connection.
  • the display substrate includes a base substrate, the first display area further includes a transparent support layer on the base substrate, and the first light-emitting device is located The side of the transparent support layer away from the base substrate.
  • the first pixel circuit includes a thin film transistor and a storage capacitor, and the thin film transistor includes an active layer, a gate, and a source and drain electrode;
  • the storage capacitor includes a first A capacitor plate and a second capacitor plate, the active layer is arranged on the base substrate, a first gate insulating layer is arranged on the side of the active layer away from the base substrate, and the gate
  • the electrode and the first capacitor plate are arranged in the same layer on the side of the first gate insulating layer away from the base substrate, and the gate and the first capacitor plate are away from the base substrate
  • a second gate insulation layer is provided on one side of the second gate insulation layer, the second capacitor plate is provided on the side of the second gate insulation layer away from the base substrate, and the second capacitor plate is away from the liner
  • An interlayer insulating layer is provided on one side of the base substrate, and the source and drain electrodes are provided on the side of the interlayer insulating layer away from the base substrate and pass through the first gate
  • the gate insulating layer and the vias in the interlayer insulating layer are electrically connected to the active layer, and the source and drain electrodes are provided with a planarization layer on the side away from the base substrate; the transparent support layer is connected to At least one of the first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, and the planarization layer is provided in the same layer.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a sensor, wherein the sensor is disposed on the second side of the display substrate, and the orthographic projection of the sensor on the base substrate is consistent with the first A display area at least partially overlaps and is configured to receive the light from the first side.
  • At least one embodiment of the present disclosure provides a method for preparing a display substrate, the display substrate having a first side for display and a second side opposite to the first side, and the preparation method includes: forming a display area, The display area includes a first display area and a second display area at least partially surrounding the first display area, the first display area allowing light from the first side to be at least partially transmitted to the second side; At least one first connection trace is formed in the first display area and the second display area, wherein the first connection trace includes a first portion located in the first display area and a second portion located in the second display area that are electrically connected to each other.
  • the second part of the display area, the first part includes a first light-transmitting wiring layer, and the second part includes a metal wiring layer.
  • forming the display area further includes: forming a plurality of first sub-pixels arranged in an array in the first display area, each of the first sub-pixels The pixel includes a first light-emitting device, and a plurality of first pixel circuits are formed in the second display area, wherein the at least one first connection trace includes a plurality of first connection traces; the plurality of first pixels The circuit is respectively electrically connected to the first light-emitting devices of the plurality of first sub-pixels through the plurality of first connecting wires, so as to drive the first light-emitting devices of the plurality of first sub-pixels.
  • forming the second part of the first connection trace further includes: forming a second light-transmitting trace layer laminated with the metal trace, wherein, the second light-transmitting wiring layer and the first light-transmitting wiring layer are formed in the same layer and are integrally connected.
  • the method for preparing a display substrate further includes: providing a base substrate, wherein forming the second part of the first connection trace further includes: forming an anti-oxidation layer laminated with the metal trace A protective layer, wherein the second light-transmitting wiring layer is formed on the base substrate, and the metal wiring layer is formed on a side of the second light-transmitting wiring layer away from the base substrate.
  • the anti-oxidation protection layer is formed on a side of the metal wiring layer away from the base substrate.
  • forming the first connection trace includes: sequentially depositing light-transmitting traces on the first display area and the second display area through a mask.
  • forming the first connection trace includes: sequentially depositing light-transmitting traces on the first display area and the second display area through a mask. Wire material layer, metal wire material layer, and conductive protective material layer; use wet etching to etch away the metal wire material layer and conductive protective material layer in the first display area; A layer of transparent wiring material is deposited in the first display area and the second display area.
  • forming the first pixel circuit includes forming a thin film transistor and a storage capacitor, and the thin film transistor includes an active layer, a gate, and source and drain electrodes;
  • the storage capacitor includes a first capacitor plate and a second capacitor plate, wherein the active layer is formed on the base substrate, and a first layer is formed on the side of the active layer away from the base substrate.
  • a gate insulating layer, the same layer of the gate electrode and the first capacitor plate is formed on the side of the first gate insulating layer away from the base substrate, and the gate electrode and the first capacitor electrode
  • a second gate insulating layer is formed on the side of the plate away from the base substrate, and the second capacitor plate is formed on the side of the second gate insulating layer away from the base substrate.
  • An interlayer insulating layer is formed on the side of the capacitor plate away from the base substrate, and the source and drain electrodes are formed on the side of the interlayer insulating layer away from the base substrate and pass through the first gate.
  • Forming the first display area further includes: forming a transparent support layer between the base substrate and the first light-emitting device, wherein the transparent support layer and the first gate insulating layer, the first At least one of the second gate insulating layer, the interlayer insulating layer, and the planarization layer is formed in the same layer.
  • the method for preparing a display substrate further includes: providing a sensor, and combining the sensor on the second side of the display substrate, wherein the sensor is on the base substrate.
  • the orthographic projection at least partially overlaps the first display area, and is configured to receive the light from the first side.
  • Fig. 1A is a schematic plan view of a display substrate
  • Fig. 1B is a partial enlarged schematic diagram of a display substrate
  • FIG. 2 is a schematic cross-sectional view of the display substrate in FIG. 1B along the line A-A;
  • FIG. 3 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic cross-sectional view of the display substrate in FIG. 3 along the line B-B;
  • FIG. 5 is a schematic plan view of a first display area and a second display area in a display substrate provided by at least one embodiment of the present disclosure
  • Fig. 6 is another schematic cross-sectional view of the display substrate in Fig. 3 along the line B-B;
  • FIG. 7 is another schematic cross-sectional view of the display substrate in FIG. 3 along the line B-B;
  • Fig. 8 is another schematic cross-sectional view of the display substrate in Fig. 3 along the line B-B;
  • FIG. 9 is another schematic plan view of a first display area and a second display area in a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 10 is another schematic plan view of a first display area and a second display area in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 11 is a schematic plan view of the arrangement of sub-pixels in a display area of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 12 is a schematic plan view of a wiring arrangement in a display area of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 13 is another schematic plan view of wiring arrangement in a display area of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 14 is still another schematic plan view of the first display area and the second display area in a display substrate provided by at least one embodiment of the present disclosure
  • 15 is a schematic cross-sectional view of a second display area in a display substrate provided by at least one embodiment of the present disclosure
  • 16 is a schematic cross-sectional view of a third display area in a display substrate provided by at least one embodiment of the present disclosure
  • 17A-17B are schematic cross-sectional views of a display substrate provided by at least one embodiment of the present disclosure during the manufacturing process.
  • 18A-18B are schematic cross-sectional views of a display substrate provided by at least one embodiment of the present disclosure during the manufacturing process.
  • part of the display area used to install the sensor (such as image sensor, infrared sensor) and other components can be designed as a light-transmitting display area, so the light-transmitting display area can be While realizing the display function, it also facilitates the installation of sensors and other components.
  • FIG. 1A shows a schematic plan view of a display substrate
  • FIG. 1B is a partial enlarged schematic view of the display substrate shown in FIG. 1A
  • FIG. 2 shows a schematic cross-sectional view of the display substrate in FIG. 1B along the line A-A.
  • the display area of the display substrate includes a light-transmitting display area 1, a peripheral display area 2 and a main body display area 3.
  • the main display area 3 is the main display area and has a higher resolution (PPI, Pixel Per Inch), that is, the main display area 3 is arranged with sub-pixels with higher density for display.
  • Each sub-pixel includes a light-emitting device and a pixel circuit that drives the light-emitting device.
  • the light-transmitting display area 1 may allow light incident from the display side of the display substrate to pass through the display substrate to reach the back side of the display substrate, so as to be used for normal operation of components such as sensors located on the back side of the display substrate.
  • the light-transmitting display area 1 and the peripheral display area 2 also include a plurality of sub-pixels for display.
  • the pixel circuit of the sub-pixel usually does not transmit light
  • the sub-pixels in the light-transmitting display area 1 (for example, shown in the box in the light-transmitting display area 1 in FIG. 1B)
  • the pixel circuit can be set in the peripheral display area 2, as shown by the gray box in the peripheral display area 2, so it occupies part of the space of the peripheral display area 2, and the remaining space of the peripheral display area 2 is used to set the peripheral display area 2.
  • each white box in the peripheral display area 2 represents a sub-pixel.
  • the sub-pixels in the peripheral display area 2 (white boxes in FIG.
  • the resolution of the transparent display area 1 and the peripheral display area 2 is lower than the resolution of the main display area 3. That is, the density of the sub-pixels arranged in the transparent display area 1 and the peripheral display area 2 for display is less than Sub-pixel density of the main display area 3.
  • the light-emitting device 4 of one sub-pixel in the light-transmitting display area 1 includes an anode 4A, a cathode 4C, and a light-emitting layer 4B between the anode 4A and the cathode 4C.
  • the anode 4A is connected to the peripheral display area by a conductive wire. 2 in the pixel circuit 5.
  • the conductive lead may be a metal lead, for example, it may be the same material as the source and drain electrode metal in the pixel circuit of the sub-pixel, or it may be a transparent wiring (such as an ITO wiring) 6 electrically connected to the peripheral display area 2
  • the pixel circuit 5, and thus the pixel circuit 5 located in the peripheral display area 2 can be used to drive the light emitting device 4 located in the light-transmitting display area 1. Since the transparent wiring 6 has high light transmittance, it can be ensured that the light transmitting display area 1 also has high light transmittance.
  • components such as the sensor 7 provided on the back side of the display substrate can receive the light transmitted from the display side of the display substrate through the light-transmitting display area 1 to perform normal operation.
  • the transparent wiring 6 needs to extend from the pixel circuit 5 in the peripheral display area 2 to the light-emitting device 4 in the light-transmitting display area 1. Therefore, at least part of the transparent wiring 6 has a longer length, for example, its length will be too long.
  • the distance between the two sub-pixel regions on the other hand, compared to the source and drain electrode materials, such as Ti/Al/Ti, or either one or a combination of the two; or other electrode materials, such as copper, molybdenum, magnesium, Silver or a combination of at least two materials, etc.
  • the material used for the transparent wiring 6 has a relatively high resistance, and its preparation process is prone to deviations, which makes the overall resistance of the transparent wiring 6 relatively large, so the pixel circuit 5 transmits electrical signals to the sub-pixels in the light-transmitting display area 1.
  • the speed is slow, causing the sub-pixels in the light-transmitting display area 1 to be driven out of sync with the sub-pixels in the peripheral display area 2 and the main display area 3, which affects the display effect of the display area.
  • At least one embodiment of the present disclosure provides a display substrate and a preparation method thereof.
  • the display substrate has a first side for display and a second side opposite to the first side.
  • the display substrate includes a display area, and the display area includes a first display. Area and a second display area at least partially surrounding the first display area, the first display area allows light from the first side to be at least partially transmitted to the second side;
  • the display substrate further includes At least one first connection trace, the first connection trace includes a first portion located in the first display area and a second portion located in the second display area that are electrically connected to each other, the first portion includes a first light-transmitting wiring layer, and the second Part includes metal wiring layer.
  • the first connection wiring in the display substrate has a relatively low resistance.
  • FIG. 3 shows a schematic plan view of the display substrate
  • FIG. 4 shows a schematic cross-sectional view of the display substrate in FIG. 3 along the line B-B.
  • the display substrate has a first side for display (shown as the upper side of the display substrate in FIG. 4, that is, the display side of the display substrate) and a second side opposite to the first side. Side (shown as the lower side of the display substrate in FIG. 4).
  • the display substrate includes a display area, the display area includes a first display area 10 and a second display area 20 at least partially surrounding the first display area 10, and the first display area 10 allows light from the first side to be at least partially transmitted to the second display area.
  • the side, that is, the first display area 10 is at least partially light-transmissive, so as to facilitate the installation of image sensors, infrared sensors and other components.
  • the display substrate further includes at least one first connecting wire 15 in the first display area 10 and the second display area 20, and the first connecting wire 15 includes electrically connected to each other located in the first display area 10.
  • the first portion 15A and the second portion 15B located in the second display area 20 the first portion 15A includes a first light-transmitting wiring layer, and the second portion 15B includes a metal wiring layer.
  • the material of the first light-transmitting wiring layer may be a transparent conductive material, such as transparent metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO), and the material of the metal wiring layer may include silver (Ag), Metal materials such as aluminum (Al), molybdenum (Mo) or titanium (Ti) or their alloy materials. Since the resistance of the metal wiring layer is relatively low, the first connection wiring 15 may have a lower resistance than a wiring including only a light-transmitting wiring layer.
  • transparent metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO)
  • the material of the metal wiring layer may include silver (Ag), Metal materials such as aluminum (Al), molybdenum (Mo) or titanium (Ti) or their alloy materials. Since the resistance of the metal wiring layer is relatively low, the first connection wiring 15 may have a lower resistance than a wiring including only a light-transmitting wiring layer.
  • FIG. 5 shows a schematic plan view of a first display area 10 and a second display area 20.
  • the first display area 10 includes a plurality of first sub-pixels arranged in an array, each first sub-pixel includes a first light-emitting device 11, and the display area includes a plurality of first connections.
  • the wiring 15, the second display area 20 includes a plurality of first pixel circuits D, and the plurality of first pixel circuits D are electrically connected to the first light-emitting devices 11 of the plurality of first sub-pixels through the plurality of first connection wirings 15, respectively,
  • the first light emitting device 11 is used to drive a plurality of first sub-pixels.
  • the plurality of first pixel circuits D correspond to the first light-emitting devices 11 of the plurality of first sub-pixels one-to-one and are electrically connected by the first connecting wires 15.
  • one The first pixel circuit D is used to drive the first light emitting device 11 of a first sub-pixel.
  • one first pixel circuit D may be electrically connected to the first light-emitting devices 11 of the first sub-pixels through a plurality of first connection wires 15 respectively.
  • a first pixel circuit D The pixel circuit D can be used to drive the first light emitting devices 11 of a plurality of first sub-pixels.
  • the embodiment of the present disclosure does not specifically limit the correspondence between the first pixel circuit D and the first light-emitting device 11 of the first sub-pixel.
  • the first portion 15A of the first connection trace 15 includes a first light-transmitting trace layer
  • the second portion 15B of the first connection trace 15 includes a metal trace layer 16.
  • the second light-transmitting wiring layer 15C and the first light-transmitting wiring layer are arranged on the same layer and connected integrally, that is, the second light-transmitting wiring layer 15C and the first light-transmitting wiring layer are arranged in the same layer and in direct contact, thereby forming an integrated structure.
  • “same-layer arrangement” means that two functional layers or structural layers are formed in the same layer and with the same material in the hierarchical structure of the display substrate, that is, in the preparation process, the two functional layers
  • the layer or the structure layer can be formed of the same material layer, and the required pattern and structure can be formed through the same patterning process.
  • One patterning process includes, for example, photoresist formation, exposure, development, and etching.
  • the second portion 15B of the first connection trace 15 may further include an oxidation protection layer 17 laminated with the metal wiring layer 16, and the oxidation protection layer 17 may prevent
  • the metal wiring layer 16 is oxidized to ensure that the metal wiring layer 16 maintains high conductivity; in addition, the anti-oxidation protection layer 17 can also enhance the adhesion between the metal wiring layer 16 and the insulating layer 145 formed thereon to prevent The metal wiring layer 16 and the insulating layer 145 are poorly connected.
  • the anti-oxidation protective layer 17 can be made of transparent oxide materials, such as ITO, IZO, and other transparent conductive oxide materials, thereby further reducing the resistance of the first connecting trace 15.
  • the display substrate includes a base substrate 14, the second light-transmitting wiring layer 15C is located on the base substrate 14, and the metal wiring layer 16 is located on the second light-transmitting wiring layer 15C away from the base substrate.
  • the anti-oxidation protection layer 17 is located on the side of the metal wiring layer 16 away from the base substrate 14.
  • the above-mentioned design of the first connecting wires 15 can also improve the uniformity of the current flowing through the plurality of first connecting wires 15 And improve the display effect of the display substrate.
  • the second light-transmitting wiring layer 15C and the anti-oxidation protection layer 17 are spaced apart, and there is no contact.
  • the second light-transmitting wiring layer 15C and the anti-oxidation protective layer 17 may be physically connected, that is, in the embodiment shown in FIG. 6, the anti-oxidation
  • the protective layer 17 also covers the right side of the metal wiring layer 16 so as to be in physical contact with the second light-transmitting wiring layer 15C.
  • the three-layer conductive structure provided by this embodiment can also significantly reduce the resistance of the first connecting wire 15.
  • the first light-emitting device 11 includes a first anode structure 111, a first cathode structure 113, and a gap between the first anode structure 111 and the first cathode structure 113.
  • the first light-emitting layer 112 and the first portion 15A of the first connection trace 15 are electrically connected to the first anode structure 111 through a via hole.
  • an insulating layer 145 is provided on the first connection trace 15.
  • the insulation layer 145 has a via 145A in the first display area 10, and the first portion 15A of the first connection trace 15 passes through the via 145A in the insulation layer 145 and
  • the first anode structure 111 is electrically connected.
  • the first anode structure 111 includes multiple anode sublayers, for example, three anode sublayers are shown in the figure.
  • the three-layer anode sub-layer has an ITO/Ag/ITO three-layer laminated structure.
  • the first cathode structure 113 may be a structure formed on the entire surface of the display substrate.
  • the first cathode structure 113 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag). Since the first cathode structure 113 can be formed as a very thin layer, the first cathode structure 113 has good light transmittance.
  • the first connecting trace 15 and the first anode structure 111 may also adopt different designs from those in FIGS. 4 and 6.
  • the first portion 15A of the first connection trace 15 may be arranged in the same layer and integrally connected with the bottom anode sublayer (for example, ITO layer) of the multilayer anode sublayers included in the first anode structure 111 .
  • the second light-transmitting wiring 15C included in the second portion 15B of the first connecting wiring 15 can be arranged on the same layer and integrally connected with the first portion 15A, and the metal wiring layer 16 included in the second portion 15B is connected to the first portion 15A.
  • the intermediate layer anode sublayers (for example, Ag layer) of the multilayer anode sublayers included in the anode structure 111 are arranged in the same layer, and the oxidation protection layer 17 included in the second part 15B is the same as the multilayers included in the first anode structure 111
  • the top anode sublayer (for example, ITO layer) in the anode sublayer is arranged in the same layer. Therefore, the preparation process of the display substrate can be simplified. For example, compared to the display substrate shown in FIG. 4 and FIG. 6, the display substrate shown in FIG. 7 can use the same patterning process to simultaneously form the first connection trace 15 and the first anode structure 111, thereby reducing the number of separate The manufacturing process of the first connection trace 1 and the manufacturing process of the insulating layer 145.
  • the first connecting wire 15 may also adopt a design different from that of FIGS. 4, 6 and 7.
  • the first part 15A of the first connection trace is a first light-transmitting trace layer
  • the second part 15B is a metal trace layer
  • the first part 15A and the second part 15B are electrically connected through a via hole.
  • an insulating layer 148 is provided on the second portion 15B, the insulating layer 148 has a via 148A in the second display area 20, and the first portion 15A and the second portion 15B are electrically connected through the via 148A in the insulating layer 148.
  • FIG. 9 shows a plan view of the first display area 10 and the second display area 20 in the above situation.
  • the second display area 20 has a via area (area framed by a dashed line) at a position close to the first display area 10, and the first portion 15A and the second portion 15A of the multiple first connecting wires 15
  • the part 15B can be electrically connected through a plurality of via holes 148A provided in the via hole area, respectively.
  • the first connection wiring 15 can still have a lower resistance.
  • the second display area 20 further includes a plurality of second sub-pixels P, and each second sub-pixel P includes a second light-emitting device and a second light-emitting device electrically connected to the second light-emitting device.
  • the second pixel circuit, the second pixel circuit is configured to drive the second light-emitting device; in the second display area 20, a plurality of second pixel circuits are arranged in a first array, that is, the array arranged by the gray squares in FIG. 5 .
  • a plurality of first pixel circuits D are dispersedly arranged in a first array, and are arranged in a second array with a plurality of second pixel circuits D, as shown in FIG. 5
  • FIG. 10 shows another plan view of the first display area 10 and the second display area 20.
  • the first connection trace 15 may cross the second sub-pixel P in the second display area 20 to electrically connect the first light emitting device 11 (for example, It includes an anode, a light-emitting layer, and a cathode) and a first pixel circuit D (for example, including a driving transistor, a storage capacitor, etc.) located in the second display area 20 for driving the first light-emitting device 11.
  • the first light emitting device 11 for example, It includes an anode, a light-emitting layer, and a cathode
  • a first pixel circuit D for example, including a driving transistor, a storage capacitor, etc.
  • the first connection trace 15 may be linearly electrically connected to the first light emitting device 11 located in the first display area 10 and the first light emitting device 11 located in the second display area 20 for driving the first
  • the data lines D (for example, D1, D2) used to drive the first sub-pixels in the first display area 10 may be arranged around the boundary of the second display area 20 close to the first display area 10.
  • the pixel circuits of the sub-pixels located in the same column can be electrically connected to the same data line, so that the light-emitting devices of the sub-pixels located in the same column can be driven by the same data line.
  • the data line D1 on the left is electrically connected to the pixel circuits of the first column of sub-pixels on the left in the first display area 10 through windings
  • the data line D2 on the right is electrically connected to the first display.
  • other columns of sub-pixels in the first display area 10 are also respectively connected to a data line, which is not shown in the figure.
  • the column direction refers to the vertical direction in the figure
  • the row direction refers to the horizontal direction in the figure.
  • the column direction and the row direction can be interchanged. The embodiments of the present disclosure do not limit this.
  • the wiring dense area Jumper wire design can be used, that is, the wires are arranged in different wire layers.
  • FIG. 11 shows a pattern of first sub-pixel arrangement in the first display area.
  • the second sub-pixels in the second display area 20 also have the arrangement rule of sub-pixels as shown in FIG. 11.
  • every four sub-pixels constitute a repeating unit, and each sub-pixel has a different shape.
  • the anode structure of the light-emitting device of each sub-pixel also has a different shape, corresponding to light-emitting devices of the same or different colors.
  • a repeating unit may include four sub-pixels of GGRB. For example, as shown in FIG.
  • the first anode structure 111 of the first light-emitting device of each first sub-pixel has a different shape, and performs as shown in FIG. They are arranged to correspond to light of the same or different colors.
  • the four first sub-pixels 111 may respectively emit light of different colors such as green, green, red, and blue.
  • the above-mentioned repeating units may not be limited to four, for example, three of R, G, and B may be used, or other arrangements may be adopted, such as RGBG.
  • FIG. 12 shows the connection manner of the data line D when the first sub-pixel in the first display area 10 and the second sub-pixel in the second display area 20 are arranged in the above-mentioned sub-pixel arrangement.
  • the data line D is arranged around the boundary of the second display area 20 close to the first display area 10, and in the first display area 10 and the second display area 20, the sub-lines in the same column
  • the pixel circuits of the pixels are electrically connected to the same data line D.
  • the first pixel circuit located in the second display area 20 which is shown by a gray square, is electrically connected to the first pixel circuit located on the left in the first display area 10 through the first connection wiring 15.
  • a light-emitting device of a first sub-pixel, through the winding of the data line D, can connect the sub-pixels in the same column as the first first sub-pixel on the left side (whether it is the first sub-pixel or the second sub-pixel)
  • the pixel circuits are electrically connected, so that the pixel circuits of the sub-pixels in the same column are electrically connected to the same data line.
  • a part DA of the data line D (shown in the figure as a thick line extending horizontally on the upper side of the data line D) can be set by means of jumpers, that is, a part DA of the data line D can be set with other parts of the data line D In different layers.
  • the use of jumper design can reduce the arrangement space of the data lines, which is more conducive to the arrangement of the wires.
  • FIG. 12 only shows the connection traces and data lines of one first sub-pixel in the first display area 10, and other first sub-pixels in the first display area 10 also have similar connection relationships.
  • the area occupied by the gray box may have one of the pixel repeating units, or the first pixel circuits of multiple first sub-pixels.
  • the one or more first pixel circuits may respectively pass through one or more first pixel circuits.
  • the first connecting wires 15 are electrically connected to one or more first sub-pixels of a pixel repeating unit in the first display area 10.
  • the area occupied by the gray box may have first pixel circuits of four first sub-pixels of one pixel unit.
  • the four first pixel circuits may be electrically connected to each other through four first connecting wires 15 Four first sub-pixels of one pixel unit in the first display area 10.
  • the data line D may be wound on one side of the second display area 20, for example, FIG. 12 shows a situation where the data line D is wound on the upper side of the second display area 20.
  • the data line D can also be wound on the upper and lower sides of the second display area 20 at the same time.
  • the data line D may be routed between the pixel rows of the second display area 20, which is not limited in this embodiment.
  • the pixel circuits of the first column of sub-pixels on the left in the first display area 10 and the second display area 20 use the same data line D3 (the data on the left in the figure)
  • the pixel circuits of the second column of sub-pixels on the left are electrically connected by the same data line D4 (the data line on the right in the figure).
  • the data lines are simultaneously wound on the upper and lower sides of the second display area 20
  • the light-emitting devices of the sub-pixels located in the same column can be driven by the same data line.
  • a part DA of the data line D3 and the data line D4 can also be designed with jumpers.
  • the data lines are arranged densely, so a jumper design can be adopted for part of the data lines wound around the edge to save space and simplify the circuit arrangement.
  • FIG. 13 only shows the connection traces and data lines of the four first sub-pixels in the first display area 10, and other first sub-pixels in the first display area 10 also have similar connection relationships. 13 is not shown.
  • the area occupied by the gray box may have a first pixel circuit of four first sub-pixels of one pixel repeating unit.
  • the four first pixel circuits may be electrically connected by four first connecting wires 15 respectively.
  • the first sub-pixels located in the third column on the left side of the first display area 10 and the second column of second sub-pixels P in the second display area 20 above the first display area 10 are located in the same column , And the first sub-pixel (specifically the light-emitting device of the first sub-pixel, such as the anode, the light-emitting layer, and the cathode) in the third column on the left side of the first display area 10 is covered by the second display area above the first display area
  • the first pixel circuit D in the first column of 20 (for example, including a driving transistor, a storage capacitor, etc.) D is driven.
  • the data line D can pass through the first pixel circuit D and the first pixel circuit D in the first column of the second display area 20.
  • the second column of the second sub-pixel P is wound to electrically connect the pixel circuits of the sub-pixels in the same column to the same data line, so that the light-emitting devices of the sub-pixels in the same column can be driven by the same data line.
  • the pixel circuits of the sub-pixels located in the same row can be electrically connected to the same scan line, so that the light-emitting devices of the sub-pixels located in the same row can be driven by the same scan line.
  • the first light emitting device 11 located in the first first sub-pixel in the first row of the first display area 10 and the second display area 20 located on the left side of the first display area 10 are A pixel circuit D is electrically connected, the light-emitting device 11 of the second first sub-pixel in the first row in the first display area 10 and a first pixel circuit in the second display area 20 located on the upper side of the first display area 10 D is electrically connected.
  • the first pixel circuit D of the two first sub-pixels in the same row can be electrically connected through the winding of the scan line G1 (the scan line on the left in the figure).
  • the first light-emitting device 11 located in the first first sub-pixel of the third row in the first display area 10 is electrically connected to a first pixel circuit D located in the second display area 20 on the left side of the first display area 10.
  • the light emitting device 11 of the second first sub-pixel located in the third row in the first display area 10 is electrically connected to a first pixel circuit D in the second display area 20 located on the upper side of the first display area 10, through
  • the winding of the scan line G2 (the scan line on the right in the figure) can electrically connect the first pixel circuits D of the two first sub-pixels in the same row (the third row in the figure).
  • the light-emitting devices of the sub-pixels located in the same row can be driven by the same scan line.
  • the pixel circuits of the sub-pixels located in the same column can be electrically connected to the same data line, and the pixel circuits of the sub-pixels located in the same row can be electrically connected The same scan line to simplify the drive control of each sub-pixel in the display panel.
  • the wires of different lines are respectively arranged in different wire layers, that is, the wires of different lines are arranged in different layers.
  • the first connection trace 15 with the darkest color and the thickest line, the data line D with darker color but thinner lines, and the scan line G with the lightest color and thinner lines are arranged in different layers, so in preparation Different material layers are used in the process.
  • the first pixel circuit D for driving the first light-emitting device 11 includes a thin film transistor 12 and a storage capacitor 13.
  • the thin film transistor 12 includes an active layer 121, a gate 122, and source and drain electrodes (ie, source and drain).
  • the electrode 123 and the drain electrode 124), and the storage capacitor 13 includes a first capacitor plate 131 and a second capacitor plate 132.
  • the active layer 121 is provided on the base substrate 14, the side of the active layer 121 away from the base substrate 14 is provided with a first gate insulating layer 141, and the gate 122 and the first capacitor plate 131 are provided in the same layer.
  • the side of the first gate insulating layer 141 away from the base substrate 14 and the side of the gate 122 and the first capacitor plate 131 away from the base substrate 14 are provided with a second gate insulating layer 142, and the second capacitor plate 132 It is arranged on the side of the second gate insulating layer away from the base substrate 14, the side of the second capacitor plate 132 away from the base substrate 14 is provided with an interlayer insulating layer 143, and the source and drain electrodes are arranged on the interlayer insulating layer 143
  • the side away from the base substrate 14 is electrically connected to the active layer 121 through the via holes in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143.
  • the source and drain electrodes
  • FIG. 15 shows a schematic cross-sectional view of a second display area 20.
  • the second display area 20 includes a second light-emitting device 21 and a second pixel circuit that drives the second light-emitting device 21.
  • the second pixel circuit includes structures such as a thin film transistor 22 and a storage capacitor 23.
  • the second light emitting device 21 includes a second anode structure 211, a second cathode structure 213, and a second light emitting layer 212 between the second anode structure 211 and the second cathode structure 213.
  • the second anode structure 211 is connected to the second pixel through the via hole.
  • the circuit is electrically connected.
  • the second anode structure 211 may include a plurality of anode sub-layers, such as a three-layer structure of ITO/Ag/ITO (not shown in the figure), etc.
  • the specific form of the second anode structure 211 is not described in the embodiment of the present disclosure. limited.
  • the thin film transistor 22 includes structures such as an active layer 221, a gate 222, and source and drain electrodes (ie, a source 223 and a drain 224), and the storage capacitor 23 includes a first capacitor plate 231 and a second capacitor plate 232.
  • the active layer 221 is provided on the base substrate 14, the side of the active layer 221 away from the base substrate 14 is provided with a first gate insulating layer 141, and the gate 222 and the first capacitor plate 231 are provided in the same layer.
  • the side of the first gate insulating layer 141 away from the base substrate 14 and the side of the gate 222 and the first capacitor plate 231 away from the base substrate 14 are provided with a second gate insulating layer 142, and the second capacitor plate 232 It is arranged on the side of the second gate insulating layer 142 away from the base substrate 14, and the side of the second capacitor plate 232 away from the base substrate 14 is provided with an interlayer insulating layer 143, and the source and drain electrodes are arranged on the interlayer insulating layer.
  • the side of the 143 away from the base substrate 14 is electrically connected to the active layer 221 through the via holes in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143.
  • the source and drain electrodes are away from the liner.
  • a planarization layer 144 is provided on one side of the base substrate 14 to planarize the second pixel circuit.
  • the planarization layer 144 has a via 144A, and the second anode structure 211 is electrically connected to the source 223 of the thin film transistor 22 through the via 144A in the planarization layer 144.
  • the transition layer may be provided in the same layer as the first connection trace 15.
  • the display area further includes a third display area 30 at least partially surrounding the second display area 20, and the third display area 30 includes a plurality of third sub-pixels arranged in an array.
  • FIG. 16 shows a schematic cross-sectional view of a third display area 30.
  • each third sub-pixel includes a third light-emitting device 31 and a third pixel circuit electrically connected to the third light-emitting device.
  • the third pixel circuit is configured to drive the third light emitting device 31.
  • the third light emitting device 31 includes a third anode structure 311, a third cathode structure 313, and a third light emitting layer 312 between the third anode structure 311 and the third cathode structure 313.
  • the third anode structure 311 is connected to the third pixel through the via hole.
  • the circuit is electrically connected.
  • the third anode structure 311 may include a plurality of anode sub-layers, such as a three-layer structure of ITO/Ag/ITO (not shown in the figure), etc.
  • the specific form of the third anode structure 311 is not described in the embodiment of the present disclosure. limited.
  • the third pixel circuit includes structures such as a thin film transistor 32 and a storage capacitor 33.
  • the thin film transistor 32 includes an active layer 331, a gate 332, and source and drain electrodes (ie, a source 233 and a drain 234)
  • the storage capacitor 33 includes a first capacitor plate 331 and a second capacitor plate 332.
  • the active layer 321 is provided on the base substrate 14, the side of the active layer 321 away from the base substrate 14 is provided with a first gate insulating layer 141, and the gate 322 and the first capacitor plate 331 are provided in the same layer.
  • the side of the first gate insulating layer 141 away from the base substrate 14 and the side of the gate 322 and the first capacitor plate 331 away from the base substrate 14 are provided with a second gate insulating layer 142, and the second capacitor plate 332 It is arranged on the side of the second gate insulating layer 142 away from the base substrate 14, and the side of the second capacitor plate 332 away from the base substrate 14 is provided with an interlayer insulating layer 143, and the source and drain electrodes are arranged on the interlayer insulating layer.
  • the side of the 143 away from the base substrate 14 is electrically connected to the active layer 321 through the via holes in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143.
  • the source and drain electrodes are away from the liner.
  • a planarization layer 144 is provided on one side of the base substrate 14 to planarize the third pixel circuit.
  • the planarization layer 144 has a via hole 144B, and the third anode structure 311 is electrically connected to the source electrode 323 of the thin film transistor 32 through the via hole 144B in the insulating layer 145.
  • transition layer there may be a transition layer (not shown in the figure) between the source electrode 323 and the second anode structure 311, and the transition layer may be provided in the same layer as the first connection trace 15.
  • the first pixel circuit and the second pixel circuit in the second display area 20 are arranged in the same layer as the third pixel circuit in the third display area 30, so the same patterning process can be used in the manufacturing process.
  • the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the planarization layer 144 are arranged in the same layer in the second display area 20 and the third display area 30. In some embodiments It is still integrally connected, so the same reference numerals are used in the drawings.
  • the first display area 10 further includes a transparent support layer 18 on the base substrate 14, and the first light emitting device 11 is located on the transparent support layer 18.
  • the transparent support layer 18 is provided in the same layer as at least one of the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the planarization layer 144.
  • the transparent support layer 18 is disposed in the same layer as the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the planarization layer 144, so that the first light emitting device 11 in the first display area 10 It is substantially the same height as the second light emitting device 21 in the second display area 20 and the third light emitting device 31 in the third display area 30, and the manufacturing process of the display substrate is simplified.
  • the display substrate further includes a pixel defining layer 146, an encapsulation layer 147 and other structures.
  • the pixel defining layer 146 is disposed on the first anode structure and includes a plurality of openings, and the first light-emitting layer is formed on the pixel defining layer.
  • the encapsulation layer 147 may include a single-layer or multi-layer encapsulation structure.
  • the multilayer encapsulation structure includes, for example, a stack of an inorganic encapsulation layer and an organic encapsulation layer, thereby improving the encapsulation effect on the display substrate.
  • the pixel defining layer 146 and the encapsulation layer 147 are arranged in the same layer, and in some embodiments, they are integrally connected. The same label is used in.
  • the base substrate 14 may be a glass substrate, a quartz substrate, a metal substrate, a resin substrate, or the like.
  • the embodiments of the present disclosure do not limit this.
  • the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143 and the planarization layer 144, the insulating layer 145, the pixel defining layer 146, the encapsulation layer 147, and the insulating layer 148 may include silicon oxide, Inorganic insulating materials such as silicon nitride and silicon oxynitride, or may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenol resin.
  • the embodiments of the present disclosure do not specifically limit the materials of the above-mentioned functional layers.
  • the material of the active layer may include semiconductor materials such as polysilicon or oxide semiconductor (for example, indium gallium zinc oxide).
  • the part of the active layer 121/221/321 may be conductive through a conductive process such as doping, so as to have higher conductivity.
  • the materials of the grid, the first capacitor plate, and the second capacitor plate may include metal materials or alloy materials, such as molybdenum, aluminum, and titanium.
  • the material of the source and drain electrodes may include metal materials or alloy materials, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, etc.
  • the multi-layer structure is a multi-metal laminated layer, such as titanium, aluminum, Titanium three-layer metal laminate (Ti/Al/Ti), etc.
  • the display substrate provided by the embodiment of the present disclosure may be a display substrate such as an organic light emitting diode (OLED) display substrate or a quantum dot light emitting diode (QLED) display substrate, and the embodiment of the present disclosure does not limit the specific type of the display substrate.
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • the light-emitting layer 111/211/311 may include small molecular organic materials or polymer molecular organic materials, may be fluorescent light-emitting materials or phosphorescent light-emitting materials, and may emit red light or green light. Light, blue light, or white light, etc.
  • the light-emitting layer 111/211/311 may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light-emitting layer 111/211/311 may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots Dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc.
  • the particle size of the quantum dots is 2-20nm.
  • the first display area 10 may have various shapes such as a circle (the situation shown in FIG. 3), a rectangle, a triangle, etc.
  • the shape of the first display area 10 in the embodiment of the present disclosure is different. Make a limit.
  • the display substrate may further include a sensor 19, such as an image sensor, an infrared sensor, a distance sensor, etc.
  • the sensor 19 may be implemented in the form of a chip or the like, for example.
  • the sensor 19 is arranged on the second side of the display substrate, for example, the sensor 19 is arranged on the second side of the display panel by means of double-sided tape, and the orthographic projection of the sensor 19 on the base substrate 14 is at least the same as that of the first display area 10. Partially overlapped and configured to receive light from the first side. Therefore, the first display area 10 provides convenience for the setting of the sensor 19 while realizing display.
  • At least one embodiment of the present disclosure also provides a method for preparing a display substrate having a first side (display side) for display and a second side (non-display side or back side) opposite to the first side,
  • the preparation method includes: forming a display area, and forming at least one first connecting wire in the first display area and the second display area.
  • the display area includes a first display area and a second display area at least partially surrounding the first display area.
  • the first display area allows light from the first side to be at least partially transmitted to the second side.
  • the first connection trace includes a first portion located in the first display area and a second portion located in the second display area that are electrically connected to each other, the first portion includes a first light-transmitting wiring layer, and the second portion includes a metal wiring layer.
  • forming the display area further includes: forming a plurality of first sub-pixels arranged in an array in the first display area, each of the first sub-pixels includes a first light-emitting device, and is located in the second display area.
  • a plurality of first pixel circuits are formed, at least one of the first connection traces includes a plurality of first connection traces; the plurality of first pixel circuits are respectively electrically connected to the first sub-pixels of the plurality of first sub-pixels through the plurality of first connection traces.
  • a light-emitting device for driving the first light-emitting device of a plurality of first sub-pixels.
  • forming the second part of the first connection trace further includes: forming a second light-transmitting wiring layer layered with the metal wiring, and the second light-transmitting wiring layer is connected to the first light-transmitting wiring layer.
  • the wiring layer is formed on the same layer and connected integrally.
  • the preparation method of the display substrate further includes: providing a base substrate.
  • forming the second part of the first connection trace further includes: forming an oxidation protection layer laminated with the metal trace.
  • the second light-transmitting wiring layer is formed on the base substrate, the metal wiring layer is formed on the side of the second light-transmitting wiring layer away from the base substrate, and the anti-oxidation protection layer is formed on the metal wiring layer away from the substrate One side of the substrate.
  • a patterning process is used on the base substrate 14 to simultaneously form the pixel circuits in the second display area 20 and the third display area 30 (including the first pixel circuit, the second pixel circuit, and the third pixel circuit). ), and at the same time form a transparent support layer 18.
  • forming the first pixel circuit includes forming a thin film transistor 12 and a storage capacitor 13.
  • the thin film transistor 12 includes an active layer 121, a gate 122, and source and drain electrodes 123 and 124;
  • the storage capacitor 13 includes a first capacitor plate 131 and a second capacitor plate 132.
  • the active layer 121 is formed on the base substrate 14, a first gate insulating layer 141 is formed on the side of the active layer 121 away from the base substrate 14, and the same layer is formed on the first gate insulating layer 141.
  • the gate 122 and the first capacitor plate 131 are formed.
  • a second gate insulating layer 142 is formed on the side of the gate 122 and the first capacitor plate 131 away from the base substrate 14, and the second gate insulating layer 142 is away from the liner.
  • a second capacitor plate 132 is formed on one side of the base substrate 14, an interlayer insulating layer 143 is formed on the side of the second capacitor plate 132 away from the base substrate 14, and on the side of the interlayer insulating layer 143 away from the base substrate 14
  • Source and drain electrodes 123 and 124 are formed on one side, and the source and drain electrodes 123 and 124 are electrically connected to the active layer 121 through vias in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143, and then
  • a planarization layer 144 is formed on the side of the source and drain electrodes 123 and 124 away from the base substrate 14.
  • the transparent support layer 18 is formed in the same layer as at least one of the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the planarization layer 144.
  • the transparent support layer 18 is formed in the same layer as the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the planarization layer 144.
  • each of the above-mentioned functional layers is formed by a patterning process.
  • One patterning process includes, for example, photoresist formation, exposure, development, and etching.
  • a buffer layer (not shown in the figure) may also be formed on the base substrate 14.
  • the buffer layer serves as a transition layer to prevent harmful substances in the base substrate 14 from intruding into the display.
  • the inside of the substrate can also increase the adhesion of the film layer in the display substrate on the base substrate 14.
  • the material of the buffer layer may include a single-layer or multi-layer structure formed of insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • first connecting wires are formed in the first display area 10 and the second display area 20.
  • a light-transmitting wiring material layer 151, a metal wiring material layer 161, and a conductive protective material layer 171 are sequentially deposited on the first display area 10 and the second display area 20 through the mask 40.
  • the mask plate 40 has a hollow part (ie, the white part in the figure), so that the material passes through the hollow part to form a certain pattern.
  • the transparent wiring material layer 151, the metal wiring material layer 161, and the conductive protective material layer 171 deposited through the mask 40 have substantially the same pattern.
  • the first connection trace 15 including the first portion 15A and the second portion 15B is formed. Since the dry etching method is easy to control and can precisely control the etching thickness of the metal wiring material layer 161 and the conductive protective material layer 171, the first connection wiring 15 can be formed by a dry etching method once.
  • the metal wiring material layer 161, and the conductive protective material layer 171 are sequentially deposited on the first display area 10 and the second display area 20 through the mask 40 .
  • a wet etching method may be used to etch away the metal wiring material layer 161 and the conductive protective material layer 171 located in the first display area 10.
  • the etching thickness is not easy to control.
  • over-etching is generally used. At this time, as shown in FIG.
  • the portion of the light-transmitting wiring material layer 151 located in the first display area 10 may be partially etched, in order to ensure the thickness and the thickness of the light-transmitting wiring material layer 151 in the first display area 10 Connectivity with the light-transmitting wiring material layer 151 in the second display area 20, after the above-mentioned wet etching, another layer can be deposited in the first display area 10 and the second display area 20 through the mask 40
  • the light-transmitting wiring material layer is used to increase the thickness of the light-transmitting wiring layer in the first display area 10.
  • the light-transmitting wiring material layer will also be formed on the right side of the metal wiring material layer 161, as shown in FIG. Shown in 18B.
  • the light-transmitting wiring material layer 151 and the conductive protective material layer 171 can be made of the same material, for example, ITO is used, in FIG. 18B, the light-transmitting wiring material layer 151 and the conductive protective material layer 171 is shown as an integrally connected structure.
  • basically the same method can also be used to form the display substrates shown in FIGS. 7 and 8.
  • the light-transmitting wiring material layer 151, the metal wiring material layer 161, and the conductive material are sequentially deposited on the first display area 10 and the second display area 20 through the mask 40.
  • a dry etching method can be used to etch away part of the metal wiring material layer 161 and the conductive protective material layer 171 in the first display area 10 to form the first connection wiring 15 and the first connection wiring 15 and the first connection wiring 15 in the same layer.
  • Anode structure 111 the material of the light-transmitting wiring material layer 151 may be ITO
  • the material of the metal wiring material layer 161 may be Ag
  • the conductive protective material layer 171 may be ITO.
  • a patterning process may be used to first form the metal wiring layer of the second portion 15B, then form an insulating layer 148 on the metal wiring layer, and form vias in the insulating layer 148 . After that, a patterning process is used to form the first light-transmitting wiring layer of the first portion 15A on the insulating layer 148.
  • the first light-transmitting wiring layer is electrically connected to the second portion 15B through the vias formed in the insulating layer 148, thereby forming
  • the first connecting trace includes the first part 15A and the second part 15B.
  • the preparation method of the display substrate further includes forming a pixel defining layer, a light emitting device, and an encapsulation layer on the first connection trace 15.
  • a pixel defining layer for example, a pixel defining layer, a light emitting device, and an encapsulation layer on the first connection trace 15.
  • the preparation method of the display substrate may further include: providing a sensor and bonding the sensor to the second side of the display substrate.
  • the orthographic projection of the sensor on the base substrate at least partially overlaps the first display area, so that the light from the first side can be received through the first display area.
  • the first display area has a relatively high light transmittance, and therefore, it is possible to facilitate the setting of the sensor while realizing display.
  • the first connection traces located in the first display area and the second display area have lower resistance, which can increase the signal transmission speed of the first connection traces; when multiple first connection traces are used as the first connection trace
  • the current flowing through the plurality of first connecting wires 15 has a higher uniformity, which can further improve the display effect of the display substrate.

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Abstract

一种显示基板及其制备方法。该显示基板具有用于显示的第一侧和与第一侧相对的第二侧，显示基板包括显示区域，显示区域包括第一显示区域（10）以及至少部分围绕第一显示区域（10）的第二显示区域（20），第一显示区域（10）允许来自第一侧的光至少部分透射至第二侧；显示基板还包括在第一显示区域（10）和第二显示区域（20）中的至少一条第一连接走线（15），第一连接走线（15）包括彼此电连接的位于第一显示区域（10）的第一部分（15A）和位于第二显示区域（20）的第二部分（15B），第一部分（15A）包括第一透光走线层，第二部分（15B）包括金属走线层。该显示基板中的第一连接走线（15）具有较低的电阻。

Description

显示基板及其制备方法 技术领域
本公开的实施例涉及一种显示基板及其制备方法。
背景技术
目前，用于电子装置的显示屏正往大屏化、全屏化方向发展，以使用户具有更好的视觉体验。以手机、平板电脑等电子产品为例，由于这些电子装置需要结合摄像头、光线传感器等部件，而这些部件通常占据显示屏的显示区，由此导致显示屏难以实现全屏化设计。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板具有用于显示的第一侧和与所述第一侧相对的第二侧，所述显示基板包括显示区域，其中，所述显示区域包括第一显示区域以及至少部分围绕所述第一显示区域的第二显示区域，所述第一显示区域允许来自所述第一侧的光至少部分透射至所述第二侧；所述显示基板还包括在所述第一显示区域和所述第二显示区域中的至少一条第一连接走线，其中，所述第一连接走线包括彼此电连接的位于第一显示区域的第一部分和位于第二显示区域的第二部分，所述第一部分包括第一透光走线层，所述第二部分包括金属走线层。
例如，本公开至少一实施例提供的显示基板中，所述第一显示区域包括阵列排布的多个第一子像素，每个第一子像素包括第一发光器件，所述至少一条第一连接走线包括多条第一连接走线；所述第二显示区域包括多个第一像素电路，所述多个第一像素电路分别通过所述多条第一连接走线电连接所述多个第一子像素的第一发光器件，以用于驱动所述多个第一子像素的第一发光器件。
例如，本公开至少一实施例提供的显示基板中，所述第二部分还包括与所述金属走线层叠层的第二透光走线层，所述第二透光走线层与所述第一透光走线层同层设置且一体连接。
例如，本公开至少一实施例提供的显示基板中，所述第二部分还包括与 所述金属走线层叠层的防氧化保护层，所述显示基板包括衬底基板，所述第二透光走线层位于所述衬底基板上，所述金属走线层位于所述第二透光走线层的远离所述衬底基板的一侧，所述防氧化保护层位于所述金属走线层的远离所述衬底基板的一侧。
例如，本公开至少一实施例提供的显示基板中，所述金属走线层的材料包括Ag、Al、Mo或Ti；所述防氧化保护层的材料包括透明氧化物。
例如，本公开至少一实施例提供的显示基板中，所述第一发光器件包括第一阳极结构、第一阴极结构以及在所述第一阳极结构与所述第一阴极结构之间的第一发光层，所述第一部分通过过孔与所述第一阳极结构电连接。
例如，本公开至少一实施例提供的显示基板中，所述第二显示区域还包括多个第二子像素，每个第二子像素包括第二发光器件以及与所述第二发光器件电连接的第二像素电路，所述第二像素电路配置为驱动所述第二发光器件，在所述第二显示区域中，所述多个第二像素电路呈第一阵列排布。
例如，本公开至少一实施例提供的显示基板中，在所述第二显示区域中，所述多个第一像素电路设置在所述第一阵列中，并与所述多个第二像素电路排布为第二阵列。
例如，本公开至少一实施例提供的显示基板中，所述第二发光器件包括第二阳极结构、第二阴极结构以及所述第二阳极结构与所述第二阴极结构之间的第二发光层，所述第二阳极结构通过过孔与所述第二像素电路电连接。
例如，本公开至少一实施例提供的显示基板中，所述显示区域还包括至少部分围绕所述第二显示区的第三显示区域，所述第三显示区域包括阵列排布的多个第三子像素，每个第三子像素包括第三发光器件以及与所述第三发光器件电连接的第三像素电路，所述第三像素电路配置为驱动所述第三发光器件，所述第三发光器件包括第三阳极结构、第三阴极结构以及所述第三阳极结构与所述第三阴极结构之间的第三发光层，所述第三阳极结构通过过孔与所述第三像素电路电连接。
例如，本公开至少一实施例提供的显示基板中，所述显示基板包括衬底基板，所述第一显示区域还包括位于所述衬底基板上的透明支撑层，所述第一发光器件位于所述透明支撑层的远离所述衬底基板的一侧。
例如，本公开至少一实施例提供的显示基板中，所述第一像素电路包括薄膜晶体管和存储电容，所述薄膜晶体管包括有源层、栅极和源漏电极；所 述存储电容包括第一电容极板和第二电容极板，所述有源层设置在所述衬底基板上，所述有源层的远离所述衬底基板的一侧设置有第一栅绝缘层，所述栅极和所述第一电容极板同层设置在所述第一栅绝缘层的远离所述衬底基板的一侧，所述栅极和所述第一电容极板的远离所述衬底基板的一侧设置有第二栅绝缘层，所述第二电容极板设置在所述第二栅绝缘层的远离所述衬底基板的一侧，所述第二电容极板的远离所述衬底基板的一侧设置有层间绝缘层，所述源漏电极设置在所述层间绝缘层的远离所述衬底基板的一侧，并通过所述第一栅绝缘层、所述第二栅绝缘层和所述层间绝缘层中的过孔与所述有源层电连接，所述源漏电极的远离所述衬底基板的一侧设置有平坦化层；所述透明支撑层与所述第一栅绝缘层、所述第二栅绝缘层、所述层间绝缘层和所述平坦化层中的至少一种同层设置。
例如，本公开至少一实施例提供的显示基板还包括传感器，其中，所述传感器设置于所述显示基板的第二侧，并且所述传感器在所述衬底基板上的正投影与所述第一显示区域至少部分重叠，配置为接收所述来自所述第一侧的光。
本公开至少一实施例提供一种显示基板的制备方法，所述显示基板具有用于显示的第一侧和与所述第一侧相对的第二侧，所述制备方法包括：形成显示区域，所述显示区域包括第一显示区域以及至少部分围绕所述第一显示区域的第二显示区域，所述第一显示区域允许来自所述第一侧的光至少部分透射至所述第二侧；在所述第一显示区域和所述第二显示区域中形成至少一条第一连接走线，其中，所述第一连接走线包括彼此电连接的位于第一显示区域的第一部分和位于第二显示区域的第二部分，所述第一部分包括第一透光走线层，所述第二部分包括金属走线层。
例如，本公开至少一实施例提供的显示基板的制备方法中，形成所述显示区域还包括：在所述第一显示区域中形成阵列排布的多个第一子像素，每个第一子像素包括第一发光器件，在所述第二显示区域中形成多个第一像素电路，其中，所述至少一条第一连接走线包括多条第一连接走线；所述多个第一像素电路分别通过所述多条第一连接走线电连接所述多个第一子像素的第一发光器件，以用于驱动所述多个第一子像素的第一发光器件。
例如，本公开至少一实施例提供的显示基板的制备方法中，形成所述第一连接走线的第二部分还包括：形成与所述金属走线层叠层的第二透光走线 层，其中，所述第二透光走线层与所述第一透光走线层同层形成且一体连接。
例如，本公开至少一实施例提供的显示基板的制备方法还包括：提供衬底基板，其中，形成第一连接走线的第二部分还包括：形成与所述金属走线层叠层的防氧化保护层，其中，所述第二透光走线层形成于所述衬底基板上，所述金属走线层形成于所述第二透光走线层的远离所述衬底基板的一侧，所述防氧化保护层形成于所述金属走线层的远离所述衬底基板的一侧。
例如，本公开至少一实施例提供的显示基板的制备方法中，形成所述第一连接走线包括：通过掩膜板在所述第一显示区域和所述第二显示区域依次沉积透光走线材料层、金属走线材料层以及导电保护材料层；使用干刻蚀法刻蚀掉位于所述第一显示区域的金属走线材料层以及导电保护材料层。
例如，本公开至少一实施例提供的显示基板的制备方法中，形成所述第一连接走线包括：通过掩膜板在所述第一显示区域和所述第二显示区域依次沉积透光走线材料层、金属走线材料层以及导电保护材料层；使用湿刻蚀法刻蚀掉位于所述第一显示区域的金属走线材料层以及导电保护材料层；通过所述掩膜板在所述第一显示区域和所述第二显示区域再沉积一层透光走线材料层。
例如，本公开至少一实施例提供的显示基板的制备方法中，形成所述第一像素电路包括形成薄膜晶体管和存储电容，所述薄膜晶体管包括有源层、栅极和源漏电极；所述存储电容包括第一电容极板和第二电容极板，其中，所述有源层形成在所述衬底基板上，在所述有源层的远离所述衬底基板的一侧形成第一栅绝缘层，所述栅极和所述第一电容极板同层形成在所述第一栅绝缘层的远离所述衬底基板的一侧，在所述栅极和所述第一电容极板的远离所述衬底基板的一侧形成第二栅绝缘层，所述第二电容极板形成在所述第二栅绝缘层的远离所述衬底基板的一侧，在所述第二电容极板的远离所述衬底基板的一侧形成层间绝缘层，所述源漏电极形成在所述层间绝缘层的远离所述衬底基板的一侧，并通过所述第一栅绝缘层、所述第二栅绝缘层和所述层间绝缘层中的过孔与所述有源层电连接，在所述源漏电极的远离所述衬底基板的一侧形成平坦化层；形成所述第一显示区域还包括：在所述衬底基板与所述第一发光器件之间形成透明支撑层，其中，所述透明支撑层与所述第一栅绝缘层、所述第二栅绝缘层、所述层间绝缘层中和所述平坦化层中的至少一种同层形成。
例如，本公开至少一实施例提供的显示基板的制备方法还包括：提供传感器，并将所述传感器结合于所述显示基板的第二侧，其中，所述传感器在所述衬底基板上的正投影与所述第一显示区域至少部分重叠，配置为接收所述来自所述第一侧的光。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种显示基板的平面示意图；
图1B为一种显示基板的局部放大示意图；
图2为图1B中的显示基板沿A-A线的截面示意图；
图3为本公开至少一实施例提供的一种显示基板的平面示意图；
图4为图3中的显示基板沿B-B线的截面示意图；
图5为本公开至少一实施例提供的一种显示基板中第一显示区域和第二显示区域的平面示意图；
图6为图3中的显示基板沿B-B线的另一截面示意图；
图7为图3中的显示基板沿B-B线的另一截面示意图；
图8为图3中的显示基板沿B-B线的另一截面示意图；
图9为本公开至少一实施例提供的一种显示基板中第一显示区域和第二显示区域的另一平面示意图；
图10为本公开至少一实施例提供的一种显示基板中第一显示区域和第二显示区域的再一平面示意图；
图11为本公开至少一实施例提供的一种显示基板的显示区域中子像素排布的平面示意图；
图12为本公开至少一实施例提供的一种显示基板的显示区域中走线排布的平面示意图；
图13为本公开至少一实施例提供的一种显示基板的显示区域中走线排布的另一平面示意图；
图14为本公开至少一实施例提供的一种显示基板中第一显示区域和第二显示区域的再一平面示意图；
图15为本公开至少一实施例提供的一种显示基板中第二显示区域的截面示意图；
图16为本公开至少一实施例提供的一种显示基板中第三显示区域的截面示意图；
图17A-图17B为本公开至少一实施例提供的一种显示基板在制备过程中的截面示意图；以及
图18A-图18B为本公开至少一实施例提供的一种显示基板在制备过程中的截面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了实现显示屏的全屏化设计，在一些实施方式中，可以将用于安装传感器(例如图像传感器、红外传感器)等部件的部分显示区设计为透光显示区，由此该透光显示区可以在实现显示功能的同时，为安装传感器等部件提供便利。
例如，图1A示出了一种显示基板的平面示意图，图1B为图1A示出的的显示基板的局部放大示意图，图2示出了图1B中的显示基板沿A-A线的截面示意图。如图1A、图1B和图2所示，该显示基板的显示区包括透光显 示区1、周边显示区2以及主体显示区3。
例如，主体显示区3为主要的显示区域，具有较高的分辨率(PPI，Pixel Per Inch)，即主体显示区3内排布有密度较高的用于显示的子像素。每个子像素包括发光器件以及驱动发光器件的像素电路。透光显示区1可以允许从显示基板显示侧射入的光透过显示基板而到达显示基板的背侧，从而用于位于显示基板背侧的传感器等部件的正常工作。透光显示区1和周边显示区2也包括多个子像素，以用于显示。但是，由于子像素的像素电路通常不透光，为了保证透光显示区1的透光性，透光显示区1中子像素(例如图1B中透光显示区1内的方框所示)的像素电路可以设置在周边显示区2，如周边显示区2中的灰色方框所示，因此占据了周边显示区2的部分空间，而周边显示区2的剩余空间用于设置周边显示区2的子像素，例如周边显示区2中的每一个白色方框代表一个子像素。此时，周边显示区2的子像素(图1B中的白色方框)以及透光显示区1中子像素的像素电路(图1B中的灰色方框)在周边显示区2中排布为阵列。由此，透光显示区1和周边显示区2的分辨率低于主体显示区3的分辨率，即透光显示区1和周边显示区2内排布的用于显示的子像素的密度小于主体显示区3的子像素密度。
如图2所示，透光显示区1中的一个子像素的发光器件4包括阳极4A、阴极4C以及在阳极4A和阴极4C之间的发光层4B，阳极4A通过导电引线连接至周边显示区2中的像素电路5。
具体实施例中，导电引线可以是金属引线，例如可以和子像素的像素电路中源漏电极金属采用相同材料，也可以是透明走线(例如ITO走线)6电连接至周边显示区2中的像素电路5，从而位于周边显示区2的像素电路5可用于驱动位于透光显示区1的发光器件4。由于透明走线6具有较高的透光性，因此可保证透光显示区1也具有较高的透光性。由此，设置于显示基板背侧的传感器7等部件可以通过透光显示区1接收到从显示基板显示侧透过的光，以进行正常工作。
在上述情况下，透明走线6需要从周边显示区2的像素电路5延伸至透光显示区1的发光器件4，因此至少部分透明走线6的长度较长，例如其长度会跨过多于2个子像素区域的距离，另一方面，相比于源漏电极材料，如Ti/Al/Ti，或者任意一者，或者两者的组合；或者其他电极材料，如铜、钼、镁、银或者至少两种材料的组合等。透明走线6所采用的材料本身电阻也较 大，并且其制备工艺容易产生偏差，使得透明走线6的整体电阻较大，因此像素电路5向透光显示区1中的子像素传输电信号的速度较慢，导致透光显示区1中的子像素与周边显示区2和主体显示区3中的子像素的驱动不同步，影响显示区的显示效果。
本公开至少一实施例提供一种显示基板及其制备方法，该显示基板具有用于显示的第一侧和与第一侧相对的第二侧，显示基板包括显示区域，显示区域包括第一显示区域以及至少部分围绕第一显示区域的第二显示区域，第一显示区域允许来自第一侧的光至少部分透射至第二侧；显示基板还包括在第一显示区域和第二显示区域中的至少一条第一连接走线，第一连接走线包括彼此电连接的位于第一显示区域的第一部分和位于第二显示区域的第二部分，第一部分包括第一透光走线层，第二部分包括金属走线层。该显示基板中的第一连接走线具有较低的电阻。
下面通过几个具体的实施例对本公开一些实施例的显示基板及其制备方法进行说明。
本公开至少一实施例提供一种显示基板，图3示出了该显示基板的平面示意图，图4示出了图3中的显示基板沿B-B线的截面示意图。
如图3和图4所示，该显示基板具有用于显示的第一侧(图4中示出为显示基板的上侧，也即显示基板的显示侧)和与第一侧相对的第二侧(图4中示出为显示基板的下侧)。该显示基板包括显示区域，该显示区域包括第一显示区域10以及至少部分围绕第一显示区域10的第二显示区域20，第一显示区域10允许来自第一侧的光至少部分透射至第二侧，即第一显示区域10至少部分透光，以便于图像传感器、红外传感器等部件的安装。
如图4所示，显示基板还包括在第一显示区域10和第二显示区域20中的至少一条第一连接走线15，第一连接走线15包括彼此电连接的位于第一显示区域10的第一部分15A和位于第二显示区域20的第二部分15B，第一部分15A包括第一透光走线层，第二部分15B包括金属走线层。
例如，第一透光走线层的材料可以为透明导电材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)等透明金属氧化物，金属走线层的材料可以包括银(Ag)、铝(Al)、钼(Mo)或钛(Ti)等金属材料或其合金材料。由于金属走线层的电阻较低，因此相比于只包括透光走线层的走线来说，第一连接走线15可具有较低的电阻。
例如，图5示出了一种第一显示区域10和第二显示区域20的平面示意图。如图5所示，在一些实施例中，第一显示区域10包括阵列排布的多个第一子像素，每个第一子像素包括第一发光器件11，显示区域包括多条第一连接走线15，第二显示区域20包括多个第一像素电路D，多个第一像素电路D分别通过多条第一连接走线15电连接多个第一子像素的第一发光器件11，以用于驱动多个第一子像素的第一发光器件11。
例如，在图5示出的实施例中，多个第一像素电路D与多个第一子像素的第一发光器件11一一对应且通过第一连接走线15电连接，此时，一个第一像素电路D用于驱动一个第一子像素的第一发光器件11。例如，在另一些实施例中，也可以是一个第一像素电路D分别通过多条第一连接走线15与多个第一子像素的第一发光器件11电连接，此时，一个第一像素电路D可用于驱动多个第一子像素的第一发光器件11。本公开的实施例对第一像素电路D和第一子像素的第一发光器件11的对应关系不做具体限定。
例如，在一些实施例中，如图4所示，第一连接走线15的第一部分15A包括第一透光走线层，第一连接走线15的第二部分15B包括金属走线层16以及与金属走线层16叠层的第二透光走线层15C，第二透光走线层15C与第一透光走线层同层设置且一体连接，即第二透光走线层15C与第一透光走线层同层设置且直接接触，从而形成一体结构。
需要注意的是，在本公开的实施例中，“同层设置”为两个功能层或结构层在显示基板的层级结构中同层且同材料形成，即在制备工艺中，该两个功能层或结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构。一次构图工艺例如包括光刻胶的形成、曝光、显影、刻蚀等工序。
例如，在一些实施例中，如图4所示，第一连接走线15的第二部分15B还可以包括与金属走线层16叠层的防氧化保护层17，防氧化保护层17可以防止金属走线层16氧化，以保证金属走线层16维持较高的导电性能；另外，防氧化保护层17还可以增强金属走线层16与其上形成的绝缘层145的粘结性，以防止金属走线层16与绝缘层145连接不良。例如，在一些实施例中，防氧化保护层17可以采用透明氧化物材料，例如ITO、IZO等透明导电氧化物材料，由此还可以进一步降低第一连接走线15的电阻。
例如，如图4所示，显示基板包括衬底基板14，第二透光走线层15C 位于衬底基板14上，金属走线层16位于第二透光走线层15C的远离衬底基板14的一侧，防氧化保护层17位于金属走线层16的远离衬底基板14的一侧。由此，第一连接走线15的第二部分15B形成为三层叠层的导电结构，该三层叠层的导电结构可显著降低第一连接走线15的电阻。当多条第一连接走线15分别用于为多个第一发光器件11传输驱动信号时，第一连接走线15的上述设计还可提高流经多条第一连接走线15的电流均一性，进而提高显示基板的显示效果。
例如，在图4示出的实施例中，第二透光走线层15C与防氧化保护层17间隔设置，没有接触。在另一些实施例中，由于制备工艺的不同，如图6所示，第二透光走线层15C与防氧化保护层17可以物理连接，即在图6示出的实施例中，防氧化保护层17还覆盖在金属走线层16的右侧，从而与第二透光走线层15C物理接触。该实施例提供的三层导电结构也可显著降低第一连接走线15的电阻。
例如，在一些实施例中，如图4和图6所示，第一发光器件11包括第一阳极结构111、第一阴极结构113以及在第一阳极结构111与第一阴极结构113之间的第一发光层112，第一连接走线15的第一部分15A通过过孔与第一阳极结构111电连接。例如，第一连接走线15上设置有绝缘层145，绝缘层145在第一显示区域10中具有过孔145A，第一连接走线15的第一部分15A通过绝缘层145中的过孔145A与第一阳极结构111电连接。
例如，在一些实施例中，第一阳极结构111包括多层阳极子层，例如图中示出为三层阳极子层。例如，该三层阳极子层为ITO/Ag/ITO三层叠层结构。例如，第一阴极结构113可以为显示基板上整面形成的结构，第一阴极结构113例如可以包括锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。由于第一阴极结构113可以形成为很薄的一层，因此第一阴极结构113具有良好的透光性。
例如，在另一些实施例中，第一连接走线15和第一阳极结构111也可以采用与图4和图6不同的设计。例如，如图7所示，第一连接走线15的第一部分15A可以与第一阳极结构111所包括的多层阳极子层中的底层阳极子层(例如ITO层)同层设置且一体连接。另外，第一连接走线15的第二部分15B所包括的第二透光走线15C可以与第一部分15A同层设置且一体连接，第二部分15B所包括的金属走线层16与第一阳极结构111所包括的 多层阳极子层中的中间层阳极子层(例如Ag层)同层设置，第二部分15B所包括的防氧化保护层17与第一阳极结构111所包括的多层阳极子层中的顶层阳极子层(例如ITO层)同层设置。由此可以简化显示基板的制备工艺。例如，相比于图4和图6所示的显示基板来说，图7中示出的显示基板可以采用相同的构图工艺同时形成第一连接走线15和第一阳极结构111，从而减少单独的第一连接走线1的制备工艺以及绝缘层145的制备工艺。
例如，在另一些实施例中，第一连接走线15也可以采用与图4、图6和图7均不同的设计。例如，如图8所示，第一连接走线的第一部分15A为第一透光走线层，第二部分15B为金属走线层，第一部分15A和第二部分15B通过过孔电连接。例如，第二部分15B上设置有绝缘层148，绝缘层148在第二显示区域20中具有过孔148A，第一部分15A和第二部分15B通过绝缘层148中的过孔148A电连接。
例如，图9示出了一种在上述情况下第一显示区域10和第二显示区域20的平面图。例如，如图9所示，第二显示区域20的靠近第一显示区域10的位置处具有过孔区(虚线框框出的区域)，多条第一连接走线15的第一部分15A和第二部分15B可以分别通过在该过孔区内设置的多个过孔148A进行电连接。在该实施例中，通过第二部分15B的金属走线层的设计，第一连接走线15仍可具有较低的电阻。
例如，在一些实施例中，如图5所示，第二显示区域20还包括多个第二子像素P，每个第二子像素P包括第二发光器件以及与第二发光器件电连接的第二像素电路，第二像素电路配置为驱动第二发光器件；在第二显示区域20中，多个第二像素电路呈第一阵列排布，即图5中灰色方格所排布的阵列。
例如，在一些实施例中，在第二显示区域20中，多个第一像素电路D分散设置在第一阵列中，并与多个第二像素电路D排布为第二阵列，即图5中灰色方格和白色方格共同排布的阵列。
例如，图10示出了另一种第一显示区域10和第二显示区域20的平面图。如图10所示，在一些实施例中，第一连接走线15可以跨过第二显示区域20中的第二子像素P以电连接位于第一显示区域10的第一发光器件11(例如包括阳极、发光层、阴极)以及位于第二显示区域20的用于驱动该第一发光器件11第一像素电路D(例如包括驱动晶体管、存储电容等)。例 如，在图10示出的实施例中，第一连接走线15可以呈直线形电连接位于第一显示区域10的第一发光器件11以及位于第二显示区域20的用于驱动该第一发光器件11的第一像素电路D。例如，用于驱动第一显示区域10中第一子像素的数据线D(例如D1、D2)可以在第二显示区域20的靠近第一显示区域10的边界处绕线排布。
例如，位于同一列的子像素的像素电路可以电连接同一数据线，由此位于同一列的子像素的发光器件可以由相同的数据线驱动。例如，在图10示出的实施例中，左侧的数据线D1通过绕线电连接第一显示区域10中左侧第一列子像素的像素电路，右侧的数据线D2电连接第一显示区域10中左侧第二列子像素的像素电路。当然，第一显示区域10中其他列子像素也分别连接一条数据线，图中未示出。
需要说明的是，在本公开的实施例中，列方向指的是图中的竖直方向，行方向指的是图中的水平方向，在其他实施例中，列方向和行方向可以互换，本公开的实施例对此不做限定。
例如，第一显示区域10和第二显示区域20之间存在布线密集区，如图中的虚线框所示，此时，为了排线方便并节省空间，在一些实施例中，该布线密集区可以采用跳线设计，即将走线排布在不同的走线层中。
例如，图11示出了一种第一显示区域中第一子像素排列的图案。例如，第二显示区域20中的第二子像素也具有如图11所示的子像素排列规律。在该实施例中，每四个子像素构成一个重复单元，每个子像素具有不同的形状，相应地，每个子像素的发光器件的阳极结构也具有不同的形状，对应相同、或者不同颜色的发光器件，例如一个重复单元可以包括GGRB四个子像素。例如，如图11所示，在第一显示区域10的一个像素单元中，每个第一子像素的第一发光器件的第一阳极结构111具有不同的形状，并进行如图11所示的排布以对应用于发出相同、或者不同颜色的光，例如四个第一子像素111可以分别发出绿、绿、红、蓝等不同颜色的光线。
具体实施例中，上述重复单元可以不限于4个，例如可以是R、G、B三个，亦或者可以采取其他排列方式，如RGBG等。
例如，图12示出了第一显示区域10中的第一子像素和第二显示区域20中的第二子像素在进行上述子像素排布的情况下，数据线D的连接方式。如图12所示，数据线D在第二显示区域20的靠近第一显示区域10的边界处 绕线排布，并且在第一显示区域10和第二显示区域20中，位于同一列的子像素的像素电路电连接同一条数据线D。例如，在图12所示的实施例中，用灰色方块示出的位于第二显示区域20中的第一像素电路通过第一连接走线15电连接位于第一显示区域10中的左侧第一个第一子像素的发光器件，通过数据线D的绕线，可以将与左侧第一个第一子像素位于同一列的子像素(无论是第一子像素还是第二子像素)的像素电路均电连接，从而将位于同一列的子像素的像素电路电连接同一数据线。例如，数据线D的一部分DA(图中示出为数据线D上侧水平延伸的粗线部分)可以采用跳线的方式设置，即数据线D的一部分DA可以与数据线D的其他部分设置在不同层中。例如，当数据线D的设置密度较大时，采用跳线设计可以缩减数据线的排布空间，从而更有利于走线的设置。
例如，图12仅示出了第一显示区域10中一个第一子像素的连接走线以及数据线等，第一显示区域10中的其他第一子像素也具有类似的连接关系，图中12未示出。例如，灰色方框所占据的区域可以具有一个像素重复单元中的一个，或者多个第一子像素的第一像素电路，此时，该一个或者多个第一像素电路可分别通过一条或者多条第一连接走线15电连接到第一显示区域10中一个像素重复单元的一个或者多个第一子像素。
例如，灰色方框所占据的区域可以具有一个像素单元的四个第一子像素的第一像素电路，此时，该四个第一像素电路可分别通过四条第一连接走线15电连接到第一显示区域10中一个像素单元的四个第一子像素。
例如，在一些实施例中，数据线D可以在第二显示区域20的一侧绕线，例如图12中示出了在第二显示区域20的上侧绕线的情况。在另一些实施例中，如图13所示，数据线D也可以同时在第二显示区域20的上侧和下侧绕线。
例如，在一些实施例中，数据线D可以在第二显示区域20的像素行之间进行绕线，本实施例不做限制。
例如，如图13所示，在该实施例中，在第一显示区域10和第二显示区域20中的左侧第一列子像素的像素电路采用同一条数据线D3(图中左侧的数据线)电连接，左侧第二列子像素的像素电路采用同一条数据线D4(图中右侧的数据线)电连接，此时，数据线在第二显示区域20的上下两侧同时绕线，以将位于同一列的子像素的像素电路电连接，由此位于同一列的子 像素的发光器件可以由相同的数据线驱动。
类似地，数据线D3和数据线D4的一部分DA也可以采用跳线设计。例如，在第二显示区域20的边缘，数据线的排布较密集，因此在该边缘绕线的部分数据线可以采用跳线设计，以节省空间，并简化电路排布。
类似地，图13仅示出了第一显示区域10中四个第一子像素的连接走线以及数据线等，第一显示区域10中的其他第一子像素也具有类似的连接关系，图中13未示出。例如，灰色方框所占据的区域可以具有一个像素重复单元的四个第一子像素的第一像素电路，此时，该四个第一像素电路可分别通过四条第一连接走线15电连接到第一显示区域10中一个像素单元的四个第一子像素。
例如，如图14所示，位于第一显示区域10左侧第三列的第一子像素与第一显示区域10上方的第二显示区域20中的第二列第二子像素P位于同一列，并且位于第一显示区域10左侧第三列的第一子像素(具体为第一子像素的发光器件，如包括阳极、发光层、阴极)被第一显示区域10上方的第二显示区域20中的第一列中的第一像素电路(如包括驱动晶体管，存储电容等)D驱动，此时，数据线D可以通过在第二显示区域20中的第一列第一像素电路D和第二列第二子像素P中绕线，以将这些位于同一列的子像素的像素电路电连接到同一数据线，由此位于同一列的子像素的发光器件可以由相同的数据线驱动。
例如，位于同一行的子像素的像素电路可以电连接同一扫描线，由此位于同一行的子像素的发光器件可以由相同的扫描线驱动。例如，如图14所示，位于第一显示区域10中第一行第一个第一子像素的第一发光器件11与位于第一显示区域10左侧的第二显示区域20中的一个第一像素电路D电连接，位于第一显示区域10中第一行第二个第一子像素的发光器件11与位于第一显示区域10上侧的第二显示区域20中的一个第一像素电路D电连接，通过扫描线G1(图中左侧的扫描线)的绕线，可以将位于同一行(图中第一行)的这两个第一子像素的第一像素电路D电连接。类似地，位于第一显示区域10中第三行第一个第一子像素的第一发光器件11与位于第一显示区域10左侧的第二显示区域20中的一个第一像素电路D电连接，位于第一显示区域10中第三行第二个第一子像素的发光器件11与位于第一显示区域10上侧的第二显示区域20中的一个第一像素电路D电连接，通过扫描线G2 (图中右侧的扫描线)的绕线，可以将位于同一行(图中第三行)的这两个第一子像素的第一像素电路D电连接。由此，位于同一行的子像素的发光器件可以由相同的扫描线驱动。
由此，在本公开的实施例中，通过扫描线和数据线的绕线，可以将位于同一列的子像素的像素电路电连接同一数据线，将位于同一行的子像素的像素电路电连接同一扫描线，以简化显示面板中各子像素的驱动控制。
例如，在图14中，不同线条的走线分别设置在不同的走线层中，即不同线条的走线异层设置。例如，图中颜色最深且线条最粗的第一连接走线15、颜色较深但线条较细的数据线D以及颜色最浅且线条较细的扫描线G分别设置在不同层，因此在制备工艺中分别采用不同的材料层制作。
例如，如图4所示，用于驱动第一发光器件11的第一像素电路D包括薄膜晶体管12和存储电容13，薄膜晶体管12包括有源层121、栅极122和源漏电极(即源极123和漏极124)等结构，存储电容13包括第一电容极板131和第二电容极板132。
例如，有源层121设置在衬底基板14上，有源层121的远离衬底基板14的一侧设置有第一栅绝缘层141，栅极122和第一电容极板131同层设置在第一栅绝缘层141的远离衬底基板14的一侧，栅极122和第一电容极板131的远离衬底基板14的一侧设置有第二栅绝缘层142，第二电容极板132设置在第二栅绝缘层的远离衬底基板14的一侧，第二电容极板132的远离衬底基板14的一侧设置有层间绝缘层143，源漏电极设置在层间绝缘层143的远离衬底基板14的一侧，并通过第一栅绝缘层141、第二栅绝缘层142和层间绝缘层143中的过孔与有源层121电连接，源漏电极的远离衬底基板14的一侧设置有平坦化层144，以平坦化第一像素电路。
例如，图15示出了一种第二显示区域20的截面示意图，如图15所示，第二显示区域20包括第二发光器件21以及驱动第二发光器件21的第二像素电路。例如，第二像素电路包括薄膜晶体管22和存储电容23等结构。第二发光器件21包括第二阳极结构211、第二阴极结构213以及第二阳极结构211与第二阴极结构213之间的第二发光层212，第二阳极结构211通过过孔与第二像素电路电连接。例如，第二阳极结构211可以包括多个阳极子层，例如包括ITO/Ag/ITO三层结构等(图中未示出)，本公开的实施例对第二阳极结构211的具体形式不做限定。
例如，薄膜晶体管22包括有源层221、栅极222和源漏电极(即源极223和漏极224)等结构，存储电容23包括第一电容极板231和第二电容极板232。例如，有源层221设置在衬底基板14上，有源层221的远离衬底基板14的一侧设置有第一栅绝缘层141，栅极222和第一电容极板231同层设置在第一栅绝缘层141的远离衬底基板14的一侧，栅极222和第一电容极板231的远离衬底基板14的一侧设置有第二栅绝缘层142，第二电容极板232设置在第二栅绝缘层142的远离衬底基板14的一侧，第二电容极板232的远离衬底基板14的一侧设置有层间绝缘层143，源漏电极设置在层间绝缘层143的远离衬底基板14的一侧，并通过第一栅绝缘层141、第二栅绝缘层142和层间绝缘层143中的过孔与有源层221电连接，源漏电极的远离衬底基板14的一侧设置有平坦化层144，以平坦化第二像素电路。
例如，平坦化层144中具有过孔144A，第二阳极结构211通过平坦化层144中过孔144A与薄膜晶体管22的源极223电连接。
例如，在一些实施例中，源极223与第二阳极结构211之间还可以具有过渡层(图中未示出)，该过渡层可以与第一连接走线15同层设置。
例如，如图3所示，显示区域还包括至少部分围绕第二显示区20的第三显示区域30，第三显示区域30包括阵列排布的多个第三子像素。例如，图16示出了一种第三显示区域30的截面示意图，如图16所示，每个第三子像素包括第三发光器件31以及与第三发光器件电连接的第三像素电路，第三像素电路配置为驱动第三发光器件31。第三发光器件31包括第三阳极结构311、第三阴极结构313以及第三阳极结构311与第三阴极结构313之间的第三发光层312，第三阳极结构311通过过孔与第三像素电路电连接。例如，第三阳极结构311可以包括多个阳极子层，例如包括ITO/Ag/ITO三层结构等(图中未示出)，本公开的实施例对第三阳极结构311的具体形式不做限定。
例如，第三像素电路包括薄膜晶体管32和存储电容33等结构。例如，薄膜晶体管32包括有源层331、栅极332和源漏电极(即源极233和漏极234)等结构，存储电容33包括第一电容极板331和第二电容极板332。例如，有源层321设置在衬底基板14上，有源层321的远离衬底基板14的一侧设置有第一栅绝缘层141，栅极322和第一电容极板331同层设置在第一栅绝缘层141的远离衬底基板14的一侧，栅极322和第一电容极板331的 远离衬底基板14的一侧设置有第二栅绝缘层142，第二电容极板332设置在第二栅绝缘层142的远离衬底基板14的一侧，第二电容极板332的远离衬底基板14的一侧设置有层间绝缘层143，源漏电极设置在层间绝缘层143的远离衬底基板14的一侧，并通过第一栅绝缘层141、第二栅绝缘层142和层间绝缘层143中的过孔与有源层321电连接，源漏电极的远离衬底基板14的一侧设置有平坦化层144，以平坦化第三像素电路。
例如，平坦化层144中具有过孔144B，第三阳极结构311通过绝缘层145中的过孔144B与薄膜晶体管32的源极323电连接。
例如，在一些实施例中，源极323与第二阳极结构311之间还可以具有过渡层(图中未示出)，该过渡层可以与第一连接走线15同层设置。
例如，第二显示区域20中的第一像素电路和第二像素电路与第三显示区域30中的第三像素电路是同层设置的，因此在制备工艺中可采用相同的构图工艺形成。例如，第一栅极绝缘层141、第二栅极绝缘层142、层间绝缘层143以及平坦化层144在第二显示区域20和第三显示区域30是同层设置的，在一些实施例中还是一体连接的，因此在附图中采用了相同的标号。
例如，在一些实施例中，如图4和图6-图8所示，第一显示区域10还包括位于衬底基板14上的透明支撑层18，第一发光器件11位于透明支撑层18的远离衬底基板14的一侧。由此，相对于衬底基板14来说，第一显示区域10中的第一发光器件11可以与第二显示区域20中的第二发光器件21以及第三显示区域30中的第三发光器件31处于基本相同的高度，从而可以提高显示基板的显示效果。
例如，透明支撑层18与第一栅绝缘层141、第二栅绝缘层142、层间绝缘层143和平坦化层144中的至少一种同层设置。例如，透明支撑层18与第一栅绝缘层141、第二栅绝缘层142、层间绝缘层143和平坦化层144均同层设置，以使第一显示区域10中的第一发光器件11与第二显示区域20中的第二发光器件21以及第三显示区域30中的第三发光器件31处于基本相同的高度，并简化显示基板的制备工艺。
例如，在一些实施例中，显示基板还包括像素界定层146、封装层147等结构，例如，像素界定层146设置在第一阳极结构上，包括多个开口，第一发光层形成在像素界定层146的开口中。例如，封装层147可以包括单层或多层封装结构，多层封装结构例如包括无机封装层和有机封装层的叠层， 由此提高对显示基板的封装效果。
例如，在第一显示区域10、第二显示区域20和第三显示区域30中，像素界定层146和封装层147是同层设置的，在一些实施例中还是一体连接的，因此在附图中采用了相同的标号。
例如，本公开的各个实施例中，衬底基板14可以为玻璃基板、石英基板、金属基板或树脂类基板等。本公开的实施例对此不作限制。
例如，第一栅极绝缘层141、第二栅极绝缘层142、层间绝缘层143以及平坦化层144、绝缘层145、像素界定层146、封装层147以及绝缘层148可以包括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，或者可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料。本公开的实施例对上述各功能层的材料均不做具体限定。
例如，有源层的材料可以包括多晶硅或氧化物半导体(例如，氧化铟镓锌)等半导体材料。例如，有源层121/221/321的部分可以通过掺杂等导体化处理以导体化，从而具有较高的导电性。
例如，栅极、第一电容极板和第二电容极板的材料可以包括金属材料或者合金材料，例如包括钼、铝及钛等。
例如，源漏电极的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层，例如钛、铝、钛三层金属叠层(Ti/Al/Ti)等。
例如，本公开实施例提供的显示基板可以为有机发光二极管(OLED)显示基板或者量子点发光二极管(QLED)显示基板等显示基板，本公开的实施例对显示基板的具体种类不做限定。
例如，在显示基板为有机发光二极管显示基板的情形，发光层111/211/311可以包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光等。并且，根据实际不同需要，在不同的示例中，发光层111/211/311还可以进一步包括电子注入层、电子传输层、空穴注入层、空穴传输层等功能层。
例如，在显示基板为量子点发光二极管(QLED)显示基板的情形，发光层111/211/311可以包括量子点材料，例如，硅量子点、锗量子点、硫化镉量子点、硒化镉量子点、碲化镉量子点、硒化锌量子点、硫化铅量子点、硒化铅量子点、磷化铟量子点和砷化铟量子点等，量子点的粒径为2-20nm。
例如，在本公开的实施例中，第一显示区域10可以为圆形(图3中示出的情形)、矩形、三角形等各种形状，本公开的实施例第一显示区域10的形状不做限定。
例如，在一些实施例中，如图4、图6-图8所示，显示基板还可以包括传感器19，例如图像传感器、红外传感器、距离传感器等，传感器19例如可以实现为芯片等形式。例如，传感器19设置于显示基板的第二侧，例如传感器19通过双面胶等方式设置在显示面板的第二侧，并且传感器19在衬底基板14上的正投影与第一显示区域10至少部分重叠，配置为接收来自第一侧的光。由此，第一显示区域10在实现显示的同时，还为传感器19的设置提供了便利。
本公开至少一实施例还提供一种显示基板的制备方法，该显示基板具有用于显示的第一侧(显示侧)和与第一侧相对的第二侧(非显示侧或背侧)，该制备方法包括：形成显示区域，以及在第一显示区域和第二显示区域中形成至少一条第一连接走线。显示区域包括第一显示区域以及至少部分围绕第一显示区域的第二显示区域，第一显示区域允许来自第一侧的光至少部分透射至第二侧。第一连接走线包括彼此电连接的位于第一显示区域的第一部分和位于第二显示区域的第二部分，第一部分包括第一透光走线层，第二部分包括金属走线层。
例如，在一些实施例中，形成显示区域还包括：在第一显示区域中形成阵列排布的多个第一子像素，每个第一子像素包括第一发光器件，并在第二显示区域中形成多个第一像素电路，至少一条第一连接走线包括多条第一连接走线；多个第一像素电路分别通过多条第一连接走线电连接多个第一子像素的第一发光器件，以用于驱动多个第一子像素的第一发光器件。
例如，在一些实施例中，形成第一连接走线的第二部分还包括：形成与金属走线层叠层的第二透光走线层，并且第二透光走线层与第一透光走线层同层形成且一体连接。
例如，在一些实施例中，显示基板的制备方法还包括：提供衬底基板，此时，形成第一连接走线的第二部分还包括：形成与金属走线层叠层的防氧化保护层。第二透光走线层形成于衬底基板上，金属走线层形成于第二透光走线层的远离衬底基板的一侧，防氧化保护层形成于金属走线层的远离衬底基板的一侧。
下面，以图4中示出的显示基板为例，对本公开至少一实施例提供的显示基板的制备方法进行介绍。
例如，如图17A所示，在衬底基板14上采用构图工艺同时形成第二显示区域20和第三显示区域30中的像素电路(包括第一像素电路、第二像素电路和第三像素电路)，并同时形成透明支撑层18。
以形成第一像素电路为例，如图17A所示，形成第一像素电路包括形成薄膜晶体管12和存储电容13，薄膜晶体管12包括有源层121、栅极122和源漏电极123和124；存储电容13包括第一电容极板131和第二电容极板132。如图17A所示，有源层121形成在衬底基板14上，在有源层121的远离衬底基板14的一侧形成第一栅绝缘层141，在第一栅绝缘层141上同层形成栅极122和第一电容极板131，在栅极122和第一电容极板131的远离衬底基板14的一侧形成第二栅绝缘层142，在第二栅绝缘层142的远离衬底基板14的一侧形成第二电容极板132，在第二电容极板132的远离衬底基板14的一侧形成层间绝缘层143，在层间绝缘层143的远离衬底基板14的一侧形成源漏电极123和124，源漏电极123和124通过第一栅绝缘层141、第二栅绝缘层142和层间绝缘层143中的过孔与有源层121电连接，然后在源漏电极123和124的远离衬底基板14的一侧形成平坦化层144。例如，平坦化层144中形成有暴露源漏极的过孔。例如，透明支撑层18与第一栅绝缘层141、第二栅绝缘层142、层间绝缘层143和平坦化层144中的至少一种同层形成。例如，透明支撑层18与第一栅绝缘层141、第二栅绝缘层142、层间绝缘层143和平坦化层144均同层形成。
例如，上述每一功能层均采用构图工艺形成。一次构图工艺例如包括光刻胶的形成、曝光、显影以及刻蚀等工序。
例如，在一些实施例中，在形成上述结构之前，还可以在衬底基板14上形成缓冲层(图中未示出)，缓冲层作为过渡层可以防止衬底基板14中的有害物质侵入显示基板的内部，并且还可以增加显示基板中的膜层在衬底基板14上的附着力。例如，缓冲层的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料形成的单层或多层结构。
例如，在上述结构形成后，在第一显示区域10和第二显示区域20中形成第一连接走线。例如，如图17A所示，通过掩膜板40在第一显示区域10和第二显示区域20依次沉积透光走线材料层151、金属走线材料层161以及 导电保护材料层171。例如，掩膜板40具有镂空部分(即图中的白色部分)，以使材料通过镂空部分形成一定的图案。由此，通过掩膜板40沉积的透光走线材料层151、金属走线材料层161以及导电保护材料层171具有基本相同的图案。
然后，如图17B所示，使用干刻蚀法刻蚀掉位于第一显示区域10的金属走线材料层161以及导电保护材料层171，而仅保留位于第二显示区域20的金属走线材料层161以及导电保护材料层171。由此形成包括第一部分15A和第二部分15B的第一连接走线15。由于干刻蚀法易于控制，能够精确控制对金属走线材料层161以及导电保护材料层171的刻蚀厚度，因此可通过一次干刻蚀法即形成第一连接走线15。
例如，在另一些实施例中，在通过掩膜板40在第一显示区域10和第二显示区域20依次沉积透光走线材料层151、金属走线材料层161以及导电保护材料层171后，也可以使用湿刻蚀法刻蚀掉位于第一显示区域10的金属走线材料层161以及导电保护材料层171。但是，由于湿刻蚀法的刻蚀精确度较低，刻蚀厚度不易控制，为了保证完全除去第一显示区域10的金属走线材料层161以及导电保护材料层171，一般会采用过刻。此时，如图18A所示，透光走线材料层151位于第一显示区域10的部分可能会被部分刻蚀，为了保证第一显示区域10中透光走线材料层151的厚度及其与第二显示区域20中的透光走线材料层151的连接性，可以在上述湿法刻蚀后，通过掩膜板40在第一显示区域10和第二显示区域20中再沉积一层透光走线材料层，以增厚第一显示区域10中透光走线层的厚度，此时，透光走线材料层也会形成在金属走线材料层161的右侧面，如图18B所示。
例如，在一些实施例中，由于透光走线材料层151与导电保护材料层171可以采用相同的材料，例如采用ITO，因此在图18B中，透光走线材料层151与导电保护材料层171示出为一体连接的结构。
例如，在其他实施例中，也可以采用基本相同的方法形成如图7和图8所示的显示基板。例如，在形成如图7所示的显示基板时，在通过掩膜板40在第一显示区域10和第二显示区域20依次沉积透光走线材料层151、金属走线材料层161以及导电保护材料层171后，可以使用干刻蚀法刻蚀掉位于第一显示区域10中的部分金属走线材料层161以及导电保护材料层171，以同层形成第一连接走线15和第一阳极结构111。例如，在该实施例中，透光 走线材料层151的材料可以采用ITO，金属走线材料层161的材料可以采用Ag，导电保护材料层171可以采用ITO。
例如，在形成图8所示的显示基板时，可采用构图工艺先形成第二部分15B的金属走线层，然后在金属走线层上形成绝缘层148，并在绝缘层148中形成过孔。之后，在绝缘层148上采用构图工艺形成第一部分15A的第一透光走线层，第一透光走线层通过绝缘层148中形成的过孔与第二部分15B电连接，由此形成包括第一部分15A和第二部分15B的第一连接走线。
例如，在第一连接走线15形成后，显示基板的制备方法还包括在第一连接走线15上形成像素界定层、发光器件以及封装层等结构，这些结构的具体形成方式可参见相关技术，在此不再赘述。
例如，参考图4和图6-图8，在显示基板的上述结构形成完成后，显示基板的制备方法还可以包括：提供传感器，并将传感器结合于显示基板的第二侧。此时，传感器在衬底基板上的正投影与第一显示区域至少部分重叠，由此可通过第一显示区域接收来自第一侧的光。
在本公开各实施例提供的显示基板及其制备方法中，第一显示区域具有较高的透光性，因此可以在实现显示的同时，为传感器的设置提供便利。另外，位于第一显示区域和第二显示区域的第一连接走线具有较低的电阻，由此可提高第一连接走线的信号传输速度；当采用为多条第一连接走线为第一显示区域的多个第一发光器件传输驱动信号时，流经多条第一连接走线15的电流具有较高的均一性，进而还可进一步提高显示基板的显示效果。
还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易 想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (21)

  1. 一种显示基板，具有用于显示的第一侧和与所述第一侧相对的第二侧，所述显示基板包括：
    显示区域，其中，所述显示区域包括第一显示区域以及至少部分围绕所述第一显示区域的第二显示区域，所述第一显示区域允许来自所述第一侧的光至少部分透射至所述第二侧；
    在所述第一显示区域和所述第二显示区域中的至少一条第一连接走线，其中，所述第一连接走线包括彼此电连接的位于所述第一显示区域的第一部分和位于所述第二显示区域的第二部分，所述第一部分包括第一透光走线层，所述第二部分包括金属走线层。
  2. 根据权利要求1所述的显示基板，其中，所述第一显示区域包括阵列排布的多个第一子像素，每个第一子像素包括第一发光器件，所述至少一条第一连接走线包括多条第一连接走线；
    所述第二显示区域包括多个第一像素电路，所述多个第一像素电路分别通过所述多条第一连接走线电连接所述多个第一子像素的第一发光器件，以用于驱动所述多个第一子像素的第一发光器件。
  3. 根据权利要求1或2所述的显示基板，其中，所述第二部分还包括与所述金属走线层叠层的第二透光走线层，所述第二透光走线层与所述第一透光走线层同层设置且一体连接。
  4. 根据权利要求3所述的显示基板，其中，所述第二部分还包括与所述金属走线层叠层的防氧化保护层，
    所述显示基板包括衬底基板，所述第二透光走线层位于所述衬底基板上，所述金属走线层位于所述第二透光走线层的远离所述衬底基板的一侧，所述防氧化保护层位于所述金属走线层的远离所述衬底基板的一侧。
  5. 根据权利要求4所述的显示基板的制备方法，其中，所述金属走线层的材料包括Ag、Al、Mo或Ti；
    所述防氧化保护层的材料包括透明氧化物。
  6. 根据权利要求2-5任一所述的显示基板，其中，所述第一发光器件包括第一阳极结构、第一阴极结构以及在所述第一阳极结构与所述第一阴极结构之间的第一发光层，
    所述第一部分通过过孔与所述第一阳极结构电连接。
  7. 根据权利要求2-6任一所述的显示基板，其中，所述第二显示区域还包括多个第二子像素，每个第二子像素包括第二发光器件以及与所述第二发光器件电连接的第二像素电路，所述第二像素电路配置为驱动所述第二发光器件，
    在所述第二显示区域中，所述多个第二像素电路呈第一阵列排布。
  8. 根据权利要求7所述的显示基板，其中，在所述第二显示区域中，所述多个第一像素电路设置在所述第一阵列中，并与所述多个第二像素电路排布为第二阵列。
  9. 根据权利要求7或8所述的显示基板，其中，所述第二发光器件包括第二阳极结构、第二阴极结构以及所述第二阳极结构与所述第二阴极结构之间的第二发光层，
    所述第二阳极结构通过过孔与所述第二像素电路电连接。
  10. 根据权利要求1-9任一所述的显示基板，其中，所述显示区域还包括至少部分围绕所述第二显示区的第三显示区域，所述第三显示区域包括阵列排布的多个第三子像素，每个第三子像素包括第三发光器件以及与所述第三发光器件电连接的第三像素电路，所述第三像素电路配置为驱动所述第三发光器件，
    所述第三发光器件包括第三阳极结构、第三阴极结构以及所述第三阳极结构与所述第三阴极结构之间的第三发光层，所述第三阳极结构通过过孔与所述第三像素电路电连接。
  11. 根据权利要求2-9任一所述的显示基板，其中，所述显示基板包括衬底基板，
    所述第一显示区域还包括位于所述衬底基板上的透明支撑层，所述第一发光器件位于所述透明支撑层的远离所述衬底基板的一侧。
  12. 根据权利要求11所述的显示基板，其中，所述第一像素电路包括薄膜晶体管和存储电容，所述薄膜晶体管包括有源层、栅极和源漏电极；所述存储电容包括第一电容极板和第二电容极板，
    所述有源层设置在所述衬底基板上，所述有源层的远离所述衬底基板的一侧设置有第一栅绝缘层，
    所述栅极和所述第一电容极板同层设置在所述第一栅绝缘层的远离所 述衬底基板的一侧，所述栅极和所述第一电容极板的远离所述衬底基板的一侧设置有第二栅绝缘层，
    所述第二电容极板设置在所述第二栅绝缘层的远离所述衬底基板的一侧，所述第二电容极板的远离所述衬底基板的一侧设置有层间绝缘层，
    所述源漏电极设置在所述层间绝缘层的远离所述衬底基板的一侧，并通过所述第一栅绝缘层、所述第二栅绝缘层和所述层间绝缘层中的过孔与所述有源层电连接，所述源漏电极的远离所述衬底基板的一侧设置有平坦化层；
    所述透明支撑层与所述第一栅绝缘层、所述第二栅绝缘层、所述层间绝缘层和所述平坦化层中的至少一种同层设置。
  13. 根据权利要求11所述的显示基板，还包括传感器，其中，所述传感器设置于所述显示基板的第二侧，并且所述传感器在所述衬底基板上的正投影与所述第一显示区域至少部分重叠，配置为接收所述来自所述第一侧的光。
  14. 一种显示基板的制备方法，所述显示基板具有用于显示的第一侧和与所述第一侧相对的第二侧，所述制备方法包括：
    形成显示区域，所述显示区域包括第一显示区域以及至少部分围绕所述第一显示区域的第二显示区域，所述第一显示区域允许来自所述第一侧的光至少部分透射至所述第二侧；
    在所述第一显示区域和所述第二显示区域中形成至少一条第一连接走线，其中，所述第一连接走线包括彼此电连接的位于所述第一显示区域的第一部分和位于所述第二显示区域的第二部分，所述第一部分包括第一透光走线层，所述第二部分包括金属走线层。
  15. 根据权利要求14所述的显示基板的制备方法，其中，形成所述显示区域还包括：
    在所述第一显示区域中形成阵列排布的多个第一子像素，每个第一子像素包括第一发光器件，
    在所述第二显示区域中形成多个第一像素电路，其中，所述至少一条第一连接走线包括多条第一连接走线；所述多个第一像素电路分别通过所述多条第一连接走线电连接所述多个第一子像素的第一发光器件，以用于驱动所述多个第一子像素的第一发光器件。
  16. 根据权利要求15所述的显示基板的制备方法，其中，形成所述第 一连接走线的第二部分还包括：
    形成与所述金属走线层叠层的第二透光走线层，其中，所述第二透光走线层与所述第一透光走线层同层形成且一体连接。
  17. 根据权利要求16所述的显示基板的制备方法，还包括：提供衬底基板，其中，形成第一连接走线的第二部分还包括：形成与所述金属走线层叠层的防氧化保护层，
    其中，所述第二透光走线层形成于所述衬底基板上，所述金属走线层形成于所述第二透光走线层的远离所述衬底基板的一侧，所述防氧化保护层形成于所述金属走线层的远离所述衬底基板的一侧。
  18. 根据权利要求17所述的显示基板的制备方法，其中，形成所述第一连接走线包括：
    通过掩膜板在所述第一显示区域和所述第二显示区域依次沉积透光走线材料层、金属走线材料层以及导电保护材料层；
    使用干刻蚀法刻蚀掉位于所述第一显示区域的金属走线材料层以及导电保护材料层。
  19. 根据权利要求17所述的显示基板的制备方法，其中，形成所述第一连接走线包括：
    通过掩膜板在所述第一显示区域和所述第二显示区域依次沉积透光走线材料层、金属走线材料层以及导电保护材料层；
    使用湿刻蚀法刻蚀掉位于所述第一显示区域的金属走线材料层以及导电保护材料层；
    通过所述掩膜板在所述第一显示区域和所述第二显示区域再沉积一层透光走线材料层。
  20. 根据权利要求17所述的显示基板的制备方法，其中，形成所述第一像素电路包括形成薄膜晶体管和存储电容，所述薄膜晶体管包括有源层、栅极和源漏电极；所述存储电容包括第一电容极板和第二电容极板，
    其中，所述有源层形成在所述衬底基板上，在所述有源层的远离所述衬底基板的一侧形成第一栅绝缘层，
    所述栅极和所述第一电容极板同层形成在所述第一栅绝缘层的远离所述衬底基板的一侧，在所述栅极和所述第一电容极板的远离所述衬底基板的一侧形成第二栅绝缘层，
    所述第二电容极板形成在所述第二栅绝缘层的远离所述衬底基板的一侧，在所述第二电容极板的远离所述衬底基板的一侧形成层间绝缘层，
    所述源漏电极形成在所述层间绝缘层的远离所述衬底基板的一侧，并通过所述第一栅绝缘层、所述第二栅绝缘层和所述层间绝缘层中的过孔与所述有源层电连接，在所述源漏电极的远离所述衬底基板的一侧形成平坦化层；
    形成所述第一显示区域还包括：在所述衬底基板与所述第一发光器件之间形成透明支撑层，
    其中，所述透明支撑层与所述第一栅绝缘层、所述第二栅绝缘层、所述层间绝缘层中和所述平坦化层中的至少一种同层形成。
  21. 根据权利要求17所述的显示基板的制备方法，还包括：提供传感器，并将所述传感器结合于所述显示基板的第二侧，其中，所述传感器在所述衬底基板上的正投影与所述第一显示区域至少部分重叠，配置为接收所述来自所述第一侧的光。
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