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WO2021068233A1 - 显示基板、显示装置及制造显示基板的方法 - Google Patents

显示基板、显示装置及制造显示基板的方法 Download PDF

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Publication number
WO2021068233A1
WO2021068233A1 PCT/CN2019/110779 CN2019110779W WO2021068233A1 WO 2021068233 A1 WO2021068233 A1 WO 2021068233A1 CN 2019110779 W CN2019110779 W CN 2019110779W WO 2021068233 A1 WO2021068233 A1 WO 2021068233A1
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WO
WIPO (PCT)
Prior art keywords
substrate
conductive
display substrate
dielectric layer
layer
Prior art date
Application number
PCT/CN2019/110779
Other languages
English (en)
French (fr)
Inventor
狄沐昕
王珂
王国强
梁志伟
顾仁权
刘英伟
姚琪
曹占锋
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/110779 priority Critical patent/WO2021068233A1/zh
Priority to EP19944648.5A priority patent/EP4002467A4/en
Priority to CN201980001953.0A priority patent/CN113068414A/zh
Priority to US16/975,771 priority patent/US12062744B2/en
Publication of WO2021068233A1 publication Critical patent/WO2021068233A1/zh
Priority to US18/518,526 priority patent/US20240088170A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/387—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • the present disclosure relates to the field of display technology. More specifically, it relates to a display substrate, a display device, and a method of manufacturing the display substrate.
  • GOA Gate Driver On Array
  • COF Chip On Film
  • the embodiment of the present disclosure provides a display substrate.
  • the display substrate includes: a substrate having a first side and a second side opposite to the first side; a through hole provided in the substrate; a thin film transistor provided on the second side of the substrate On one side; a first conductive structure disposed on the first side of the substrate, wherein the first sub-portion of the first conductive structure is located in the through hole, wherein the first conductive structure
  • the material of is the same as the material of the source/drain electrodes of the thin film transistor.
  • the display substrate further includes a first conductive portion, the first conductive portion is at least partially located in the through hole and directly contacts the first sub-portion of the first conductive structure.
  • the surface of the first conductive portion facing away from the first side of the substrate is coplanar with the second side.
  • the display substrate further includes a first dielectric layer located between the substrate and the first conductive portion, and the first side of the first dielectric layer facing away from the substrate The surface is coplanar with the second side.
  • the display substrate further includes an intermediate layer; a first opening penetrates the intermediate layer and communicates with the through hole, wherein the second sub-portion of the first conductive structure at least partially covers the The sidewall of the first opening, and wherein the third sub-portion of the first conductive structure is located on the surface of the intermediate layer away from the substrate.
  • the source/drain electrodes of the thin film transistor are at least arranged in the same layer as the third sub-part of the first conductive structure.
  • the display substrate further includes a light emitting element, the light emitting element includes a first electrode and a second electrode, wherein one of the first electrode and the second electrode is connected to the source/drain Extremely electrical connection.
  • the display substrate further includes a second dielectric layer, wherein the second dielectric layer covers the source/drain electrodes and the first conductive structure.
  • the display substrate further includes a second conductive portion, wherein the second conductive portion is electrically connected to the source/drain electrode through a via hole located in the second dielectric layer.
  • the display substrate further includes a third dielectric layer, wherein the third dielectric layer covers at least a side surface of the second conductive portion.
  • the display substrate further includes a light-shielding pattern, the light-shielding pattern is located on a side of the third dielectric layer away from the substrate, and the orthographic projection of the light-shielding pattern on the substrate At least cover the orthographic projection of the first conductive part on the substrate.
  • the display substrate further includes an integrated circuit disposed on the second side of the substrate, wherein the integrated circuit is electrically connected to the first conductive part.
  • the embodiment of the present disclosure also provides a display device.
  • the display device includes the display substrate as described above.
  • Embodiments of the present disclosure also provide a method of manufacturing a display substrate.
  • the method of manufacturing a display substrate includes: providing a substrate; forming a through hole in the substrate; forming a first conductive structure and a thin film transistor on a first side of the substrate, wherein the first conductive structure The first sub-portion of is located in the through hole, and the first conductive structure and the source electrode and the drain electrode of the thin film transistor are prepared by a one-time film forming process.
  • providing the substrate includes: providing a supporting substrate; providing a sacrificial layer on the supporting substrate; forming a first conductive portion on the sacrificial layer; forming a first dielectric layer (green PVX on pad1) To cover the first conductive part and the sacrificial layer; and to coat a first material on the first dielectric layer to form the substrate.
  • the method of manufacturing a display substrate further includes: forming an intermediate layer on the substrate; wherein, forming the through hole in the substrate includes: forming through the intermediate layer and the substrate. The hole of the substrate exposes the surface of the first conductive part.
  • forming the first conductive structure includes: forming a conductive material layer on the intermediate layer; and performing a patterning process on the conductive material layer to form the first conductive structure and the source/drain electrodes .
  • FIG. 1 is a schematic diagram of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a display substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic top view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a spliced display device according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic flowchart of a method for manufacturing a display substrate according to an embodiment of the present disclosure.
  • 10A-10E are schematic diagrams of a method of manufacturing a display substrate according to an embodiment of the present disclosure.
  • 11A-11J are schematic diagrams of a method of manufacturing a display substrate according to an embodiment of the present disclosure.
  • 12A-12F are schematic diagrams of a method of manufacturing a display substrate according to an embodiment of the present disclosure.
  • the terms “overlying”, “on top of”, “positioned on top” or “positioned on top” mean that a first element such as a first structure is present on a second element such as a second structure Above, where there may be an intermediate element such as an interface structure between the first element and the second element.
  • the term “contact” means to connect a first element such as a first structure and a second element such as a second structure, and there may or may not be other elements at the interface of the two elements.
  • FIG. 1 is a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • a display substrate according to an embodiment of the present disclosure includes: a substrate 10 having a first side S1 and a second side S2 opposite to the first side S1; a through hole V1 provided in the substrate 10 Thin film transistor 11, which is disposed on the first side S1 of the substrate 10; the first conductive structure 12, which is disposed on the first side S1 of the substrate 10, wherein the first sub-portion 121 of the first conductive structure 12 is located Through hole V1.
  • the material of the first conductive structure 12 may be the same as the material of the source/drain electrode 111 of the thin film transistor.
  • the orthographic projection of the through hole V1 of the thin film transistor 11 on the substrate 10 does not coincide with the orthographic projection of the through hole V1 on the substrate 10.
  • a frameless or narrow frame display substrate can be realized.
  • a circuit or the like may be provided on the back side (eg, the second side) of the display substrate.
  • the area of the effective display area can be increased, and the display quality can be improved.
  • FIG. 2 is a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • the display substrate according to the embodiment of the present disclosure further includes a first conductive part 13.
  • the first conductive portion 13 is at least partially located in the through hole V1 and directly contacts the first sub-portion 121 of the first conductive structure 12.
  • the first conductive portion 13 may provide electrical connection to the first conductive structure 12.
  • the first conductive part 13 may at least partially cover the sidewall of the through hole V1.
  • the surface S131 of the first conductive portion 13 facing away from the first side S1 of the substrate 10 is coplanar with the second side S2.
  • the first conductive part 13 may include a single layer or a stacked layer structure.
  • the first conductive part may include at least one of the following: Ti/Al/Ti stack or Cu.
  • the substrate 10 may include a flexible substrate.
  • the substrate 10 may include a polymide (PI) substrate.
  • FIG. 3 is a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • the display substrate according to an embodiment of the present disclosure may further include a first dielectric layer 14 between the substrate 10 and the first conductive portion 13.
  • the surface S141 of the first dielectric layer 14 facing away from the first side S1 of the substrate 10 is coplanar with the second side S2.
  • the first dielectric layer 14 may be used as a passivation layer.
  • the first dielectric layer 14 may include silicon nitride (SiNx).
  • FIG. 4 is a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • the display substrate according to an embodiment of the present disclosure may further include an intermediate layer 15 and a first opening 16.
  • the intermediate layer 15 may be located between the substrate 10 and the first conductive structure 12. It can be seen from FIG. 4 that the first opening 16 penetrates the intermediate layer 15 and communicates with the through hole V1.
  • the second sub-portion 122 of the first conductive structure 12 may at least partially cover the sidewall 161 of the first opening 16.
  • the third sub-portion 123 of the first conductive structure 12 is located on the surface of the intermediate layer 15 away from the substrate 10.
  • the source/drain electrode 111 of the thin film transistor may be provided at least in the same layer as the third sub-part 123 of the first conductive structure 12.
  • the "same layer arrangement" here can also be said to be formed by the same film layer.
  • FIG. 5 is a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • the display substrate according to the embodiment of the present disclosure may further include a light emitting element 17.
  • the light emitting element 17 may include a first electrode 171 and a second electrode 172, wherein one of the first electrode 171 and the second electrode 172 is electrically connected to the source/drain electrode 111.
  • FIG. 5 exemplifies that the first electrode 171 is electrically connected to the source/drain electrode 111. It can be understood that the positions of the first pole 171 and the second pole 172 can be interchanged.
  • the first pole 171 may be one of a positive electrode and a negative electrode
  • the second pole 172 may be the other of a positive electrode and a negative electrode.
  • the display substrate may further include a second dielectric layer 18.
  • the second dielectric layer 18 may cover the source/drain electrodes 111 and the first conductive structure 12.
  • the display substrate may further include a second conductive part 19.
  • the second dielectric layer 18 may have a first hole exposing the source/drain electrode 111.
  • the second conductive portion 19 may be electrically connected to the source/drain electrode 111 through the first hole in the second dielectric layer 18.
  • the display substrate may further include a third conductive part 20 and a fourth conductive part 21.
  • the fourth conductive portion 21 may be located on the side of the intermediate layer 15 away from the substrate 10.
  • the fourth conductive part 21 may include the same material as the source/drain electrode 111.
  • the fourth conductive portion 21 may be provided in the same layer as the source/drain electrode 111, that is, the two may be formed of the same film layer.
  • the second dielectric layer 18 may further have a second hole exposing the fourth conductive part 21.
  • the third conductive portion 20 may be electrically connected to the fourth conductive portion 21 through the second hole. With this arrangement, the light-emitting element 17 can be provided with a display signal conveniently.
  • a third dielectric layer 22 is further included.
  • the third dielectric layer 22 covers at least the side surface of the second conductive portion 19.
  • the third dielectric layer 22 can prevent the side surface of the second conductive portion 19 from being oxidized. It can be seen from FIG. 5 that the third dielectric layer 22 is located on the side of the second dielectric layer 18 facing away from the substrate 10.
  • the display substrate further includes a light shielding pattern 23.
  • the light shielding pattern 23 may be located on a side of the third dielectric layer 22 away from the substrate.
  • the orthographic projection of the light shielding pattern 23 on the substrate 10 at least covers the orthographic projection of the first conductive portion 13 on the substrate 10.
  • the light-shielding pattern 23 can block the incident or reflection of undesired light, and can improve the display effect.
  • the intermediate layer 15 may include a first sub-dielectric layer 151 and a second sub-dielectric layer 152 sequentially arranged on the first side of the substrate 10 in a direction away from the substrate 10.
  • the source/drain electrode 111 of the thin film transistor includes a first portion 111 a located on the side of the intermediate layer 15 facing away from the substrate 10 and a second portion 111 b passing through at least a portion of the intermediate layer 15 to reach the active layer 112.
  • the first sub-dielectric layer 151 covers the active layer 112 and serves as a gate dielectric layer of the thin film transistor.
  • the gate electrode 113 is located on the side of the first sub-dielectric layer 151 away from the substrate 10 and is covered by the second sub-dielectric 152.
  • the intermediate layer 15 may further include a third sub-dielectric layer 153 disposed on a side of the second sub-dielectric layer 152 away from the substrate 10.
  • the display substrate further includes a conductive structure 24 located on a side of the second sub-medium layer 152 facing away from the substrate 10 and covered by the third sub-medium 153.
  • the orthographic projection of the conductive structure 24 on the substrate 10 and the orthographic projection of the gate electrode 113 on the substrate 10 at least partially overlap.
  • the conductive structure 24 may form a storage capacitor with the gate electrode 113.
  • FIG. 6 is a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • the intermediate layer 15 may include a first sub-dielectric layer 151 and a second sub-dielectric layer 152 that are sequentially arranged along a direction away from the substrate 10 on the first side of the substrate 10.
  • the second sub-dielectric layer 152 may be used as a gate dielectric layer.
  • the first sub-dielectric layer 151 and the second sub-dielectric layer 152 may include at least one of silicon oxide and silicon nitride.
  • the gate electrode 113 may be located on a side of the first sub-dielectric layer 151 facing away from the substrate 10 and covered by the second sub-dielectric layer 152.
  • the active layer 112 is located on the side of the second sub-dielectric layer 152 away from the substrate 10.
  • the display substrate may further include a conductive structure 24 on the substrate 10 and covered by the first sub-dielectric layer 151.
  • the orthographic projection of the conductive structure 24 on the substrate 10 and the orthographic projection of the gate electrode 113 on the substrate 10 at least partially overlap, so as to form a storage capacitor with the gate electrode 113.
  • the display substrate may further include a barrier layer 25 and a buffer layer located between the substrate 10 and the first sub-dielectric layer 151 and arranged in a direction away from the substrate 10. 26.
  • the barrier layer 25 may include silicon oxide (SiOx).
  • the buffer layer 26 may include at least one of silicon oxide (SiOx) or silicon nitride (SiNx).
  • Both the buffer layer and the barrier layer can prevent heat from spreading. This way, on the one hand, it can prevent the influence of heat on the underlying material, and on the other hand, it can play a role in insulating the crystallization process of the active layer.
  • the barrier layer 26 may include at least one of silicon oxide and silicon nitride.
  • the buffer layer can also prevent impurities from entering the active layer to avoid affecting the characteristics of the thin film transistor.
  • the display substrate may further include an integrated circuit 29 on a second side of the substrate 10 opposite to the first side.
  • the integrated circuit 29 is electrically connected to the first conductive portion 13.
  • the integrated circuit 29 can be used to input/output electrical signals to the display substrate.
  • FIG. 7 is a schematic top view of a display substrate according to an embodiment of the present disclosure.
  • the area AA' of the display substrate 100 according to an embodiment of the present disclosure is a display area, and the area BB' may also be a display area.
  • the area BB' is the frame area of the display substrate, and wiring, etc., need to be provided, and display cannot be realized.
  • the BB' area can simultaneously realize the functions of setting wiring (i.e., serving as a bonding area) and displaying. Therefore, the embodiments of the present disclosure can realize a display substrate with no frame or a narrow frame.
  • a circuit or the like can be provided on the back side (eg, the second side) of the display substrate, which solves the problem that the circuit occupies an effective display area.
  • the area of the effective display area can be increased, and the display quality can be improved.
  • the embodiment of the present disclosure also provides a display device.
  • FIG. 8 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the display device 200 according to the embodiment of the present disclosure includes the display substrate 100 as described above. It should be understood that although the drawings only show the case where the display device 200 includes one display substrate 100, the display device 200 may also include a plurality of display substrates 100 spliced together.
  • Embodiments of the present disclosure also provide a method of manufacturing a display substrate.
  • FIG. 9 is a schematic flowchart of a method of manufacturing a display substrate according to an embodiment of the present disclosure. As shown in FIG. 9, the method of manufacturing a display substrate according to an embodiment of the present disclosure includes:
  • a first conductive structure and a thin film transistor are formed on the first side of the substrate, wherein the first sub-portion of the first conductive structure is located in the through hole, and the first conductive structure is connected to the
  • the source electrode and the drain electrode of the thin film transistor are prepared by a single film forming process, in other words, are formed from the same film layer by a single patterning process.
  • 10A-10E are schematic diagrams of a method of manufacturing a display substrate according to an embodiment of the present disclosure.
  • the supporting substrate may be glass, for example.
  • a sacrificial layer (DBL) 28 is provided on the supporting substrate 27.
  • the sacrificial layer may include PI-like materials.
  • the first conductive portion 13 is formed on the sacrificial layer 28.
  • a first dielectric layer 14 is formed to cover the first conductive portion 13 and the sacrificial layer 28;
  • a first material 10' is coated on the first dielectric layer 14 to form a substrate 10.
  • a substrate 10 for example, liquid polyimide can be coated and then cured to form a substrate.
  • the method of manufacturing a display substrate may further include forming an intermediate layer 15 on the substrate 10.
  • Forming a through hole in the substrate may include forming a hole through the intermediate layer 15 and the substrate 10 to expose the surface of the first conductive part 13.
  • Forming the first conductive structure may include: forming a conductive material layer on the intermediate layer; and performing a patterning process on the conductive material layer to form the first conductive structure and source/drain electrodes.
  • 11A-11J are schematic diagrams of a method of manufacturing a display substrate according to an embodiment of the present disclosure.
  • a method of manufacturing a display substrate may include: forming a sacrificial layer 28 on the support substrate 27; forming a first conductive portion 13 on the sacrificial layer 28; A first dielectric layer 14 is formed to cover the first conductive portion 13; a substrate 10 is formed on the first dielectric layer 14; a barrier layer 25 is formed on the substrate 10; a buffer layer 26 is formed on the barrier layer 25; An active layer 112 is formed thereon. Both the buffer layer and the barrier layer can prevent heat from spreading. This way, on the one hand, it can prevent the influence of heat on the underlying material, and on the other hand, it can play a role in insulating the crystallization process of the active layer.
  • the barrier layer 26 may include at least one of silicon oxide and silicon nitride.
  • the buffer layer can also prevent impurities from entering the active layer to avoid affecting the characteristics of the thin film transistor.
  • the method of manufacturing a display substrate may further include: forming a first sub-dielectric layer 151 on the active layer 112; and forming a gate of a thin film transistor on the first sub-dielectric layer 151 Electrode 113; forming a second sub-dielectric layer 152 on the gate electrode 113; forming a conductive structure 24 on the second sub-dielectric layer; forming a third sub-dielectric layer 153 on the conductive structure.
  • the method of manufacturing a display substrate according to an embodiment of the present disclosure further includes: forming a first opening 16, a through hole V1, a first connection hole CH1, and a second connection hole CH2, for example, by etching.
  • the first opening 16 passes through the first sub-dielectric layer 151, the second sub-dielectric layer 152, the third sub-dielectric layer 153, the buffer layer 26 and the barrier layer 25.
  • the through hole V1 penetrates the substrate 10 and the first dielectric layer 14 and reaches the upper surface of the first conductive portion 13.
  • the first opening 16 and the through hole V1 can be formed by performing 1 to 3 etchings using the same mask.
  • the first connection hole CH1 and the second connection hole CH2 pass through the first sub-dielectric layer 151, the second sub-dielectric layer 152 and the third sub-dielectric layer 153 to reach the upper surface of the active layer 112.
  • the method of manufacturing a display substrate according to an embodiment of the present disclosure further includes: forming a first conductive structure 12, a source/drain electrode 111 of a thin film transistor, and a fourth conductive portion on the third sub-dielectric layer 153 twenty one.
  • the first conductive structure 12, the source/drain electrode 111 of the thin film transistor, and the fourth conductive portion 21 may be formed by a single film forming process.
  • a second material layer may be formed on the third sub-dielectric layer 153, and then the second material layer may be patterned (for example, etched) to form the first conductive structure 12 and the source/drain electrodes 111 of the thin film transistor.
  • the fourth conductive part 21 may be formed by a single film forming process.
  • the source/drain electrode 111 of the thin film transistor may include a first portion 111 a on the side of the intermediate layer 15 facing away from the substrate 10 and a second portion 111 b passing through at least a portion of the intermediate layer 15 to reach the active layer 112.
  • the method of manufacturing a display substrate according to an embodiment of the present disclosure further includes: forming a second dielectric layer 18 on the first conductive structure 12, the source/drain electrodes 111 of the thin film transistor, and the fourth conductive portion 21 .
  • the method of manufacturing a display substrate according to an embodiment of the present disclosure further includes: forming a first hole H1 and a second hole H2 in the second dielectric layer 18.
  • the first hole H1 reaches the upper surface of the source/drain electrode 111.
  • the second hole H2 of the fourth conductive portion reaches the upper surface of 21.
  • the method of manufacturing a display substrate according to an embodiment of the present disclosure further includes forming a second conductive part 19 in the first hole H1 and forming a third conductive part 20 in the second hole H2.
  • the second conductive portion 19 may be electrically connected to the source/drain electrode 111 through the first hole H1 located in the second dielectric layer 18.
  • the third conductive portion 20 may be electrically connected to the fourth conductive portion 21 through the second hole H2.
  • the method of manufacturing a display substrate according to an embodiment of the present disclosure further includes forming a third dielectric layer 22 on the second dielectric layer 18.
  • the third dielectric layer 22 may cover the side surfaces of the second portion 19 and the third conductive portion 20, thereby preventing the side surfaces of both from being oxidized.
  • the method of manufacturing a display substrate according to an embodiment of the present disclosure further includes forming a light-shielding pattern 23 on the third dielectric layer 22 (ie, on the side of the third dielectric layer 22 away from the substrate 10).
  • the orthographic projection of the light shielding pattern 23 on the substrate 10 at least covers the orthographic projection of the first conductive portion 13 on the substrate 10.
  • the method of manufacturing a display substrate according to an embodiment of the present disclosure may further include disposing the light emitting element 17 above the first hole H1 and the second hole H2, wherein the first pole 171 and the second pole 172 of the light emitting element 17 are located in the first hole H1 and the second hole H2, respectively. H1 and the second hole H2.
  • the first electrode 171 may be electrically connected to the source/drain electrode 111 through the first hole H1.
  • the second pole 172 may be electrically connected to the fourth conductive part 21 through the second hole H2.
  • the method of manufacturing a display substrate according to an embodiment of the present disclosure may further include binding the light emitting element 17.
  • the light emitting element 17 may include micro LEDs.
  • the light-emitting element 17 may also include other light-emitting elements, such as LEDs, organic light-emitting diodes (OLEDs), and the like.
  • the method of manufacturing a display substrate according to an embodiment of the present disclosure may further include separating the sacrificial layer 28 from the substrate 10.
  • a laser lift off (LLO) method may be used to separate the sacrificial layer 28 from the substrate 10. Specifically, after high-energy irradiation of the LLO, the material of the sacrificial layer 28 is decomposed, so that the sacrificial layer 28 is easily separated from the substrate 10.
  • LLO laser lift off
  • the method of manufacturing a display substrate according to an embodiment of the present disclosure may further include forming an integrated circuit 29 on a second side of the substrate 10 opposite to the first side.
  • the integrated circuit 29 is electrically connected to the first conductive portion 13.
  • the integrated circuit 29 may be used to control the operation of the display substrate, for example, to drive and control the display panel.
  • FIGS. 12A-12F are schematic diagrams of a method of manufacturing a display substrate according to an embodiment of the present disclosure.
  • a method of manufacturing a display substrate according to some embodiments of the present disclosure will be described with reference to FIGS. 12A to 12F, in which some details that are the same as those of the embodiment shown in FIGS. 11A to 11J are omitted.
  • a method of manufacturing a display substrate includes: forming a sacrificial layer 28 on a support substrate 27; forming a first conductive portion 13 on the sacrificial layer 28; and forming a first conductive portion 13 on the first conductive portion 13.
  • the first dielectric layer 14 covers the first conductive portion 13; the substrate 10 is formed on the first dielectric layer 14; the barrier layer 25 is formed on the substrate 10; the buffer layer 26 is formed on the barrier layer 25; Forming a conductive structure 24; forming a first sub-dielectric layer 151 on the conductive structure 24; forming a gate electrode 113 on the first sub-dielectric layer 151; forming a second sub-dielectric layer 152 on the gate electrode 113; The active layer 112 is formed on the dielectric layer 152.
  • the conductive structure 24 may form a storage capacitor with the gate electrode 113.
  • the method of manufacturing a display substrate according to an embodiment of the present disclosure may further include patterning to form the first opening 16 and the through hole V1.
  • the first opening 16 passes through the first sub-dielectric layer 151, the second sub-dielectric layer 152, the buffer layer 26 and the barrier layer 25.
  • the through hole V1 penetrates the substrate 10 and the first dielectric layer 14, and reaches the upper surface of the first conductive portion 13.
  • the method for manufacturing a display substrate may further include forming a first conductive structure 12 and a source/drain electrode 111 of a thin film transistor on the active layer 112 and the second sub-dielectric layer 152. And the fourth conductive part 21.
  • the first conductive structure 12, the source/drain electrode 111 of the thin film transistor, and the fourth conductive part 21 may be formed by a single film forming process.
  • a second material layer may be formed on the second sub-dielectric layer 152, and then the second material layer may be patterned (for example, etched) to form the first conductive structure 12 and the source/drain electrodes 111 of the thin film transistor.
  • the fourth conductive part 21 may further include forming a first conductive structure 12 and a source/drain electrode 111 of a thin film transistor on the active layer 112 and the second sub-dielectric layer 152.
  • the fourth conductive part 21 may be formed by a single film forming process.
  • a second material layer may be formed on the second sub
  • the method of manufacturing a display substrate according to an embodiment of the present disclosure may further include forming two dielectric layers 18 on the first conductive structure 12, the source/drain electrodes 111 of the thin film transistor, and the fourth conductive portion 21. Then, the first hole H1 and the second hole H2 may be formed in the second dielectric layer 18. The first hole H1 reaches the upper surface of the source/drain electrode 111. The second hole H2 of the fourth conductive portion reaches the upper surface of 21. Further, the second conductive portion 19 may be formed in the first hole H1 and the third conductive portion 20 may be formed in the second hole H2. Further, a third dielectric layer 22 can also be formed on the second dielectric layer 18.
  • the light shielding pattern 23 may be formed on the third dielectric layer 22.
  • the method of manufacturing the display substrate may further include disposing the light emitting element 17 above the first hole H1 and the second hole H2, wherein the first pole 171 and the second pole 172 of the light emitting element 17 are respectively located in the first hole H1 and the second hole H2 .
  • the method of manufacturing a display substrate according to an embodiment of the present disclosure may further include separating the sacrificial layer 28 from the substrate 10.
  • a laser lift-off method may be used to separate the sacrificial layer 28 from the substrate 10.
  • the use of the sacrificial layer can solve the problem that the substrate 10 (for example, a flexible substrate such as PI) is difficult to peel from the supporting substrate (for example, a rigid substrate such as glass).
  • the method of manufacturing a display substrate according to an embodiment of the present disclosure may further include forming an integrated circuit 29 on a second side of the substrate 10 opposite to the first side.
  • the integrated circuit 29 is electrically connected to the first conductive portion 13.
  • the integrated circuit 29 can be used to provide driving and control signals to the display substrate.
  • a through hole provided in a substrate such as polyimide needs to be deliberately filled with organic material to fill the through hole, and the organic material filled in the through hole needs to undergo high temperature processing (for example, High temperatures are experienced when the active layer and source/drain electrodes are formed using the LTPS process).
  • high temperatures are experienced when the active layer and source/drain electrodes are formed using the LTPS process.
  • the thermal stability of organic materials is poor, which results in the organic materials filling the through-holes easily exploding when undergoing a high-temperature process.

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Abstract

本公开涉及一种显示基板、显示装置和制造显示基板的方法。所述显示基板包括：衬底，具有第一侧与所述第一侧相对的第二侧；通孔，设置在所述衬底中；薄膜晶体管，设置在所述衬底的所述第一侧上；第一导电结构（左侧的SD），设置在所述衬底的所述第一侧上，其中所述第一导电结构的第一子部分位于所述通孔中，其中，所述第一导电结构的材料与所述薄膜晶体管的源/漏电极的材料相同。

Description

显示基板、显示装置及制造显示基板的方法 技术领域
本公开涉及显示技术领域。更具体地，涉及一种显示基板、显示装置及制造显示基板的方法。
背景技术
全面屏技术逐渐成为手机等手持设备的主流技术，目前采用GOA(Gate Driver On Array)技术实现左右边框的窄型化，采用COF(Chip On Film)技术实现下边框的窄型化。但是显示屏正面仍然存在无法成为显示区的区域，不能实现较好的窄边框或者无边框效果。
发明内容
本公开的实施例提供了一种显示基板。所述显示基板，包括：衬底，具有第一侧与所述第一侧相对的第二侧；通孔，设置在所述衬底中；薄膜晶体管，设置在所述衬底的所述第一侧上；第一导电结构，设置在所述衬底的所述第一侧上，其中所述第一导电结构的第一子部分位于所述通孔中，其中，所述第一导电结构的材料与所述薄膜晶体管的源/漏电极的材料相同。
在一些实施例中，所述显示基板进一步包括第一导电部，所述第一导电部至少部分地位于所述通孔中且直接接触所述第一导电结构的所述第一子部分。
在一些实施例中，所述第一导电部的背离所述衬底的所述第一侧的表面与所述第二侧共面。
在一些实施例中，所述显示基板还包括位于所述衬底与所述第一导电部之间的第一介质层，所述第一介质层的背离所述衬底的所述第一侧的表面与所述第二侧共面。
在一些实施例中，所述显示基板还包括中间层；第一开口，贯穿所述中间层且与所述通孔连通，其中，所述第一导电结构的第二子部分至少部分覆盖所述第一开口的侧壁，并且其中，所述第一导电结构的第三子部分 位于所述中间层的远离所述衬底的表面。
在一些实施例中，所述薄膜晶体管的源/漏电极至少与所述第一导电结构的所述第三子部分同层设置。
在一些实施例中，所述显示基板进一步包括发光元件，所述发光元件包括第一极和第二极，其中，所述第一极和所述第二极中的一个与所述源/漏电极电连接。
在一些实施例中，所述显示基板进一步包括第二介质层，其中，所述第二介质层覆盖所述源/漏电极和所述第一导电结构。
在一些实施例中，所述显示基板还包括第二导电部，其中，所述第二导电部通过位于所示第二介质层中的过孔与所述源/漏电极电连接。
在一些实施例中，所述显示基板进一步包括第三介质层，其中，所述第三介质层至少覆盖所述第二导电部的侧表面。
在一些实施例中，所述显示基板进一步包括遮光图案，所述遮光图案位于所述第三介质层的远离所述衬底的一侧，并且所述遮光图案在所述衬底上的正投影至少覆盖所述第一导电部在所述衬底上的正投影。
在一些实施例中，所述显示基板进一步包括设置在所述衬底的所述第二侧上的集成电路，其中，所述集成电路与所述第一导电部电连接。
本公开的实施例还提供了一种显示装置。所述显示装置包括如上所述的显示基板。
本公开的实施例还提供了一种制造显示基板的方法。所述制造显示基板的方法包括：提供衬底；在所述衬底中形成通孔；在所述衬底的第一侧上形成第一导电结构和薄膜晶体管，其中，所述第一导电结构的第一子部分位于所述通孔中，所述第一导电结构与所述薄膜晶体管的源电极和漏电极采用一次成膜工艺制备。
在一些实施例中，提供衬底包括：提供支撑基板；在所述支撑基板上设置牺牲层；在所述牺牲层上形成第一导电部；形成第一介质层(pad1上的绿色的PVX)以覆盖所述第一导电部和所述牺牲层；在所述第一介质层上涂覆第一材料以形成所述衬底。
在一些实施例中，所述制造显示基板的方法进一步包括：在所述衬底上形成中间层；其中，在所述衬底中形成所述通孔包括：形成穿过所述中间层和所述衬底的孔以暴露所述第一导电部的表面。
在一些实施例中，形成所述第一导电结构包括：在所述中间层上形成导电材料层；对所述导电材料层进行构图工艺以形成所述第一导电结构、所述源/漏电极。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本公开的一些实施例，而非对本公开的限制，其中：
图1为根据本公开的实施例的显示基板的示意图；
图2为根据本公开的实施例的显示基板的示意图；
图3为根据本公开的实施例的显示基板的示意图；
图4为根据本公开的实施例的显示基板的示意图；
图5为根据本公开的实施例的显示基板的示意图；
图6为根据本公开的实施例的显示基板的示意图；
图7为根据本公开的实施例的显示基板的俯视示意图；
图8为根据本公开的实施例的拼接显示装置的示意图；
图9为根据本公开的实施例的制造显示基板的方法的流程示意图；
图10A-图10E为根据本公开的实施例的制造显示基板的方法的的示意图；
图11A-图11J为根据本公开的实施例的制造显示基板的方法的示意图；
图12A-图12F为根据本公开的实施例的制造显示基板的方法的示意图。
具体实施方式
为了使本公开的实施例的目的、技术方案和优点更加清楚，下面将接 合附图，对本公开的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其他实施例，也都属于本公开保护的范围。
当介绍本公开的元素及其实施例时，冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素。用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素。
出于下文表面描述的目的，如其在附图中被标定方向那样，术语“上”、“下”、“左”、“右”“垂直”、“水平”、“顶”、“底”及其派生词应涉及发明。术语“上覆”、“在……顶上”、“定位在……上”或者“定位在……顶上”意味着诸如第一结构的第一要素存在于诸如第二结构的第二要素上，其中，在第一要素和第二要素之间可存在诸如界面结构的中间要素。术语“接触”意味着连接诸如第一结构的第一要素和诸如第二结构的第二要素，而在两个要素的界面处可以有或者没有其它要素。
图1为根据本公开的实施例的显示基板的示意图。如图1所示，根据本公开的实施例的显示基板包括：衬底10，其具有第一侧S1与第一侧S1相对的第二侧S2；通孔V1，其设置在衬底10中；薄膜晶体管11，其设置在衬底10的第一侧S1上；第一导电结构12，其设置在衬底10的第一侧S1上，其中第一导电结构12的第一子部分121位于通孔V1中。在本公开的实施例中，第一导电结构12的材料可以与薄膜晶体管的源/漏电极111的材料相同。薄膜晶体管11在衬底10上的正投影通孔V1在衬底10上的正投影不重合。
通过本公开的实施例，可以实现无边框或者窄边框的显示基板。例如，可以在显示基板的背侧(如，第二侧)设置电路等。可以提高有效显示区的面积，提升显示品质。
图2为根据本公开的实施例的显示基板的示意图。如图2所示，根据本公开的实施例的显示基板还包括第一导电部13。如图2所示，第一导电部13至少部分地位于通孔V1中且直接接触第一导电结构12的第一子部 分121。第一导电部13可以向第一导电结构12提供电连接。根据本公开的实施例，第一导电部13可以至少部分覆盖通孔V1的侧壁。
在一些实施例中，所述第一导电部13的背离衬底10的第一侧S1的表面S131与该第二侧S2共面。第一导电部13可以包括单层或者叠层结构。例如，第一导电部可以包括下列的至少一种：Ti/Al/Ti叠层或Cu。
衬底10可以包括柔性衬底。例如，衬底10可以包括聚酰亚胺(polymide，PI)衬底。
图3为根据本公开的实施例的显示基板的示意图。如图3所示，根据本公开的实施例的显示基板还可以包括位于衬底10与第一导电部13之间的第一介质层14。如图所示，第一介质层14的背离衬底10的第一侧S1的表面S141与第二侧S2共面。第一介质层14可以用作钝化层。例如，第一介质层14可以包括硅氮化物(SiNx)。
图4为根据本公开的实施例的显示基板的示意图。如图4所示，根据本公开的实施例的显示基板还可以包括中间层15和第一开口16。中间层15可以位于衬底10和第一导电结构12之间。从图4可以看出，第一开口16贯穿中间层15且与通孔V1连通。第一导电结构12的第二子部分122可以至少部分覆盖第一开口16的侧壁161。第一导电结构12的第三子部分123位于中间层15的远离衬底10的表面。
在一些实施例中，薄膜晶体管的源/漏电极111可以至少与第一导电结构12的第三子部分123同层设置。这里的“同层设置”也可被称为可以由相同的膜层形成。
图5为根据本公开的实施例的显示基板的示意图。如图5所示，根据本公开的实施例的显示基板还可以包括发光元件17。发光元件17可以包括第一极171和第二极172，其中，第一极171和第二极172中的一个与源/漏电极111电连接。图5以第一极171与源/漏电极111电连接为示例。可以理解，第一极171和第二极172的位置可以互换。第一极171可以为正极和负极中的一者，第二极172可以为正极和负极中的另一者。
在一些实施例中，显示基板还可以包括第二介质层18。第二介质层18 可以覆盖源/漏电极111和第一导电结构12。在一些实施例中，显示基板还可以包括第二导电部19。第二介质层18可以具有暴露源/漏电极111的第一孔。第二导电部19可以通过位于第二介质层18中的该第一孔与源/漏电极111电连接。
在一些实施例中，显示基板还可以包括第三导电部20和第四导电部21。如图5所示，第四导电部21可以位于中间层15的背离衬底10的一侧。第四导电部21可以与源/漏电极111包括相同的材料。在一些实施例中，第四导电部21可以与源/漏电极111同层设置，即，二者可以由同一膜层形成。第二介质层18可以进一步具有暴露第四导电部21的第二孔。第三导电部20可以通过该第二孔而与第四导电部21电连接。通过这样的设置，可以便捷地给发光元件17提供显示信号。
在一些实施例中，进一步包括第三介质层22。第三介质层22至少覆盖所述第二导电部19的侧表面。第三介质层22可以防止第二导电部19的侧表面被氧化。从图5中可以看出，第三介质层22位于第二介质层18的背离衬底10的一侧上。
在一些实施例中，显示基板进一步包括遮光图案23。遮光图案23可以位于第三介质层22的远离所述衬底的一侧上。遮光图案23在衬底10上的正投影至少覆盖第一导电部13在衬底10上的正投影。遮光图案23可以遮挡不希望的光入射或反射，能够提高显示效果。
在一些实施例中，中间层15可以包括在衬底10的第一侧上沿远离衬底10的方向依次设置的第一子介质层151和第二子介质层152。薄膜晶体管的源/漏极电极111包括位于中间层15的背离衬底10的一侧上的第一部分111a以及穿过中间层15的至少一部分而到达有源层112的第二部分111b。第一子介质层151覆盖有源层112并作为薄膜晶体管的栅极介质层。栅极电极113位于第一子介质层151的背离衬底10的一侧且被第二子介质152覆盖。
中间层15还可以包括设置在第二子介质层152的远离衬底10的一侧上的第三子介质层153。显示基板还包括位于第二子介质层152的背离衬 底10的一侧上且被第三子介质153覆盖的导电结构24。导电结构24在衬底10上的正投影与栅极电极113与在衬底10上的正投影至少部分重叠。导电结构24可以与栅极电极113形成存储电容。
图6为根据本公开的实施例的显示基板的示意图。如图6所示，中间层15可以包括在衬底10的第一侧上的沿远离衬底10的方向而依次设置的第一子介质层151和第二子介质层152。第二子介质层152可以被用作栅极介质层。第一子介质层151和第二子介质层152可以包括氧化硅和氮化硅中的至少一种。栅极电极113可以位于第一子介质层151的背离衬底10的一侧上且被第二子介质层152覆盖。有源层112位于第二子介质层152的背离10衬底的一侧上。显示基板还可以包括位于衬底10上并被第一子介质层151覆盖的导电结构24。导电结构24在衬底10上的正投影与栅极电极113与在衬底10上的正投影至少部分重叠，从而能与栅极电极113形成存储电容。
在一些实施例中，如图5和图6所示，显示基板还可以包括位于衬底10和第一子介质层151之间且沿远离衬底10的方向依次设置的阻挡层25和缓冲层26。阻挡层25可以包括硅氧化物(SiOx)。缓冲层26可以包括硅氧化物(SiOx)或硅氮化物(SiNx)的至少一种。
缓冲层和阻挡层都可以阻止热量扩散。这样一方面可以防止热量对下层材料的影响，另一方面可以给有源层的晶化工艺起到保温的作用。阻挡层26可以包括氧化硅和氮化硅中的至少一种。缓冲层还可以防止杂质进入到有源层，以避免对薄膜晶体管的特性的影响。
在一些实施例中，显示基板可以进一步包括在衬底10的与第一侧相对的第二侧上的集成电路29。集成电路29与第一导电部13电连接。集成电路29可以用来向显示基板输入/输出电学信号。
图7为根据本公开的实施例的显示基板的俯视示意图。根据本公开的实施例的显示基板100的区域AA’为显示区，区域BB’也可以为显示区。在常规的技术中，区域BB’为显示基板的边框区，需要设置布线等，无法实现显示。然而，本公开的实施例中，BB’区可以同时实现设置布线(即， 用作接合(bonding)区)和显示的功能。从而，本公开的实施例能够实现无边框或者窄边框的显示基板。例如，可以在显示基板的背侧(如，第二侧)设置电路等，解决了电路占据有效显示面积的问题。可以提高有效显示区的面积，提升显示品质。
本公开的实施例还提供了一种显示装置。
图8为根据本公开的实施例的显示装置的示意图。如图8所示，根据本公开的实施例的显示装置200包括如上所述的显示基板100。应该理解，虽然附图仅示出了显示装置200包括一个显示基板的100的情况，但显示装置200同样可以包括拼接到一起的多个显示基板100。
本公开的实施例还提供了一种制造显示基板的方法。图9为根据本公开的实施例的制造显示基板的方法的流程示意图。如图9所示，根据本公开的实施例的制造显示基板的方法包括：
S1、提供衬底；
S3、在所述衬底中形成通孔；
S5、在所述衬底的第一侧上形成第一导电结构和薄膜晶体管，其中，所述第一导电结构的第一子部分位于所述通孔中，所述第一导电结构与所述薄膜晶体管的源电极和漏电极采用一次成膜工艺制备，换言之，由同一膜层通过一次构图工艺形成。
图10A-图10E为根据本公开的实施例的制造显示基板的方法的的示意图。
如图10A所示，提供支撑基板27。支撑基板可以例如为玻璃。
如图10B所示，在支撑基板27上设置牺牲层(De-bonding layer，DBL)28。牺牲层可以包括类PI材料。
如图10C所示，在牺牲层28上形成第一导电部13。
如图10D所示，形成第一介质层14以覆盖第一导电部13和牺牲层28；
如图10E所示，在第一介质层14上涂覆第一材料10’以形成衬底10。例如可以涂覆液态的聚酰亚胺，然后进行固化来形成衬底。
在一些实施例中，如图4所示，制造显示基板的方法可以进一步包括 在衬底10上形成中间层15。在衬底中形成通孔可以包括形成穿过中间层15和衬底10的孔以暴露第一导电部13的表面。形成所述第一导电结构可以包括：在中间层上形成导电材料层；对导电材料层进行构图工艺以形成第一导电结构和源/漏电极。
图11A-图11J为根据本公开的实施例的制造显示基板的方法的示意图。
如图11A所示，根据本公开的实施例的制造显示基板的方法可以包括：在支撑基板27上形成牺牲层28；在牺牲层28上形成第一导电部13；在第一导电部13上形成第一介质层14以覆盖第一导电部13；在第一介质层14上形成衬底10；在衬底10上形成阻挡层25；在阻挡层25上形成缓冲层26；在缓冲层26上形成有源层112。缓冲层和阻挡层都可以阻止热量扩散。这样一方面可以防止热量对下层材料的影响，另一方面可以给有源层的晶化工艺起到保温的作用。阻挡层26可以包括氧化硅和氮化硅中的至少一者。缓冲层还可以防止杂质进入到有源层，以避免对薄膜晶体管的特性的影响。
如图11B所示，根据本公开的实施例的制造显示基板的方法还可以包括：在有源层112上形成第一子介质层151；在第一子介质层151上形成薄膜晶体管的栅极电极113；在栅极电极113上形成第二子介质层152；在第二子介质层上形成导电结构24；在导电结构上形成第三子介质层153。
如图11C所示，根据本公开的实施例的制造显示基板的方法进一步包括：例如通过蚀刻，形成第一开口16、通孔V1、第一连接孔CH1和第二连接孔CH2。第一开口16穿过第一子介质层151、第二子介质层152、第三子介质层153、缓冲层26和阻挡层25。通孔V1穿过衬底10和第一介质层14，并且到达第一导电部13的上表面。可以用同一掩模进行1～3次刻蚀来形成第一开口16和通孔V1。第一连接孔CH1和第二连接孔CH2穿过第一子介质层151、第二子介质层152和第三子介质层153而到达有源层112的上表面。
如图11D所示，根据本公开的实施例的制造显示基板的方法进一步包括：在第三子介质层153上形成第一导电结构12、薄膜晶体管的源/漏极电极111和第四导电部21。在一些实施例中，第一导电结构12、薄膜晶体 管的源/漏极电极111和第四导电部21可以由一次成膜工艺形成。具体而言，可以在第三子介质层153上形成第二材料层，然后对第二材料层进行构图(例如，刻蚀)以形成第一导电结构12、薄膜晶体管的源/漏极电极111和第四导电部21。薄膜晶体管的源/漏极电极111可以包括位于中间层15的背离衬底10的一侧上的第一部分111a以及穿过中间层15的至少一部分而到达有源层112的第二部分111b。
如图11E所示，根据本公开的实施例的制造显示基板的方法进一步包括：在第一导电结构12、薄膜晶体管的源/漏极电极111和第四导电部21上形成第二介质层18。
如图11F所示，根据本公开的实施例的制造显示基板的方法进一步包括：在第二介质层18中形成第一孔H1和第二孔H2。第一孔H1到达源/漏电极111的上表面。第四导电部第二孔H2到达21的上表面。
根据本公开的实施例的制造显示基板的方法进一步包括在第一孔H1中形成第二导电部19以及在第二孔H2中形成第三导电部20。第二导电部19可以通过位于第二介质层18中的该第一孔H1与源/漏电极111电连接。第三导电部20可以通过该第二孔H2而与第四导电部21电连接。
根据本公开的实施例的制造显示基板的方法进一步包括在第二介质层18上形成第三介质层22。第三介质层22可以覆盖第二部19和第三导电部20的侧表面，从而防止二者的侧表面被氧化。
如图11G所示，根据本公开的实施例的制造显示基板的方法进一步包括在第三介质层22上(即，在第三介质层22的远离衬底10的一侧)形成遮光图案23。遮光图案23在衬底10上的正投影至少覆盖第一导电部13在衬底10上的正投影。
根据本公开的实施例的制造显示基板的方法可以进一步包括在第一孔H1和第二孔H2上方设置发光元件17，其中发光元件17的第一极171和第二极172分别位于第一孔H1和第二孔H2中。第一极171可以通过第一孔H1与源/漏电极111电连接。第二极172可以通过第二孔H2与第四导电部21电连接。
如图11H所示，根据本公开的实施例的制造显示基板的方法可以进一步包括在绑定发光元件17。发光元件17可以包括微LED。发光元件17也可以包括其它发光元件，例如，LED、有机发光二极管(Organic Light-Emitting Diode，OLED)等。
如图11I所示，根据本公开的实施例的制造显示基板的方法可以进一步包括将牺牲层28与衬底10分离。例如，可以采用激光剥离(Laser Lift Off，LLO)的方式来将牺牲层28与衬底10分离。具体而言，经过LLO的高能量照射后，牺牲层28的材料会分解，从而容易将牺牲层28与衬底10分离。
如图11J所示，根据本公开的实施例的制造显示基板的方法可以进一步包括在衬底10的与第一侧相对的第二侧上形成集成电路29。集成电路29与第一导电部13电连接。集成电路29可以用来控制显示基板的操作，例如，用于驱动和控制显示面板。
图12A-图12F为根据本公开的实施例的制造显示基板的方法的示意图。下面将结合图12A-图12F为描述根据本公开的一些实施例的制造显示基板的方法，其中，有些与图11A-图11J中所示出的实施例的相同的细节被省略。
如图12A所示，根据本公开的实施例的制造显示基板的方法包括：在支撑基板27上形成牺牲层28；在牺牲层28上形成第一导电部13；在第一导电部13上形成第一介质层14以覆盖第一导电部13；在第一介质层14上形成衬底10；在衬底10上形成阻挡层25；在阻挡层25上形成缓冲层26；在缓冲层26上形成导电结构24；在导电结构24上形成第一子介质层151；在第一子介质层151上形成栅极电极113；在栅极电极113上形成第二子介质层152；在第二子介质层152上形成有源层112。导电结构24可以与栅极电极113形成存储电容。
如图12B所示，根据本公开的实施例的制造显示基板的方法可以进一步包括进行构图以形成第一开口16和通孔V1。第一开口16穿过第一子介质层151、第二子介质层152、缓冲层26和阻挡层25。通孔V1穿过衬底 10和第一介质层14，并且到达第一导电部13的上表面。
如图12C所示，根据本公开的实施例的制造显示基板的方法可以进一步包括在有源层112、第二子介质层152上形成第一导电结构12、薄膜晶体管的源/漏极电极111和第四导电部21。第一导电结构12、薄膜晶体管的源/漏极电极111和第四导电部21可以由一次成膜工艺形成形成。具体而言，可以在第二子介质层152上形成第二材料层，然后对第二材料层进行构图(例如，刻蚀)以形成第一导电结构12、薄膜晶体管的源/漏极电极111和第四导电部21。
如图12D所示，根据本公开的实施例的制造显示基板的方法可以进一步包括在第一导电结构12、薄膜晶体管的源/漏极电极111和第四导电部21上形成二介质层18。然后，可以在在第二介质层18中形成第一孔H1和第二孔H2。第一孔H1到达源/漏电极111的上表面。第四导电部第二孔H2到达21的上表面。进一步地，可以在第一孔H1中形成第二导电部19以及在第二孔H2中形成第三导电部20。进一步地，还可以在第二介质层18上形成第三介质层22。接着，可以在第三介质层22上形成遮光图案23。制造显示基板的方法可以进一步包括在第一孔H1和第二孔H2上方设置发光元件17，其中发光元件17的第一极171和第二极172分别位于第一孔H1和第二孔H2中。
如图12E所示，根据本公开的实施例的制造显示基板的方法可以进一步包括将牺牲层28与衬底10分离。例如，可以采用激光剥离的方式来将牺牲层28与衬底10分离。采用牺牲层能解决衬底10(例如，诸如PI的柔性衬底)难以从支撑基板(例如，诸如玻璃的刚性衬底)上剥离的问题。
如图12F所示，根据本公开的实施例的制造显示基板的方法可以进一步包括在衬底10的与第一侧相对的第二侧上形成集成电路29。集成电路29与第一导电部13电连接。集成电路29可以用来向显示基板提供驱动和控制信号。
在一些方案中，需要在设置在诸如聚酰亚胺的衬底中的通孔刻意填充有机材料，来将该通孔填平，并且填充在通孔中的有机材料需要经过高温 处理(例如，利用LTPS工艺形成有源层、源/漏极电极时会经历高温)。然而，有机材料热稳定性差，导致填充通孔的有机材料在经历高温工艺时容易爆膜。对于本公开的实施例，无需刻意在通孔中施加上述有机材料。因此，能够避免爆膜，提高显示基板的性能。
已经描述了某特定实施例，这些实施例仅通过举例的方式展现，而且不旨在限制本公开的范围。事实上，本文所描述的新颖实施例可以以各种其它形式来实施；此外，可在不脱离本公开的精神下，做出以本文所描述的实施例的形式的各种省略、替代和改变。所附权利要求以及它们的等价物旨在覆盖落在本公开范围和精神内的此类形式或者修改。

Claims (17)

  1. 一种显示基板，包括：
    衬底，具有第一侧与所述第一侧相对的第二侧；
    通孔，设置在所述衬底中；
    薄膜晶体管，设置在所述衬底的所述第一侧上；
    第一导电结构，设置在所述衬底的所述第一侧上，其中所述第一导电结构的第一子部分位于所述通孔中，
    其中，所述第一导电结构的材料与所述薄膜晶体管的源/漏电极的材料相同。
  2. 根据权利要求1所述的显示基板，进一步包括第一导电部，所述第一导电部至少部分地位于所述通孔中且直接接触所述第一导电结构的所述第一子部分。
  3. 根据权利要求2所述的显示基板，其中，所述第一导电部的背离所述衬底的所述第一侧的表面与所述第二侧共面。
  4. 根据权利要求3所述的显示基板，进一步包括位于所述衬底与所述第一导电部之间的第一介质层，所述第一介质层的背离所述衬底的所述第一侧的表面与所述第二侧共面。
  5. 根据权利要求3所述的显示基板，进一步包括：
    中间层；
    第一开口，贯穿所述中间层且与所述通孔连通，
    其中，所述第一导电结构的第二子部分至少部分覆盖所述第一开口的侧壁，并且其中，所述第一导电结构的第三子部分位于所述中间层的远离所述衬底的表面。
  6. 根据权利要求5所述的显示基板，其中，所述薄膜晶体管的源/漏电极至少与所述第一导电结构的所述第三子部分同层设置。
  7. 根据权利要求6所述的显示基板，进一步包括发光元件，所述发光元件包括第一极和第二极，其中，所述第一极和所述第二极中的一个与所述源/漏电极电连接。
  8. 根据权利要求7所述的显示基板，进一步包括第二介质层，其中，所述第二介质层覆盖所述源/漏电极和所述第一导电结构。
  9. 根据权利要求8所述的显示基板，进一步包括第二导电部，其中，所述第二导电部通过位于所示第二介质层中的过孔与所述源/漏电极电连接。
  10. 根据权利要求9所述的显示基板，进一步包括第三介质层，其中，所述第三介质层至少覆盖所述第二导电部的侧表面。
  11. 根据权利要求10所述的显示基板，进一步包括遮光图案，所述遮光图案位于所述第三介质层的远离所述衬底的一侧，并且所述遮光图案在所述衬底上的正投影至少覆盖所述第一导电部在所述衬底上的正投影。
  12. 根据权利要求1-11中任一项所述的显示基板，进一步包括设置在所述衬底的所述第二侧上的集成电路，其中，所述集成电路与所述第一导电部电连接。
  13. 一种显示装置，包括根据权利要求1-12中任一项所述的显示基板。
  14. 一种制造显示基板的方法，包括：
    提供衬底；
    在所述衬底中形成通孔；
    在所述衬底的第一侧上形成第一导电结构和薄膜晶体管，其中，所述第一导电结构的第一子部分位于所述通孔中，所述第一导电结构与所述薄膜晶体管的源电极和漏电极采用一次成膜工艺制备。
  15. 根据权利要求14所述的方法，其中，提供衬底包括：
    提供支撑基板；
    在所述支撑基板上设置牺牲层；
    在所述牺牲层上形成第一导电部；
    形成第一介质层以覆盖所述第一导电部和所述牺牲层；
    在所述第一介质层上涂覆第一材料以形成所述衬底。
  16. 根据权利要求15所述的方法，进一步包括：
    在所述衬底上形成中间层；
    其中，在所述衬底中形成所述通孔包括：
    形成穿过所述中间层和所述衬底的孔以暴露所述第一导电部的表面。
  17. 根据权利要求16所述的方法，其中，形成所述第一导电结构包括：
    在所述中间层上形成导电材料层；
    对所述导电材料层进行构图工艺以形成所述第一导电结构、所述源/漏电极。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104460147A (zh) * 2014-11-20 2015-03-25 深圳市华星光电技术有限公司 薄膜晶体管阵列基板、制造方法及显示装置
JP2015072361A (ja) * 2013-10-03 2015-04-16 株式会社ジャパンディスプレイ 表示装置及びその製造方法
CN107342299A (zh) * 2017-08-30 2017-11-10 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置及其制作方法
CN108511487A (zh) * 2017-02-28 2018-09-07 三星显示有限公司 显示设备
CN109904080A (zh) * 2019-03-20 2019-06-18 北京京东方显示技术有限公司 一种驱动背板及其制作方法、显示装置
US20190271873A1 (en) * 2018-03-01 2019-09-05 Panasonic Liquid Crystal Display Co., Ltd. Display device and manufacturing method for display device
CN110310575A (zh) * 2019-06-28 2019-10-08 云谷（固安）科技有限公司 一种显示面板及其制作方法和显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9012900B2 (en) * 2012-12-26 2015-04-21 Lg Display Co., Ltd. Organic light emitting diode display device and method of fabricating the same
CN107256870A (zh) 2017-06-09 2017-10-17 京东方科技集团股份有限公司 一种阵列基板及制作方法、柔性显示面板、显示装置
KR102390447B1 (ko) * 2017-07-28 2022-04-26 삼성디스플레이 주식회사 표시장치용 기판, 유기발광표시장치 및 유기발광표시장치의 제조방법
KR20200049115A (ko) * 2018-10-31 2020-05-08 엘지디스플레이 주식회사 투명 유기 발광 표시 장치 및 이의 제조방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015072361A (ja) * 2013-10-03 2015-04-16 株式会社ジャパンディスプレイ 表示装置及びその製造方法
CN104460147A (zh) * 2014-11-20 2015-03-25 深圳市华星光电技术有限公司 薄膜晶体管阵列基板、制造方法及显示装置
CN108511487A (zh) * 2017-02-28 2018-09-07 三星显示有限公司 显示设备
CN107342299A (zh) * 2017-08-30 2017-11-10 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置及其制作方法
US20190271873A1 (en) * 2018-03-01 2019-09-05 Panasonic Liquid Crystal Display Co., Ltd. Display device and manufacturing method for display device
CN109904080A (zh) * 2019-03-20 2019-06-18 北京京东方显示技术有限公司 一种驱动背板及其制作方法、显示装置
CN110310575A (zh) * 2019-06-28 2019-10-08 云谷（固安）科技有限公司 一种显示面板及其制作方法和显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4002467A4 *

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