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WO2020001026A1 - 像素驱动电路及方法、显示面板 - Google Patents

像素驱动电路及方法、显示面板 Download PDF

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Publication number
WO2020001026A1
WO2020001026A1 PCT/CN2019/074024 CN2019074024W WO2020001026A1 WO 2020001026 A1 WO2020001026 A1 WO 2020001026A1 CN 2019074024 W CN2019074024 W CN 2019074024W WO 2020001026 A1 WO2020001026 A1 WO 2020001026A1
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WO
WIPO (PCT)
Prior art keywords
node
signal
transistor
circuit
pixel driving
Prior art date
Application number
PCT/CN2019/074024
Other languages
English (en)
French (fr)
Inventor
张陶然
莫再隆
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/485,131 priority Critical patent/US11404001B2/en
Publication of WO2020001026A1 publication Critical patent/WO2020001026A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel driving circuit, a pixel driving method, and a display panel.
  • OLED Organic Light Emitting Diode
  • the threshold voltages of the driving transistors in different positions may be different due to process variations. And as the working time is extended and the use environment is changed, the threshold voltage of the driving transistor will drift, resulting in uneven light emission of the OLED display, and the appearance of the display screen will deteriorate.
  • An object of the present disclosure is to provide a pixel driving circuit, a pixel driving method, and a display panel.
  • a pixel driving circuit for driving an electroluminescent element including:
  • a first switching circuit connected to the first node and configured to be turned on in response to a scanning signal to transmit an input signal to the first node;
  • a compensation circuit connected to the second node and configured to be turned on in response to the scan signal to transmit a data signal to the second node;
  • a power control circuit connected to the third node and configured to be turned on in response to the first control signal to transmit the first power signal to the third node;
  • a second switching circuit connected to the first node and the second node and configured to be turned on in response to a second control signal to connect the first node and the second node;
  • the driving circuit is connected to the second node, the third node, and the fourth node, and is configured to be turned on in response to a signal of the second node, and output a driving current under the action of the signal of the third node To the fourth node;
  • An isolation circuit connected to the fourth node and configured to be turned on in response to the second control signal to transmit the driving current to the electroluminescent element;
  • An energy storage circuit is connected between the first node and the third node.
  • the first switching circuit includes a first transistor, wherein:
  • a first terminal of the first transistor receives the input signal, a second terminal is connected to the first node, and a control terminal receives the scan signal.
  • the compensation circuit includes a second transistor, wherein:
  • a first terminal of the second transistor receives the data signal, a second terminal is connected to the second node, and a control terminal receives the scan signal.
  • the power control circuit includes a third transistor, wherein:
  • a first terminal of the third transistor receives the first power signal, a second terminal is connected to the third node, and a control terminal receives the first control signal.
  • the second switching circuit includes a fourth transistor, wherein:
  • a first terminal of the fourth transistor is connected to the first node, a second terminal is connected to the second node, and a control terminal receives the second control signal.
  • the driving circuit includes a driving transistor, wherein:
  • a first terminal of the driving transistor is connected to the third node, a second terminal is connected to the fourth node, and a control terminal is connected to the second node.
  • the isolation circuit includes a fifth transistor, wherein:
  • a first terminal of the fifth transistor is connected to the fourth node, a second terminal is connected to the electroluminescent element, and a control terminal receives the second control signal.
  • the energy storage circuit includes a storage capacitor, wherein:
  • a first end of the storage capacitor is connected to the first node, and a second end is connected to the third node.
  • the pixel driving circuit further includes:
  • a third switching circuit is connected to the fourth node and is configured to be turned on in response to the scan signal to transmit the input signal to the fourth node.
  • the third switching circuit includes a sixth transistor; wherein:
  • a first terminal of the sixth transistor receives the input signal, a second terminal is connected to the fourth node, and a control terminal receives the scan signal.
  • the pixel driving circuit further includes:
  • a third switching circuit is connected to the fourth node and is configured to be turned on in response to the scan signal to transmit a second power signal to the fourth node.
  • the third switching circuit includes a sixth transistor; wherein:
  • a first terminal of the sixth transistor receives the second power signal, a second terminal is connected to the fourth node, and a control terminal receives the scan signal.
  • the transistors are all N-type thin film transistors or are all P-type thin film transistors.
  • the thin film transistor is one or more of an amorphous silicon thin film transistor, a polysilicon thin film transistor, and an amorphous-indium gallium zinc oxide thin film transistor.
  • a pixel driving circuit for driving an electroluminescent element including:
  • a first transistor connected to the first node and configured to be turned on in response to a scan signal to transmit an input signal to the first node;
  • a second transistor connected to the second node and configured to be turned on in response to the scan signal to transmit a data signal to the second node;
  • a third transistor connected to the third node and configured to be turned on in response to the first control signal to transmit a first power signal to the third node;
  • a fourth transistor connected to the first node and the second node and configured to be turned on in response to a second control signal to connect the first node and the second node;
  • the driving transistor is connected to the second node, the third node, and the fourth node, and is configured to be turned on in response to a signal of the second node, and output a driving current under the action of the signal of the third node.
  • a fifth transistor connected to the fourth node and configured to be turned on in response to the second control signal to transmit the driving current to the electroluminescent element;
  • a storage capacitor is connected between the first node and the third node.
  • the first switching circuit and the compensation circuit are turned on by using the scanning signal, and the power control circuit is turned on by using the first control signal, so that the data signal is written into the second node and all the signals are turned on.
  • the input signal and the first power signal charge the energy storage circuit;
  • the first switching circuit and the compensation circuit are turned on by using the scanning signal, so that the third node discharges a compensation signal through the driving circuit;
  • the compensation signal is the data signal and the driving Difference in threshold voltage of the circuit;
  • the second switch circuit and the isolation circuit are turned on by using the second control signal, so that the signal of the first node is written into the second node, so that the driving circuit is in the first node.
  • the signal of the two nodes is turned on, and the driving current is output to the electroluminescent element through the isolation circuit under the signal of the third node.
  • the voltage of the input signal is zero.
  • the pixel driving circuit further includes a third switching circuit connected to the fourth node; the pixel driving method includes:
  • the third switching circuit is turned on by using the scanning signal, so that the third node is discharged to the compensation signal through the driving circuit and the third switching circuit.
  • the pixel driving circuit further includes a third switching circuit connected to the fourth node; the pixel driving method includes:
  • the third switching circuit is turned on by using the scanning signal so that a second power signal is transmitted to the fourth node.
  • a display panel is provided, including any one of the foregoing.
  • FIG. 1 is a schematic diagram of a pixel driving circuit in the related art
  • FIG. 2 is a current simulation diagram of a pixel driving circuit in the related art
  • FIG. 3 is a schematic diagram of a pixel driving circuit according to the present disclosure.
  • FIG. 4 is a schematic diagram of a specific structure of a pixel driving circuit according to the present disclosure.
  • FIG. 5 is a working timing diagram of a pixel driving circuit provided in an exemplary embodiment of the present disclosure
  • FIG. 6 is an equivalent circuit diagram of a pixel driving circuit provided in the present disclosure during a charging phase
  • FIG. 7 is an equivalent circuit diagram of a pixel driving circuit provided in the present disclosure in a compensation phase
  • FIG. 8 is an equivalent circuit diagram of a pixel driving circuit provided in the present disclosure at a light emitting stage
  • FIG. 9A is a schematic diagram of capacitor charging of the pixel driving circuit in FIG. 1; FIG.
  • FIG. 9B is a schematic diagram of a capacitor charging circuit of a pixel driving circuit provided by the present disclosure.
  • FIG. 10 is a schematic diagram of another specific structure of a pixel driving circuit provided by the present disclosure.
  • FIG. 11 is a voltage simulation diagram of each node in a pixel driving circuit provided by the present disclosure.
  • FIG. 12 is a driving current simulation diagram of a pixel driving circuit provided by the present disclosure.
  • the pixel circuit compensation in related technologies is mostly a PMOS voltage compensation technology.
  • a compensation circuit with a small number of transistors (such as 7T1C) cannot compensate power IR Drop.
  • a compensation circuit with a large number of transistors can compensate the threshold voltage and power IR. Drop compensates, but the pixel structure is more complicated (such as 8T1C).
  • the gates of the transistors M1 and M2 are controlled by the potential V1 of the N1 point.
  • the source S and the drain D of the transistor M2 are not directly connected to the power supply voltage, and are affected by the transistor M3 and the transistor.
  • M1 turns on the write state control and is in a long-term floating state.
  • the pixel driving circuit may include:
  • the first switching circuit 100 is connected to the first node N1 and is configured to be turned on in response to the scan signal G1 to transmit the input signal Vinit to the first node N1;
  • the compensation circuit 200 is connected to the second node N2 and is configured to be turned on in response to the scan signal G1 to transmit a data signal Vdata to the second node N2;
  • the power control circuit 300 is connected to the third node N3 and is configured to be turned on in response to the first control signal G2 to transmit the first power signal Vdd to the third node N3;
  • the second switching circuit 400 is connected to the first node N1 and the second node N2, and is configured to be turned on in response to a second control signal G3 to connect the first node N1 and the second node N2;
  • the driving circuit 500 is connected to the second node N2, the third node N3, and the fourth node N4, and is configured to be turned on in response to a signal of the second node N2, and a signal at the third node N3
  • the driving current is output to the fourth node N4 under
  • the isolation circuit 600 is connected to the fourth node N4 and is configured to be turned on in response to the second control signal G3 to transmit the driving current to the electroluminescent element L;
  • the energy storage circuit 700 is connected between the first node N1 and the third node N2.
  • the pixel driving circuit may further include a third switching circuit 800 connected to the fourth node N4 and configured to be turned on in response to the scan signal G1 to transmit the input signal Vinit to the first node N4.
  • the third switching circuit is provided to prevent the electroluminescent element from turning on in advance due to the leakage current of the isolation circuit.
  • the third switching circuit by connecting the third switching circuit to the second power signal Vss, the uncombined carriers on the interface of the light emitting layer can be reduced or eliminated, and the factors causing the aging of the light emitting material can be removed. Extend the life of luminescent materials.
  • the third node discharges the compensation signal through the driving transistor in the driving circuit.
  • the threshold voltage Vth of the driving transistor is compensated to eliminate the influence of the threshold voltage of the driving transistor on the driving current, to ensure that the driving current output by each pixel driving circuit is consistent, thereby ensuring the uniformity of the display brightness of each pixel;
  • the pixel driving circuit In the compensation phase the influence of the first power signal on the voltage between the control terminal and the first terminal of the driving transistor is eliminated, thereby eliminating the influence of the IR voltage drop of the power supply on the display brightness of each pixel, so as to ensure the output of each pixel driving circuit in the light-emitting phase
  • the driving current is the same to ensure the uniformity of the display brightness of each pixel.
  • the first switching circuit includes a first transistor
  • the compensation circuit includes a second transistor
  • the power control circuit includes a third transistor
  • the second switching circuit includes a fourth transistor.
  • the driving circuit includes a driving transistor
  • the isolation circuit includes a fifth transistor
  • the energy storage circuit includes a storage capacitor
  • the third switching circuit includes a sixth transistor.
  • the first to sixth transistors and the driving transistor each have a control terminal, a first terminal, and a second terminal.
  • the connection relationship between the first to sixth transistors (M1 to M6) and the driving transistor M7 in the pixel driving circuit is as follows:
  • the first switching circuit 100 includes a first transistor M1.
  • a first terminal of the first transistor M1 receives the input signal Vinit, a second terminal is connected to the first node N1, and a control terminal receives the scan signal G1.
  • the compensation circuit 200 includes a second transistor M2.
  • a first terminal of the second transistor M2 receives the data signal Vdata, a second terminal is connected to the second node N2, and a control terminal receives the scan signal G1.
  • the power control circuit 300 includes a third transistor M3.
  • a first terminal of the third transistor M3 receives a first power signal Vdd, a second terminal is connected to the third node N3, and a control terminal receives the first control signal G2.
  • the second switching circuit 400 includes a fourth transistor M4.
  • a first terminal of the fourth transistor M4 is connected to the first node N1, a second terminal is connected to the second node N2, and a control terminal receives the second control.
  • the driving circuit 500 includes a driving transistor M7. A first terminal of the driving transistor M7 is connected to the third node N3, a second terminal is connected to the fourth node N4, and a control terminal is connected to the second node N2.
  • the isolation circuit 600 includes a fifth transistor M5, a first terminal of the fifth transistor M5 is connected to the fourth node N4, a second terminal is connected to a first electrode of the electroluminescent element L, and a control terminal receives The second control signal G3 is described.
  • the energy storage circuit 700 includes a storage capacitor C, a first end of the storage capacitor is connected to the first node N1, and a second end is connected to the third node N3.
  • a second electrode of the electroluminescent element L is connected to a second power signal Vss.
  • the third switching circuit 800 includes a sixth transistor M6. A first terminal thereof receives the input signal Vinit, a second terminal is connected to the fourth node N4, and a control terminal receives the scan signal G1.
  • a first terminal of the sixth transistor M6 may receive a second power signal Vss, a second terminal is connected to the fourth node N4, and a control terminal receives the scan signal G1.
  • each transistor may be a gate, the first terminal may be a source, and the second terminal may be a drain; or, the first terminal and the second terminal of the transistor may be interchanged.
  • all transistors can be N-type thin film transistors or P-type thin film transistors. It should be noted that, for different transistor types, the level signal at each signal terminal needs to be adjusted and changed accordingly.
  • the thin film transistor may be one or more of an amorphous silicon thin film transistor, a polysilicon thin film transistor, and an amorphous-indium gallium zinc oxide thin film transistor.
  • the first terminal of the transistor may be a source, and the second terminal of the transistor may be a drain.
  • the first end of the transistor may be a drain, and the second end of the transistor may be a source.
  • the above-mentioned transistor may also be another type of transistor, which is not particularly limited in this exemplary embodiment.
  • each transistor may be an enhancement type transistor or a depletion type transistor, which is not particularly limited in this exemplary embodiment. It should be noted that, since the source and the drain of the transistor are symmetrical, the source and the drain of the transistor can be interchanged.
  • the driving transistor M7 has a control terminal, a first terminal, and a second terminal.
  • the control terminal of the driving transistor M7 may be a gate
  • the first terminal may be a source
  • the second terminal may be a drain.
  • the control terminal of the driving transistor M7 may be a gate
  • the first terminal may be a drain
  • the second terminal may be a source.
  • the driving transistor M7 may be an enhancement type driving transistor or a depletion type driving transistor, which is not particularly limited in this exemplary embodiment.
  • the type of the storage capacitor C may be selected according to a specific circuit.
  • it may be a MOS capacitor, a metal capacitor, or a dual poly capacitor, and the present exemplary embodiment does not specifically limit this.
  • the electroluminescent element L is a current-driven electroluminescent element, which is controlled to emit light by the current flowing through the driving transistor M7.
  • the electroluminescent element may be an OLED, but the electroluminescence in the exemplary embodiment The element L is not limited to this.
  • the electroluminescent element L has a first electrode and a second electrode.
  • the first pole of the electroluminescent element L may be an anode, and the second pole may be a cathode.
  • the first and second electrodes of the electroluminescent element L are also interchangeable.
  • a pixel driving method is also provided for driving a pixel driving circuit as shown in FIGS. 3 and 4.
  • the transistors are P-type thin film transistors
  • the first end of the transistor is a source
  • the second end of the transistor is a drain
  • the on-signals of the transistors are low-level signals
  • the off-signals of the transistors are High-level signal.
  • the driving timing diagram shows a scan signal G1, a first control signal G2, a second control signal G3, and a data signal Vdata.
  • the first power signal Vdd maintains a high-level signal
  • the second power signal Vss maintains a low-level signal
  • the input signal Vinit maintains a low-level signal.
  • the working process of the pixel driving circuit may specifically include the following stages:
  • the first switching circuit and the compensation circuit may be turned on by a scanning signal, and the power control circuit may be turned on by a first control signal, so that the data signal is written into the second node and The input signal and the first power signal are used to charge the energy storage circuit.
  • the scanning signal G1 and the first control signal G2 at the T1 stage are low-level signals
  • the second control signal G3 is a high-level signal
  • the data signal Vdata is a low-level signal
  • the first transistor M1, the second transistor M2, and the sixth transistor M6 are turned on by the low-level signal of the scan signal G1, and the third transistor M3 is turned on by the low-level signal of the first control signal G2.
  • the fourth transistor M4 and the fifth transistor M5 are in an off state.
  • the input signal Vinit can be transmitted to the first node N1 through the first transistor M1
  • the data signal Vdata can be written to the second node N2 through the second transistor M2
  • the first power signal Vdd can be written to the third node M3.
  • the driving transistor M7 can be turned on, and the voltage signal of the third node N3 can be written into the fourth node N4 through the driving transistor M7, and the input signal Vinit can be written into the fourth node N4.
  • the voltage signal of the first node is an input signal Vinit
  • the voltage signal of the second node is a data signal Vdata
  • the voltage of the third node is Vdd
  • the voltage signal of the fourth node is Vdd-Vinit.
  • the data signal Vdata can change the gate voltage of the driving transistor M7 through the second transistor M2.
  • W / L is the width-length ratio of the driving transistor M7
  • ⁇ is the hole mobility
  • Cox is the gate capacitance
  • V GS is the gate-source voltage of the driving transistor M7
  • Vth is the threshold voltage of the driving transistor M7. Since V GS of the driving transistor M7 is Vdata-Vdd, the calculation formula of the driving current of the driving transistor M7 is
  • the charging process is shown in FIG. 9B.
  • the first plate of the storage capacitor C can be directly powered by the input signal Vinit, and the second plate of the storage capacitor C can be directly powered by the first power signal Vdd.
  • Charging can achieve the effect of directly charging the capacitor through the power signal, which improves the capacitor charging speed and charging efficiency, and shortens the charging time.
  • the scanning signal G1 can be used to turn on the first switching circuit and the compensation circuit, so that the third node N3 can discharge the compensation signal through the driving circuit.
  • the signal G1 is a low-level signal
  • the first control signal G2 and the second control signal G3 are high-level signals
  • the data signal Vdata is a high-level signal. Therefore, the first transistor M1, the second transistor M2, and the sixth transistor M6 are at The low-level signal of the scanning signal G1 is turned on, and the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are in an off state.
  • the input signal Vinit can be written into the first node N1 through the first transistor M1
  • the data signal Vdata can be written into the second node N2 through the second transistor M2
  • the input signal Vinit can be written into the first node N2 through the sixth transistor M6.
  • the third switching circuit is turned on by the scanning signal, so that the third node N3 is discharged to the compensation signal through the driving circuit and the third switching circuit.
  • the driving transistor M7 since the driving transistor M7 has VGS ⁇ Vth after being charged, the second plate of the storage capacitor C can be discharged, so that a current flows to the sixth transistor M6.
  • the leakage current is reduced to enter the electroluminescent element L or OLED, so that a black frame can be added, which has a certain improvement effect on short-term afterimages.
  • the sixth transistor M6 is turned on, which can prevent the leakage current of the fifth transistor M5 from causing the electroluminescent element L device to turn on in advance.
  • the third switching circuit may include a sixth transistor M6.
  • a first terminal of the sixth transistor receives the second power signal Vss, and a second terminal is connected to the first transistor.
  • the four nodes N4, the control end receives the scanning signal G1.
  • the sixth transistor M6 can be turned on in response to the low-level signal of the scan signal G1 to transmit the second power signal Vss to the fourth node N4. This is equivalent to connecting the first end and the second end of the electroluminescent element L.
  • the cathode and the anode of the electroluminescence element L can be short-circuited by this connection method to eliminate uncomposited carriers on the interface of the light emitting layer.
  • the carrier removes the factors that cause the aging of the luminescent material, thereby extending the life of the luminescent material.
  • the second control signal can be used to turn on the second switching circuit and the isolation circuit, so that the signal of the first node is written to the second node, so that the driving circuit is at the desired location.
  • the signal from the second node is turned on, and a driving current is output to the electroluminescent element through the isolation circuit under the signal from the third node.
  • the scanning signal G1 is a high-level signal
  • the first control signal G2, the second control signal G3, and the data signal are all low-level signals.
  • the first transistor M1, the second transistor M2, and the sixth transistor M6 are turned off, and the third transistor M3 is turned on by the low-level signal of the first control signal G2.
  • the fourth transistor M4 and the fifth transistor M5 are turned on by the low-level signal of the second control signal G3.
  • the gate voltage of the second transistor M2 is Vinit
  • the third transistor M3 is turned on
  • the capacitor C is switched to adjust the gate voltage of the driving transistor M7 to Vinit + Vdd-Vdata + Vth, and VGS of the driving transistor M7.
  • Vinit-Vdata the first power signal Vdd and the driving voltage Vth are cancelled to achieve the purpose of compensating IR Drop and Vth.
  • the driving current output by the driving transistor is independent of the threshold voltage Vth of the driving transistor M7 and the first power signal Vdd. Therefore, in the compensation phase, the scan signal G1 is used to turn on the first switching circuit 100 and the compensation circuit 200, so that the third node N3 discharges the compensation signal through the driving transistor M7 in the driving circuit 500, and writes Vdata and Vth to the first Three nodes, that is, compensating the threshold voltage Vth of the driving transistor M7, eliminating the influence of the threshold voltage Vth of the driving transistor M7 on the driving current, ensuring that the driving current output by each pixel driving circuit is consistent, and thereby ensuring the uniformity of the display brightness of each pixel, At the same time, the influence of the first power signal Vdd on the voltage between the control terminal and the first terminal of the driving transistor M7 is eliminated, thereby eliminating the influence of the IR drop of the wire on the display brightness of each pixel, so as to ensure the output of each pixel driving circuit at the light-emitting stage.
  • the driving current is
  • full P-type thin-film transistors has the following advantages: for example, it has a strong ability to suppress noise; for example, it is low-level conduction, and low-level is easy to achieve in charge management; for example, P-type thin-film transistors have a simple process and relatively low price; P-type thin film transistors have better stability and so on.
  • all transistors are P-type thin film transistors; however, those skilled in the art can easily obtain a pixel driving circuit in which all transistors are N-type thin film transistors according to the pixel driving circuit provided by the present disclosure. .
  • all the transistors may be N-type thin film transistors. Since the transistors are all N-type thin film transistors, the turn-on signals of the transistors are all high levels, and the first ends of the transistors are all Is the drain, and the second end of the transistor is the source.
  • the pixel driving circuit provided in the present disclosure can also be changed to a CMOS (Complementary Metal Oxide Semiconductor) circuit, etc., which is not limited to the pixel driving circuit provided in this embodiment, and is not repeated here.
  • CMOS Complementary Metal Oxide Semiconductor
  • the exemplary embodiment further provides a display panel including the pixel driving circuit described above.
  • the display panel includes: a plurality of scanning lines for providing a scanning signal; a plurality of data lines for providing a data signal; a plurality of pixel driving circuits electrically connected to the scanning lines and the data lines; and at least one of the pixels
  • the driving circuit includes any one of the pixel driving circuits described above in this exemplary embodiment.
  • the display panel may include, for example, any product or component having a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, and a navigator.
  • the threshold voltage Vth of the driving transistor M7 can be compensated, and the influence of the threshold voltage Vth of the driving transistor M7 on the driving current can be eliminated to ensure each
  • the driving current output by the pixel driving circuit is consistent, thereby ensuring the uniformity of the display brightness of each pixel, and at the same time eliminating the influence of the first power signal Vdd on the voltage between the control terminal and the first terminal of the driving transistor M7, thereby eliminating the IR drop of the wire.
  • the influence on the display brightness of each pixel is to ensure that the driving current output by the driving circuit of each pixel is consistent at the light emitting stage, and the uniformity of the display brightness of each pixel is ensured.
  • modules or circuits of the device for action execution are mentioned in the detailed description above, this division is not mandatory.
  • the features and functions of two or more modules or circuits described above may be embodied in one module or circuit.
  • the features and functions of a module or circuit described above can be further divided into multiple modules or circuits to be embodied.

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Abstract

一种像素驱动电路及像素驱动方法、显示面板。该像素驱动电路包括第一开关电路、补偿电路、电源控制电路、第二开关电路、驱动电路、隔离电路以及储能电路。

Description

像素驱动电路及方法、显示面板
交叉引用
本申请要求于2018年6月26日提交的申请号为201810673489.7的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路及像素驱动方法、显示面板。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)作为一种电流型发光器件，因其所具有的自发光、快速响应、宽视角和可制作在柔性衬底上等特点越来越多地被应用于高性能显示领域当中。
但是驱动晶体管在制作过程中，由于工艺偏差会导致不同位置的驱动晶体管的阈值电压存在差异。并且随着工作时间延长及使用环境改变，驱动晶体管的阈值电压会发生漂移，导致OLED显示器的发光不均匀，使显示画面的观感变差。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种像素驱动电路及像素驱动方法、显示面板。
根据本公开的一个方面，提供一种像素驱动电路，用于驱动电致发光元件，所述像素驱动电路包括：
第一开关电路，与第一节点连接，用于响应扫描信号而导通，以将输入信号传输至所述第一节点；
补偿电路，与第二节点连接，用于响应所述扫描信号而导通，以将 数据信号传输至所述第二节点；
电源控制电路，与第三节点连接，用于响应第一控制信号而导通，以将第一电源信号传输至所述第三节点；
第二开关电路，与所述第一节点以及第二节点连接，用于响应第二控制信号而导通，以联通所述第一节点和第二节点；
驱动电路，与所述第二节点、所述第三节点及第四节点连接，用于响应所述第二节点的信号而导通，并在所述第三节点的信号的作用下输出驱动电流至所述第四节点；
隔离电路，与所述第四节点连接，用于响应所述第二控制信号而导通，以将所述驱动电流传输至所述电致发光元件；
储能电路，连接与所述第一节点和所述第三节点之间。
在本公开的一种示例性实施例中，所述第一开关电路包括第一晶体管，其中：
所述第一晶体管的第一端接收所述输入信号，第二端与所述第一节点连接，控制端接收所述扫描信号。
在本公开的一种示例性实施例中，所述补偿电路包括第二晶体管，其中：
所述第二晶体管的第一端接收所述数据信号，第二端连接所述第二节点，控制端接收所述扫描信号。
在本公开的一种示例性实施例中，所述电源控制电路包括第三晶体管，其中：
所述第三晶体管的第一端接收所述第一电源信号，第二端连接所述第三节点，控制端接收所述第一控制信号。
在本公开的一种示例性实施例中，所述第二开关电路包括第四晶体管，其中：
所述第四晶体管的第一端连接所述第一节点，第二端连接所述第二节点，控制端接收所述第二控制信号。
在本公开的一种示例性实施例中，所述驱动电路包括驱动晶体管，其中：
所述驱动晶体管的第一端连接所述第三节点，第二端连接所述第四 节点，控制端连接所述第二节点。
在本公开的一种示例性实施例中，所述隔离电路包括第五晶体管，其中：
所述第五晶体管的第一端连接所述第四节点，第二端与所述电致发光元件连接，控制端接收所述第二控制信号。
在本公开的一种示例性实施例中，所述储能电路包括存储电容，其中：
所述存储电容的第一端连接所述第一节点，第二端连接所述第三节点。
在本公开的一种示例性实施例中，所述像素驱动电路还包括：
第三开关电路，与所述第四节点连接，用于响应所述扫描信号而导通，以将所述输入信号传输至所述第四节点。
在本公开的一种示例性实施例中，所述第三开关电路包括第六晶体管；其中：
所述第六晶体管的第一端接收所述输入信号，第二端连接所述第四节点，控制端接收所述扫描信号。
在本公开的一种示例性实施例中，所述像素驱动电路还包括：
第三开关电路，与所述第四节点连接，用于响应所述扫描信号而导通，以将第二电源信号传输至所述第四节点。
在本公开的一种示例性实施例中，所述第三开关电路包括第六晶体管；其中：
所述第六晶体管的第一端接收所述第二电源信号，第二端连接所述第四节点，控制端接收所述扫描信号。
在本公开的一种示例性实施例中，所述晶体管均为N型薄膜晶体管或者均为P型薄膜晶体管。
在本公开的一种示例性实施例中，所述薄膜晶体管为非晶硅薄膜晶体管、多晶硅薄膜晶体管以及非晶-氧化铟镓锌薄膜晶体管中的一种或多种。
根据本公开的一个方面，提供一种像素驱动电路，用于驱动电致发光元件，所述像素驱动电路包括：
第一晶体管，与第一节点连接，用于响应扫描信号而导通，以将输入信号传输至所述第一节点；
第二晶体管，与第二节点连接，用于响应所述扫描信号而导通，以将数据信号传输至所述第二节点；
第三晶体管，与第三节点连接，用于响应第一控制信号而导通，以将第一电源信号传输至所述第三节点；
第四晶体管，与所述第一节点以及第二节点连接，用于响应第二控制信号而导通，以联通所述第一节点和第二节点；
驱动晶体管，与所述第二节点、所述第三节点及第四节点连接，用于响应所述第二节点的信号而导通，并在所述第三节点的信号的作用下输出驱动电流至所述第四节点；
第五晶体管，与所述第四节点连接，用于响应所述第二控制信号而导通，以将所述驱动电流传输至所述电致发光元件；
存储电容，连接于所述第一节点和所述第三节点之间。
根据本公开的一个方面，提供一种像素驱动方法，用于驱动上述任意一项所述的像素驱动电路，所述像素驱动方法包括：
在充电阶段，利用所述扫描信号导通所述第一开关电路以及补偿电路，利用第一控制信号导通所述电源控制电路，以使所述数据信号写入所述第二节点以及使所述输入信号以及第一电源信号对所述储能电路进行充电；
在补偿阶段，利用所述扫描信号导通所述第一开关电路以及补偿电路，以使所述第三节点通过所述驱动电路放电补偿信号；所述补偿信号为所述数据信号和所述驱动电路的阈值电压之差；
在发光阶段，利用所述第二控制信号导通所述第二开关电路以及隔离电路，以将所述第一节点的信号写入所述第二节点，以使所述驱动电路在所述第二节点的信号的作用下导通，并在所述第三节点的信号的作用下通过所述隔离电路向所述电致发光元件输出驱动电流。
在本公开的一种示例性实施例中，所述输入信号的电压为0。
在本公开的一种示例性实施例中，所述像素驱动电路还包括与所述第四节点连接的第三开关电路；所述像素驱动方法包括：
在所述补偿阶段，利用所述扫描信号导通所述第三开关电路，以使所述第三节点通过所述驱动电路以及所述第三开关电路放电至所述补偿信号。
在本公开的一种示例性实施例中，所述像素驱动电路还包括与所述第四节点连接的第三开关电路；所述像素驱动方法包括：
在所述补偿阶段，利用所述扫描信号导通所述第三开关电路，以使第二电源信号传输至所述第四节点根据本公开的一个方面，提供一种显示面板，包括上述任意一项所述的像素驱动电路。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
附图说明
通过参照附图来详细描述其示例性实施例，本公开的上述和其它特征及优点将变得更加明显。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1为相关技术中的像素驱动电路示意图；
图2为相关技术中像素驱动电路的电流仿真图；
图3为本公开一种像素驱动电路的示意图；
图4为本公开一种像素驱动电路的具体结构示意图；
图5为本公开一示例性实施例中提供的像素驱动电路的工作时序图；
图6为本公开提供的像素驱动电路在充电阶段的等效电路图；
图7为本公开提供的像素驱动电路在补偿阶段的等效电路图；
图8为本公开提供的像素驱动电路在发光阶段的等效电路图；
图9A为图1中的像素驱动电路的电容充电示意图；
图9B为本公开提供的像素驱动电路的电容充电示意图；
图10为本公开提供的像素驱动电路的另一种具体结构示意图；
图11为本公开提供的像素驱动电路中各节点的电压仿真图；
图12为本公开提供的像素驱动电路的驱动电流仿真图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的实施例；相反，提供这些实施例使得本公开将全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免模糊本公开的各方面。
此外，附图仅为本公开的示意性图解，并非一定是按照比例绘制。图中相同的附图标记标识相同或相似的部分，因而将省略对它们的重复描述。
发明人发现，显示器各像素所处的位置不同会导致电源的压降(IR Drop)不同，从而对驱动OLED的电流产生影响。如果不能对阈值电压和电源IR Drop进行补偿，则会导致OLED显示器的发光不均匀，使显示画面的观感变差。
相关技术中的像素电路补偿多数为PMOS电压补偿技术，所用的晶体管数少的补偿电路(如7T1C)不能对电源IR Drop进行补偿，所使用晶体管数量多的补偿电路虽然能对阈值电压和电源IR Drop进行补偿，但是像素结构较为复杂(如8T1C)。如图1所示的电压补偿电路，晶体管M1和晶体管M2的栅极均受控于N1点电位VN，其中晶体管M2源级S和漏极D都没有跟电源电压直接连接，受晶体管M3和晶体管M1开启写入状态控制，处于长期floating状态，对于晶体管M2，其开关特性稳定性较差，写入电流不稳定，如图2所示。其次，由于电路进行适当简化，没有Vdd写入进行补偿，对于高PPI、大尺寸面板，对于电流的长程均一性存在问题，会导致OLED显示器的发光不均匀，影响产品质量。最后，由于传统电压补偿电路，通过对电容充电过程中写入了Vth补偿，当Driver-TFT(M3)处于临界状态时，即Vg＝Vdata+Vth时，电容充电完成，随着晶体管M3的开启能力减弱，充电效率逐渐降低，对 电容充电时间有较高要求。
本示例实施方式中提供了一种像素驱动电路，用于驱动电致发光元件，参照图3所示，该像素驱动电路可以包括：
第一开关电路100，与第一节点N1连接，用于响应扫描信号G1而导通，以将输入信号Vinit传输至所述第一节点N1；
补偿电路200，与第二节点N2连接，用于响应所述扫描信号G1而导通，以将数据信号Vdata传输至所述第二节点N2；
电源控制电路300，与第三节点N3连接，用于响应第一控制信号G2而导通，以将第一电源信号Vdd传输至所述第三节点N3；
第二开关电路400，与所述第一节点N1以及第二节点N2连接，用于响应第二控制信号G3而导通，以联通所述第一节点N1和第二节点N2；
驱动电路500，与所述第二节点N2、所述第三节点N3及第四节点N4连接，用于响应所述第二节点N2的信号而导通，并在所述第三节点N3的信号的作用下输出驱动电流至所述第四节点N4；
隔离电路600，与所述第四节点N4连接，用于响应所述第二控制信号G3而导通，以将所述驱动电流传输至所述电致发光元件L；
储能电路700，连接与所述第一节点N1和所述第三节点N2之间。
除此之外，像素驱动电路还可包括第三开关电路800，与所述第四节点N4连接，用于响应所述扫描信号G1而导通，以将所述输入信号Vinit传输至所述第四节点N4。通过设置第三开关电路可防止隔离电路的漏电流造成电致发光元件提前开启。除此之外，在另一种实施例中，通过将第三开关电路连接第二电源信号Vss，可减小或消除发光层界面上未复合的载流子，去除引起发光材料老化的因素，延长发光材料的使用寿命。
本示例性实施例中提供的像素驱动电路，一方面，通过在补偿阶段，利用扫描信号导通第一开关电路以及补偿电路，以使第三节点通过驱动电路中的驱动晶体管放电补偿信号，对驱动晶体管的阈值电压Vth进行补偿，消除驱动晶体管的阈值电压对驱动电流的影响，确保各像素驱动电路输出的驱动电流一致，进而保证各像素显示亮度的均一性；另一方面，该像素驱动电路在补偿阶段，消除第一电源信号对驱动晶体管的控 制端和第一端之间的电压的影响，从而消除电源IR压降对各像素显示亮度的影响，以在发光阶段确保各像素驱动电路输出的驱动电流一致，保证各像素显示亮度的均一性。
下面结合附图对本示例实施方式中的像素驱动电路各个电路进行详细的说明。结合图3和图4进行说明，所述第一开关电路包括第一晶体管，所述补偿电路包括第二晶体管，所述电源控制电路包括第三晶体管，所述第二开关电路包括第四晶体管，所述驱动电路包括驱动晶体管，所述隔离电路包括第五晶体管，所述储能电路包括存储电容，所述第三开关电路包括第六晶体管。
如图4中所示，以第一晶体管至第六晶体管以及驱动晶体管均具有控制端、第一端和第二端。在此基础上，上述像素驱动电路中的第一晶体管至第六晶体管(M1～M6)和驱动晶体管M7的连接关系如下：
所述第一开关电路100包括第一晶体管M1，所述第一晶体管M1的第一端接收所述输入信号Vinit，第二端与所述第一节点N1连接，控制端接收所述扫描信号G1。所述补偿电路200包括第二晶体管M2，所述第二晶体管M2的第一端接收所述数据信号Vdata，第二端连接所述第二节点N2，控制端接收所述扫描信号G1。所述电源控制电路300包括第三晶体管M3，所述第三晶体管M3的第一端接收第一电源信号Vdd，第二端连接所述第三节点N3，控制端接收所述第一控制信号G2。所述第二开关电路400包括第四晶体管M4，所述第四晶体管M4的第一端连接所述第一节点N1，第二端连接所述第二节点N2，控制端接收所述第二控制信号G3。所述驱动电路500包括驱动晶体管M7，所述驱动晶体管M7的第一端连接所述第三节点N3，第二端连接所述第四节点N4，控制端连接所述第二节点N2。所述隔离电路600包括第五晶体管M5，所述第五晶体管M5的第一端连接所述第四节点N4，第二端与所述电致发光元件L的第一极连接，控制端接收所述第二控制信号G3。所述储能电路700包括存储电容C，所述存储电容的第一端连接所述第一节点N1，第二端连接所述第三节点N3。所述电致发光元件L的第二极连接第二电源信号Vss。第三开关电路800包括第六晶体管M6，其第一端接收所述输入信号Vinit，第二端连接所述第四节点N4，控制端接收所述扫描信 号G1。在另一种实施例中，第六晶体管M6的第一端可接收第二电源信号Vss，第二端连接所述第四节点N4，控制端接收所述扫描信号G1。
需要说明的是，各晶体管的控制端可以为栅极、第一端可以为源极、第二端可以为漏极；或者，晶体管的第一端和第二端可以互换。在本示例实施方式中，所有晶体管均可以均采用N型薄膜晶体管或者P型薄膜晶体管。需要说明的是：针对不同的晶体管类型，各个信号端的电平信号需要相应的调整变化。所述薄膜晶体管可以为非晶硅薄膜晶体管、多晶硅薄膜晶体管以及非晶-氧化铟镓锌薄膜晶体管中的一种或多种。
例如，第一晶体管至第六晶体管均为P型薄膜晶体管时，所述晶体管的第一端均可以为源极，所述晶体管的第二端均可以为漏极。再例如，在所述第一晶体管至第六晶体管均为N型薄膜晶体管时，所述晶体管的第一端均可以为漏极，所述晶体管的第二端可以均为源极。需要说明的是，上述晶体管还可以为其他类型的晶体管，本示例性实施例对此不作特殊限定。
此外，各晶体管可以为增强型晶体管或者耗尽型晶体管，本示例性实施例对此不作特殊限定。需要说明的是，由于晶体管的源极和漏极对称，因此，晶体管的源极、漏极可以互换。
所述驱动晶体管M7具有控制端、第一端以及第二端。例如，驱动晶体管M7的控制端可以为栅极，第一端可以为源极、第二端可以为漏极。再例如，驱动晶体管M7的控制端可以为栅极，第一端可以为漏极，第二端可以为源极。此外，驱动晶体管M7可以为增强型驱动晶体管或耗尽型驱动晶体管，本示例性实施例对此不作特殊限定。
所述存储电容C的类型可以根据具体的电路进行选择。例如，可以为MOS电容、金属电容或双多晶电容等，本示例性实施例对此不作特殊限定。
所述电致发光元件L为电流驱动型电致发光元件，由流经驱动晶体管M7的电流控制其进行发光，例如，电致发光元件可为OLED，但本示例性实施例中的电致发光元件L不限于此。此外，电致发光元件L具有第一极和第二极。例如，电致发光元件L的第一极可以为阳极，第二极可以为阴极。除此之外，电致发光元件L的第一极和第二极也可互换。
在本公开的示例性实施例中，还提供了一种像素驱动方法，用于驱动如图3和图4所示的像素驱动电路。下面，以所述晶体管均为P型薄膜晶体管、驱动晶体管为P型驱动晶体管为例，结合图5所示的像素驱动电路的工作时序图对图3和图4中的像素驱动电路的工作过程加以详细的说明。由于晶体管均为P型薄膜晶体管，因此，晶体管的第一端均为源极，晶体管的第二端均为漏极，且晶体管的导通信号均为低电平信号，晶体管的关断信号为高电平信号。该驱动时序图绘示出了扫描信号G1、第一控制信号G2、第二控制信号G3、以及数据信号Vdata。除此之外，第一电源信号Vdd保持高电平信号，第二电源信号Vss保持低电平信号，输入信号Vinit保持低电平信号。
基于此，所述像素驱动电路的工作过程具体可以包括以下阶段：
在T1阶段即充电阶段，可利用扫描信号导通所述第一开关电路以及补偿电路，利用第一控制信号导通所述电源控制电路，以使所述数据信号写入所述第二节点以及使所述输入信号以及第一电源信号对所述储能电路进行充电。具体而言，如图6所示，由于T1阶段的扫描信号G1、第一控制信号G2为低电平信号，第二控制信号G3为高电平信号，数据信号Vdata为低电平信号，因此第一晶体管M1、第二晶体管M2以及第六晶体管M6在扫描信号G1的低电平信号的作用下导通，第三晶体管M3在第一控制信号G2的低电平信号作用下导通，第四晶体管M4和第五晶体管M5处于截止状态。如此一来，可将输入信号Vinit通过第一晶体管M1传输至第一节点N1，同时将数据信号Vdata通过第二晶体管M2写入第二节点N2，将第一电源信号Vdd通过第三晶体管M3写入第三节点N3，实现通过输入信号Vinit以及第一电源信号Vdd对所述储能电路中的存储电容C进行充电的功能。由于数据信号Vdata为低电平，可导通驱动晶体管M7，进而将第三节点N3的电压信号通过驱动晶体管M7写入第四节点N4，同时将输入信号Vinit写入第四节点N4。此时，第一节点的电压信号为输入信号Vinit，第二节点的电压信号为数据信号Vdata，第三节点的电压为Vdd，第四节点的电压信号为Vdd-Vinit。
其中，数据信号Vdata可通过第二晶体管M2改变驱动晶体管M7的 栅极电压。根据驱动电流
Figure PCTCN2019074024-appb-000001
其中W/L为驱动晶体管M7的宽长比，μ为空穴迁移率，Cox为栅极电容，V GS为驱动晶体管M7的栅源极电压，Vth为驱动晶体管M7的阈值电压。由于驱动晶体管M7的V GS为Vdata-Vdd，驱动晶体管M7的驱动电流的计算公式为
Figure PCTCN2019074024-appb-000002
在该阶段中，充电过程如图9B所示，可通过输入信号Vinit对存储电容C的第一极板直接进行电源充电，通过第一电源信号Vdd对存储电容C的第二极板直接进行电源充电，可实现通过电源信号直接对电容充电的效果，提高了电容充电速度和充电效率，缩短了充电时间。
在T2阶段即补偿阶段，可利用扫描信号G1导通第一开关电路以及补偿电路，以使第三节点N3通过驱动电路放电补偿信号；具体而言，如图7所示，由于T2阶段的扫描信号G1为低电平信号、第一控制信号G2以及第二控制信号G3为高电平信号，数据信号Vdata为高电平信号，因此第一晶体管M1、第二晶体管M2以及第六晶体管M6在扫描信号G1的低电平信号的作用下导通，第三晶体管M3、第四晶体管M4和第五晶体管M5处于截止状态。如此一来，可将输入信号Vinit通过第一晶体管M1写入第一节点N1，同时将数据信号Vdata通过第二晶体管M2写入第二节点N2，将输入信号Vinit通过第六晶体管M6写入第四节点N4。
通过扫描信号导通第三开关电路，以使第三节点N3通过驱动电路以及第三开关电路放电至补偿信号。具体而言，由于驱动晶体管M7在充电后VGS<Vth，可对存储电容C的第二极板进行放电，以使电流流向第六晶体管M6。当电容第二极板的电压为补偿电压即数据信号和驱动电路的阈值电压之差Vdata-Vth时，驱动晶体管M7的VGS＝Vth，驱动晶体管M7进入截止状态，在存储电容第二极板写入Vth，补偿完成。该阶段中通过开启第六晶体管M6，减少漏电流进入电致发光元件L或OLED，从而可增加一帧黑画面，对短时残像有一定改善作用。除此之外，第六晶体管M6开启，能够防止第五晶体管M5的漏电流造成电致发光元件L器件提前开启。
在本公开的另一实施例中，第三开关电路中可包括第六晶体管M6， 如图10中所示，第六晶体管的第一端接收第二电源信号Vss，第二端连接所述第四节点N4，控制端接收所述扫描信号G1。在补偿阶段，第六晶体管M6可响应扫描信号G1的低电平信号而导通，以将第二电源信号Vss传输至第四节点N4。如此一来，相当于将电致发光元件L的第一端和第二端相连接。对于电致发光元件L而言，在其发光层的载流子进行复合时，可通过这种连接方式将电致发光元件L的阴极和阳极短接，以消除发光层界面上未复合的载流子，去除引起发光材料老化的因素，从而延长发光材料的使用寿命。
在T3阶段即发光阶段，可利用所述第二控制信号导通第二开关电路以及隔离电路，以将所述第一节点的信号写入所述第二节点，以使所述驱动电路在所述第二节点的信号的作用下导通，并在所述第三节点的信号的作用下通过所述隔离电路向所述电致发光元件输出驱动电流。具体而言，如图8所示，扫描信号G1为高电平信号，第一控制信号G2、第二控制信号G3以及数据信号均为低电平信号。在扫描信号G1的高电平信号的作用下，第一晶体管M1、第二晶体管M2以及第六晶体管M6关断，第三晶体管M3在第一控制信号G2的低电平信号作用下导通，第四晶体管M4和第五晶体管M5在第二控制信号G3的低电平信号的作用下导通。如此一来，第二晶体管M2的栅极电压为Vinit，第三晶体管M3开启，电容C通过跳变，使得驱动晶体管M7的栅极电压调整为Vinit+Vdd-Vdata+Vth，驱动晶体管M7的VGS为Vinit-Vdata，抵消掉第一电源信号Vdd和驱动电压Vth，达到补偿IR Drop和Vth的目的，驱动晶体管M7输出的驱动电流为
Figure PCTCN2019074024-appb-000003
与Vdd和Vth无关。假设Vinit＝0V，则
Figure PCTCN2019074024-appb-000004
只与Vdata有关，达到对Vdd和Vth补偿的目的。本示例性实施例中通过将输入信号Vinit设置为0，能够消除输入信号对于驱动电流的影响。
由此可知，由于驱动晶体管输出的驱动电流与驱动晶体管M7的阈值电压Vth和第一电源信号Vdd均无关。因此，通过在补偿阶段，利用扫描信号G1导通第一开关电路100以及补偿电路200，以使第三节点N3通过驱动电路500中的驱动晶体管M7放电补偿信号，通过将Vdata 和Vth写入第三节点，即对驱动晶体管M7的阈值电压Vth进行补偿，消除驱动晶体管M7的阈值电压Vth对驱动电流的影响，确保各像素驱动电路输出的驱动电流一致，进而保证各像素显示亮度的均一性，同时消除第一电源信号Vdd对驱动晶体管M7的控制端和第一端之间的电压的影响，从而消除导线IR压降对各像素显示亮度的影响，以在发光阶段确保各像素驱动电路输出的驱动电流一致，保证各像素显示亮度的均一性。
采用全P型薄膜晶体管具有以下优点：例如对噪声抑制力强；例如由于是低电平导通，而充电管理中低电平容易实现；例如P型薄膜晶体管制程简单，相对价格较低；例如P型薄膜晶体管的稳定性更好等等。
需要说明的是：在上述具体的实施例中，所有晶体管均为P型薄膜晶体管；但本领域技术人员容易根据本公开所提供的像素驱动电路得到所有晶体管均为N型薄膜晶体管的像素驱动电路。在本公开的一种示例性实施方式中，所有晶体管可以均为N型薄膜晶体管，由于晶体管均为N型薄膜晶体管，因此，晶体管的导通信号均为高电平，晶体管的第一端均为漏极，晶体管的第二端均为源极。当然，本公开所提供的像素驱动电路也可以改为CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)电路等，并不局限于本实施例中所提供的像素驱动电路，这里不再赘述。
本示例实施方式还提供一种显示面板，包括上述的像素驱动电路。该显示面板包括：多条扫描线，用于提供扫描信号；多条数据线，用于提供数据信号；多个像素驱动电路，电连接于上述的扫描线和数据线；其中至少之一的像素驱动电路包括本示例实施方式中的上述任一像素驱动电路。其中，所述显示面板例如可以包括手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
通过在显示面板中设置本示例性实施例中如图4所示的像素驱动电路，可对驱动晶体管M7的阈值电压Vth进行补偿，消除驱动晶体管M7的阈值电压Vth对驱动电流的影响，确保各像素驱动电路输出的驱动电流一致，进而保证各像素显示亮度的均一性，同时消除第一电源信号Vdd对驱动晶体管M7的控制端和第一端之间的电压的影响，从而消除导线 IR压降对各像素显示亮度的影响，以在发光阶段确保各像素驱动电路输出的驱动电流一致，保证各像素显示亮度的均一性。
需要说明的是：所述显示面板中各模块电路的具体细节已经在对应的像素驱动电路中进行了详细的描述，因此这里不再赘述。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者电路，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者电路的特征和功能可以在一个模块或者电路中具体化。反之，上文描述的一个模块或者电路的特征和功能可以进一步划分为由多个模块或者电路来具体化。
此外，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本领域技术人员在考虑说明书及实践这里公开的实施例后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (20)

  1. 一种像素驱动电路，用于驱动电致发光元件，所述像素驱动电路包括：
    第一开关电路，与第一节点连接，用于响应扫描信号而导通，以将输入信号传输至所述第一节点；
    补偿电路，与第二节点连接，用于响应所述扫描信号而导通，以将数据信号传输至所述第二节点；
    电源控制电路，与第三节点连接，用于响应第一控制信号而导通，以将第一电源信号传输至所述第三节点；
    第二开关电路，与所述第一节点以及第二节点连接，用于响应第二控制信号而导通，以联通所述第一节点和第二节点；
    驱动电路，与所述第二节点、所述第三节点及第四节点连接，用于响应所述第二节点的信号而导通，并在所述第三节点的信号的作用下输出驱动电流至所述第四节点；
    隔离电路，与所述第四节点连接，用于响应所述第二控制信号而导通，以将所述驱动电流传输至所述电致发光元件；
    储能电路，连接于所述第一节点和所述第三节点之间。
  2. 根据权利要求1所述的像素驱动电路，所述第一开关电路包括第一晶体管，其中：
    所述第一晶体管的第一端接收所述输入信号，第二端与所述第一节点连接，控制端接收所述扫描信号。
  3. 根据权利要求1所述的像素驱动电路，所述补偿电路包括第二晶体管，其中：
    所述第二晶体管的第一端接收所述数据信号，第二端连接所述第二节点，控制端接收所述扫描信号。
  4. 根据权利要求1所述的像素驱动电路，所述电源控制电路包括第三晶体管，其中：
    所述第三晶体管的第一端接收所述第一电源信号，第二端连接所述第三节点，控制端接收所述第一控制信号。
  5. 根据权利要求1所述的像素驱动电路，所述第二开关电路包括第 四晶体管，其中：
    所述第四晶体管的第一端连接所述第一节点，第二端连接所述第二节点，控制端接收所述第二控制信号。
  6. 根据权利要求1所述的像素驱动电路，所述驱动电路包括驱动晶体管，其中：
    所述驱动晶体管的第一端连接所述第三节点，第二端连接所述第四节点，控制端连接所述第二节点。
  7. 根据权利要求1所述的像素驱动电路，所述隔离电路包括第五晶体管，其中：
    所述第五晶体管的第一端连接所述第四节点，第二端与所述电致发光元件连接，控制端接收所述第二控制信号。
  8. 根据权利要求1所述的像素驱动电路，所述储能电路包括存储电容，其中：
    所述存储电容的第一端连接所述第一节点，第二端连接所述第三节点。
  9. 根据权利要求1-6中任一所述的像素驱动电路，所述像素驱动电路还包括：
    第三开关电路，与所述第四节点连接，用于响应所述扫描信号而导通，以将所述输入信号传输至所述第四节点。
  10. 根据权利要求9所述的像素驱动电路，所述第三开关电路包括第六晶体管；其中：
    所述第六晶体管的第一端接收所述输入信号，第二端连接所述第四节点，控制端接收所述扫描信号。
  11. 根据权利要求1-6中任一所述的像素驱动电路，所述像素驱动电路还包括：
    第三开关电路，与所述第四节点连接，用于响应所述扫描信号而导通，以将第二电源信号传输至所述第四节点。
  12. 根据权利要求11所述的像素驱动电路，所述第三开关电路包括第六晶体管；其中：
    所述第六晶体管的第一端接收所述第二电源信号，第二端连接所述 第四节点，控制端接收所述扫描信号。
  13. 根据权利要求2～7任意一项或权利要求10或权利要求12所述的像素驱动电路，所述晶体管均为N型薄膜晶体管或者均为P型薄膜晶体管。
  14. 根据权利要求13所述的像素驱动电路，所述薄膜晶体管为非晶硅薄膜晶体管、多晶硅薄膜晶体管以及非晶-氧化铟镓锌薄膜晶体管中的至少一种。
  15. 一种像素驱动电路，用于驱动电致发光元件，所述像素驱动电路包括：
    第一晶体管，与第一节点连接，用于响应扫描信号而导通，以将输入信号传输至所述第一节点；
    第二晶体管，与第二节点连接，用于响应所述扫描信号而导通，以将数据信号传输至所述第二节点；
    第三晶体管，与第三节点连接，用于响应第一控制信号而导通，以将第一电源信号传输至所述第三节点；
    第四晶体管，与所述第一节点以及第二节点连接，用于响应第二控制信号而导通，以联通所述第一节点和第二节点；
    驱动晶体管，与所述第二节点、所述第三节点及第四节点连接，用于响应所述第二节点的信号而导通，并在所述第三节点的信号的作用下输出驱动电流至所述第四节点；
    第五晶体管，与所述第四节点连接，用于响应所述第二控制信号而导通，以将所述驱动电流传输至所述电致发光元件；
    存储电容，连接于所述第一节点和所述第三节点之间。
  16. 一种像素驱动方法，用于驱动权利要求1所述的像素驱动电路，所述像素驱动方法包括：
    在充电阶段，利用所述扫描信号导通所述第一开关电路以及补偿电路，利用第一控制信号导通所述电源控制电路，以使所述数据信号写入所述第二节点以及使所述输入信号以及第一电源信号对所述储能电路进行充电；
    在补偿阶段，利用所述扫描信号导通所述第一开关电路以及补偿电 路，以使所述第三节点通过所述驱动电路放电补偿信号；所述补偿信号为所述数据信号和所述驱动电路的阈值电压之差；
    在发光阶段，利用所述第二控制信号导通所述第二开关电路以及隔离电路，以将所述第一节点的信号写入所述第二节点，以使所述驱动电路在所述第二节点的信号的作用下导通，并在所述第三节点的信号的作用下通过所述隔离电路向所述电致发光元件输出驱动电流。
  17. 根据权利要求16所述的像素驱动方法，所述输入信号的电压为0V。
  18. 根据权利要求16所述的像素驱动方法，所述像素驱动电路还包括与所述第四节点连接的第三开关电路；所述像素驱动方法包括：
    在所述补偿阶段，利用所述扫描信号导通所述第三开关电路，以使所述第三节点通过所述驱动电路以及所述第三开关电路放电至所述补偿信号。
  19. 根据权利要求16所述的像素驱动方法，所述像素驱动电路还包括与所述第四节点连接的第三开关电路；所述像素驱动方法包括：
    在所述补偿阶段，利用所述扫描信号导通所述第三开关电路，以使第二电源信号传输至所述第四节点。
  20. 一种显示面板，包括权利要求1～15中任意一项所述的像素驱动电路。
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