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WO2021238470A1 - 像素电路及其驱动方法、显示面板 - Google Patents

像素电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2021238470A1
WO2021238470A1 PCT/CN2021/087044 CN2021087044W WO2021238470A1 WO 2021238470 A1 WO2021238470 A1 WO 2021238470A1 CN 2021087044 W CN2021087044 W CN 2021087044W WO 2021238470 A1 WO2021238470 A1 WO 2021238470A1
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WIPO (PCT)
Prior art keywords
terminal
transistor
node
sub
circuit
Prior art date
Application number
PCT/CN2021/087044
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English (en)
French (fr)
Inventor
汪锐
邱海军
尚飞
胡明
李少茹
高明
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/763,598 priority Critical patent/US11688348B2/en
Publication of WO2021238470A1 publication Critical patent/WO2021238470A1/zh
Priority to US18/320,042 priority patent/US12073787B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, and a display panel.
  • OLED organic light emitting diode
  • Micro LED micro light emitting diode
  • mini LED mini light emitting diode
  • other display devices have broad development prospects due to their self-luminous, high contrast, low energy consumption, wide viewing angle, and fast response speed.
  • an embodiment of the present disclosure provides a pixel circuit, which includes a driving sub-circuit, a first reset sub-circuit, a writing sub-circuit, a light-emitting device, and a light-emitting control sub-circuit.
  • the driving sub-circuit includes: a driving transistor and a storage capacitor; the gate of the driving transistor is connected to a first node, the first electrode of the driving transistor is connected to the second node, and the second electrode of the driving transistor is connected to the third node;
  • the storage capacitor includes a first storage electrode and a second storage electrode, the first storage electrode is connected to the first node, and the second storage electrode is connected to a first voltage terminal.
  • the first reset sub-circuit is connected to at least the third node, the first reset signal terminal and the initialization signal terminal; the first reset sub-circuit is configured to receive at least the first reset signal terminal in the initialization phase Under the control of the first reset signal, the initialization signal from the initialization signal terminal is transmitted to the third node.
  • the writing sub-circuit is connected to the first scanning terminal, the second scanning terminal, the data terminal, the first node, the second node, and the third node; the writing sub-circuit is configured to In the initialization phase, under the control of the first scan signal received by the first scan terminal, the initialization signal on the third node is transmitted to the first node to reset the first node ; In the data writing stage, under the control of the first scan signal received by the first scan terminal and the second scan signal received by the second scan terminal, the data signal received by the data terminal is written into To the first node and perform threshold voltage compensation on the driving transistor.
  • the light emitting device includes an anode and a cathode, and the cathode is connected to a second voltage terminal.
  • the light emission control sub-circuit is connected to the second node, the third node, the first voltage terminal, the first enable signal terminal, the second enable signal terminal, and the anode of the light emitting device;
  • the lighting control sub-circuit is configured to, in the lighting phase, under the control of the first enable signal received by the first enable signal terminal and the second enable signal received by the second enable signal terminal, the The voltage signal of the first voltage terminal is transmitted to the second node, and the current output by the driving transistor is transmitted to the light emitting device, so that the light emitting device emits light.
  • the pixel circuit further includes: a second reset sub-circuit.
  • the second reset sub-circuit is connected to the anode of the light-emitting device, the second reset signal terminal and the initialization signal terminal; the second reset sub-circuit is configured to be in the initialization phase or the data writing phase Under the control of the second reset signal received by the second reset signal terminal, the initialization signal from the initialization signal terminal is transmitted to the anode of the light-emitting device, and the anode is reset.
  • the first reset signal terminal and the second reset signal terminal are connected to the same reset signal terminal.
  • the light emission control sub-circuit includes a first sub-circuit and a second sub-circuit.
  • the first sub-circuit is connected to the second node, the first voltage terminal, and the first enable signal terminal; Under the control of the first enable signal of the terminal, the voltage signal of the first voltage terminal is transmitted to the second node;
  • the second sub-circuit is connected to the third node and the second enable signal terminal And the anode of the light-emitting device;
  • the second sub-circuit is configured to transmit the current output by the driving transistor under the control of the second enable signal at the second enable signal terminal in the light-emitting phase To the light-emitting device.
  • the first enable signal terminal and the second enable signal terminal are connected to the same enable signal terminal.
  • the initialization signal terminal is connected to the anode of the light emitting device.
  • the second sub-circuit is multiplexed with the first reset sub-circuit, and the first reset signal terminal and the second enable signal terminal are the same signal terminal; the signal terminal is configured The first reset signal is output in the initialization phase, and the second enable signal is output in the light-emitting phase.
  • the first scanning end and the second scanning end are connected to the same scanning end.
  • the writing sub-circuit includes a third sub-circuit and a fourth sub-circuit.
  • the third sub-circuit is connected to the second scan terminal, the data terminal, and the second node; the third sub-circuit is configured to be under the control of the second scan signal of the second scan terminal , Turn on at least during the data writing phase, and transmit the data signal received by the data terminal to the second node; the fourth sub-circuit connects the first scanning terminal, the first node, and the third node Node, the fourth sub-circuit is configured to be turned on in the initialization phase and the data writing phase under the control of the first scan signal received by the first scan terminal, and in the initialization phase The initialization signal on the third node is transmitted to the first node, and the data signal of the second node is written to the first node in the data writing phase and the The driving transistor performs threshold voltage compensation.
  • the first reset sub-circuit includes a first transistor, the gate of the first transistor is connected to the first reset signal terminal, and the first electrode of the first transistor is connected to the initialization signal terminal , The second electrode of the first transistor is connected to the third node.
  • the second reset sub-circuit includes a second transistor, the gate of the second transistor is connected to the second reset signal terminal, and the first electrode of the second transistor is connected to the initialization signal terminal , The second electrode of the second transistor is connected to the anode of the light emitting device.
  • the first sub-circuit includes a third transistor, the gate of the third transistor is connected to the first enable signal terminal, and the first electrode of the third transistor is connected to the first voltage Terminal, the second pole of the third transistor is connected to the second node; the second sub-circuit includes a fourth transistor, the gate of the fourth transistor is connected to the second enable signal terminal, and the first The first pole of the four transistor is connected to the third node, and the second pole of the fourth transistor is connected to the anode of the light emitting device.
  • the third sub-circuit includes a fifth transistor, the gate of the fifth transistor is connected to the second scan terminal, the first electrode of the fifth transistor is connected to the data terminal, and the The second electrode of the fifth transistor is connected to the second node.
  • the fourth sub-circuit includes a sixth transistor, the gate of the sixth transistor is connected to the first scan terminal, and the first electrode of the sixth transistor is connected to the third node, so The second electrode of the sixth transistor is connected to the first node.
  • the fourth sub-circuit includes a seventh transistor and an eighth transistor; the gate of the seventh transistor is connected to the first scan terminal, and the first electrode of the seventh transistor is connected to the The third node is connected, the second electrode of the seventh transistor is connected to the fourth node; the gate of the eighth transistor is connected to the first scan terminal, and the first electrode of the eighth transistor is connected to the first scan terminal. Four-node connection, and the second electrode of the eighth transistor is connected to the first node.
  • the first reset sub-circuit includes a ninth transistor and the seventh transistor; the gate of the ninth transistor is connected to the first reset signal terminal, and the first reset signal terminal of the ninth transistor The electrode is connected to the initialization signal terminal, and the second electrode of the ninth transistor is connected to the fourth node.
  • an embodiment of the present disclosure provides a display panel including the above-mentioned pixel circuit.
  • the display panel has a plurality of sub-pixel regions arranged in an array, and each sub-pixel region is provided with one pixel circuit.
  • the display panel further includes a plurality of scan lines, and the first scan terminal and the second scan terminal connected to all the pixel circuits in the same row are both connected to one scan line; or, the display panel further includes a plurality of first scan lines and A plurality of second scan lines, and the first scan terminal and the second scan terminal connected to all the pixel circuits in the same row are respectively connected to the first scan line and the second scan line.
  • the first scan terminal and the second scan terminal connected to all pixel circuits located in the same row are connected to one scan line, and the first reset signal terminal connected to all pixel circuits located in the nth row is connected to the n-th The scan line corresponding to one row of pixel circuits.
  • an embodiment of the present disclosure provides a driving method of the above-mentioned pixel circuit, including: an initialization phase of an image frame: inputting a first reset signal to a first reset signal terminal, so that the first reset sub-circuit The initialization signal from the initialization signal terminal is transmitted to the third node; the first scanning signal is input to the first scanning terminal, so that the writing sub-circuit transmits the initialization signal on the third node to the first node , To reset the first node; in the data writing phase of an image frame: input the first scan signal to the first scan terminal, input the second scan signal to the second scan terminal, and input to the data terminal Data signal, so that the writing sub-circuit writes the data signal received by the data terminal to the first node, and performs threshold voltage compensation on the driving transistor; in the light-emitting stage of an image frame: to the first node The enable signal terminal inputs the first enable signal, and inputs the second enable signal to the second enable signal terminal, so that the light-emitting control sub-cir
  • the driving method further includes: inputting the data signal to the data terminal during the initialization phase of an image frame.
  • FIG. 1A is a structural diagram of a driving circuit provided by related technologies
  • FIG. 1B is a structural diagram of another driving circuit provided by related technologies
  • FIG. 1C is a schematic diagram of the gate voltage change of the driving transistor in the pixel circuit provided by the related art
  • FIG. 2 is a top structural view of a display panel provided by an embodiment of the disclosure.
  • 3A is a structural diagram of a pixel circuit provided by an embodiment of the disclosure.
  • 3B is a simulation result diagram of a gate voltage of a driving transistor in a pixel circuit provided by an embodiment of the disclosure and a pixel circuit provided by related technologies;
  • FIG. 4 is a flowchart of a driving method of a pixel circuit provided by an embodiment of the disclosure.
  • FIG. 5 is a structural diagram of another pixel circuit provided by an embodiment of the disclosure.
  • 6A is a circuit connection diagram of a display panel provided by an embodiment of the disclosure.
  • 6B is a circuit connection diagram of another display panel provided by an embodiment of the disclosure.
  • 6C is a circuit connection diagram of yet another display panel provided by an embodiment of the present disclosure.
  • FIG. 7 is a specific structure diagram of a pixel circuit provided by an embodiment of the disclosure.
  • FIG. 8 is a timing control diagram of the pixel circuit shown in FIG. 7;
  • FIG. 9A is a schematic diagram of the pixel circuit shown in FIG. 7 in the initialization stage
  • 9B is a schematic diagram of the pixel circuit shown in FIG. 7 in the data writing stage
  • 9C is a schematic diagram of the pixel circuit shown in FIG. 7 in the light-emitting stage
  • FIG. 10 is a specific structure diagram of another pixel circuit provided by an embodiment of the disclosure.
  • FIG. 11 is a timing control diagram of the pixel circuit shown in FIG. 10;
  • FIG. 12A is a schematic diagram of the pixel circuit shown in FIG. 10 in the initialization stage
  • FIG. 12B is a schematic diagram of the pixel circuit shown in FIG. 10 in the data writing stage
  • FIG. 13 is a diagram of simulation results of various signals in a pixel circuit provided by an embodiment of the disclosure.
  • FIG. 14 is a circuit connection diagram of yet another display panel provided by an embodiment of the disclosure.
  • FIG. 15 is a timing control diagram of the pixel circuit in the display panel shown in FIG. 14;
  • FIG. 16 is a structural diagram of yet another pixel circuit provided by an embodiment of the disclosure.
  • FIG. 17 is a specific structure diagram of the pixel circuit shown in FIG. 16;
  • FIG. 18 is a timing control diagram of the pixel circuit shown in FIG. 17;
  • FIG. 19 is a diagram of simulation results of various signals in another pixel circuit provided by an embodiment of the disclosure.
  • FIG. 20 is a structural diagram of yet another pixel circuit provided by an embodiment of the disclosure.
  • FIG. 21 is a specific structure diagram of the pixel circuit shown in FIG. 20;
  • FIG. 22 is a timing control diagram of the pixel circuit shown in FIG. 21;
  • FIG. 23A is a schematic diagram of the pixel circuit shown in FIG. 21 in the initialization stage
  • FIG. 23B is a schematic diagram of the pixel circuit shown in FIG. 21 in the data writing stage
  • FIG. 23C is a schematic diagram of the pixel circuit shown in FIG. 21 in the light-emitting stage
  • FIG. 24 is a diagram of simulation results of various signals in another pixel circuit provided by an embodiment of the disclosure.
  • FIG. 25 is a specific structure diagram of another pixel circuit provided by an embodiment of the disclosure.
  • FIG. 26 is a timing control diagram of the pixel circuit shown in FIG. 25;
  • FIG. 27A is a schematic diagram of the pixel circuit shown in FIG. 25 in the initialization stage
  • FIG. 27B is a schematic diagram of the pixel circuit shown in FIG. 25 in the data writing stage
  • FIG. 27C is a schematic diagram of the pixel circuit shown in FIG. 25 in the light-emitting stage
  • FIG. 28 is a diagram of simulation results of various signals in another pixel circuit provided by an embodiment of the disclosure.
  • FIG. 29 is a simulation result diagram of a gate voltage of a driving transistor in another pixel circuit provided by an embodiment of the disclosure and a pixel circuit provided by related technologies;
  • FIG. 30A is a structural diagram of yet another pixel circuit provided by an embodiment of the disclosure.
  • FIG. 30B is a specific structure diagram of the pixel circuit shown in FIG. 30A.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features.
  • plural means two or more.
  • connection may be used.
  • connection may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the light-emitting diode (for example, organic light-emitting diode) is a current-driven device. As shown in FIG. 1A, it is a driving circuit for driving the light-emitting diode in the related art.
  • a storage capacitor Cst is composed.
  • the driving transistor Td is turned on, the first voltage terminal VDD, the light emitting diode L, and the second voltage terminal VSS are turned on, and the driving current generated by the driving transistor Td drives the light emitting diode L to emit light.
  • the data signal on the data signal terminal DE charges the storage capacitor Cst connected to the switching transistor Ts, and the electric energy stored in the storage capacitor Cst keeps the driving transistor Td turned on to maintain a frame of image display required time.
  • the saturation current formula of the driving transistor Td is:
  • K is a coefficient related to the characteristics of the driving transistor Td
  • Vgs is the gate-source voltage of the driving transistor Td
  • Vth is the threshold voltage of the driving transistor Td.
  • the display device usually includes a plurality of light-emitting diodes L, and there are correspondingly multiple driving circuits for driving the light-emitting diodes L to emit light. Due to process differences, temperature, device aging and other factors, the threshold voltage Vth of the driving transistor Td will drift, which causes the driving current provided by the driving transistor Td to the light emitting diode L to deviate from the target current value. Since the threshold voltage Vth of each driving transistor Td in different driving circuits may be different, the light-emitting brightness of each light-emitting diode L may be inconsistent, which may result in uneven display of the display device.
  • a threshold voltage compensation sub-circuit 101 is added to the driving circuit shown in FIG. 1A to before the driving circuit drives the light emitting diode L to emit light.
  • the threshold voltage Vth of the driving transistor Td is compensated to eliminate the influence of the drift of the threshold voltage Vth on the display device.
  • the driving circuit also includes a reset sub-circuit 102 to reset the gate of the driving transistor Td before the next frame is displayed. .
  • the threshold voltage compensation sub-circuit 101 and the reset sub-circuit 102 are both electrically connected to the first node N1 (the gate of the driving transistor Td), causing the voltage of the first node N1 to be compensated by the threshold voltage.
  • a change in Vgs may cause a change in the driving current I, thereby causing a change in the luminous brightness of the light-emitting diode L, and causing a flicker phenomenon in the display screen of the display device.
  • both the display device M1 and the display device M2 have the Flicker phenomenon, and as the driving frequency decreases, the Flicker phenomenon becomes more serious.
  • the driving frequency is 40 Hz
  • the Flicker phenomenon is level one (L1)
  • the driving frequency is 20 Hz
  • the Flicker phenomenon is level three (L3).
  • the driving frequency is 15 Hz
  • the display device displays a scrolling abnormal display
  • the driving frequency is 7.5 Hz
  • the display device displays a serious scrolling abnormal display.
  • the reason for the above-mentioned Flicker phenomenon is: as shown in FIG. 1C, at the beginning of the light-emitting phase, the voltage of the first node N1 is V1, and during the duration of the light-emitting phase, the transistors in the threshold voltage compensation sub-circuit 101 and the reset sub-circuit 102 are in In the off state, due to the leakage current of the transistor, the voltage of the first node N1 continuously changes during the light-emitting phase. At the end of the light-emitting phase, the voltage of the first node N1 is V2, and during the duration of the light-emitting phase, the amount of change in the voltage of the first node N1 is ⁇ V. The lower the frequency, the longer the time of one frame, the larger the ⁇ V, the more drastic the brightness of the light-emitting diode LED changes, and the more serious the Flicker phenomenon.
  • the display panel includes a plurality of pixel circuits 100.
  • the display panel has a plurality of sub-pixel regions P arranged in an array, and each sub-pixel region P is provided with a pixel circuit 100.
  • the pixel circuit 100 provided by some embodiments of the present disclosure includes: a driving sub-circuit 10, a first reset sub-circuit 20, a writing sub-circuit 30, a light-emitting device 40, and a light-emitting control sub-circuit 50.
  • the driving sub-circuit 10 includes a driving transistor Td and a storage capacitor Cst.
  • the gate of the driving transistor Td is connected to the first node N1, the first electrode of the driving transistor Td is connected to the second node N2, and the second electrode of the driving transistor Td is connected to the third node N3.
  • the storage capacitor Cst includes a first storage electrode and a second storage electrode, the first storage electrode is connected to the first node N1, and the second storage electrode is connected to the first voltage terminal VDD.
  • the driving transistor Td is a transistor that supplies a driving current to the light emitting device 40, and the aspect ratio of the driving transistor Td is greater than that of the transistor functioning as a switch.
  • the first reset sub-circuit 20 is connected to at least the third node N3, the first reset signal terminal RE1 and the initialization signal terminal INI.
  • the first reset signal terminal RE1 is configured to receive the first reset signal and output the first reset signal to the first reset sub-circuit 20.
  • the initialization signal terminal INI is configured to receive the initialization signal and output the initialization signal to the first reset sub-circuit 20.
  • the first reset sub-circuit 20 is configured to transmit the initialization signal from the initialization signal terminal INI to the third node N3 in the initialization phase, at least under the control of the first reset signal received by the first reset signal terminal RE1.
  • the writing sub-circuit 30 is connected to the first scan terminal G1, the second scan terminal G2, the data terminal DE, the first node N1, the second node N2, and the third node N3.
  • the first scanning terminal G1 is configured to receive the first scanning signal and output the first scanning signal to the writing sub-circuit 30.
  • the second scanning terminal G2 is configured to receive the second scanning signal and output the second scanning signal to the writing sub-circuit 30.
  • the data terminal DE is configured to receive a data signal and output the data signal to the writing sub-circuit 30.
  • the writing sub-circuit 30 is configured to: in the initialization phase, under the control of the first scan signal received by the first scan terminal G1, transmit the initialization signal on the third node N3 to the first node N1, so as to communicate with the first node N1.
  • N1 is reset; in the data writing stage, under the control of the first scan signal received by the first scan terminal G1 and the second scan signal received by the second scan terminal G2, the data signal received by the data terminal DE is written to The first node N1 performs threshold voltage compensation on the driving transistor Td.
  • the light emitting device 40 includes an anode and a cathode, and the cathode is connected to the second voltage terminal VSS.
  • the light emitting device is an organic light emitting diode (OLED), a micro light emitting diode (Micro LED), a mini light emitting diode (Mini Light Emitting Diode, Mini LED), and the like.
  • the light emission control sub-circuit 50 is connected to the second node N2, the third node N3, the first voltage terminal VDD, the first enable signal terminal EM1, the second enable signal terminal EM2 and the anode of the light emitting device 40.
  • the first voltage terminal VDD is configured to receive a voltage signal and output the voltage signal to the light emission control sub-circuit 50.
  • the first enable signal terminal EM1 is configured to receive the first enable signal and output the first enable signal to the light emission control sub-circuit 50.
  • the second enable signal terminal EM2 is configured to receive the second enable signal and output the second enable signal to the light emission control sub-circuit 50.
  • the voltage signal of the first voltage terminal VDD is a high voltage signal
  • the voltage signal of the second voltage terminal VSS is a low voltage signal.
  • the light emission control sub-circuit 50 is configured to reduce the first voltage under the control of the first enable signal received by the first enable signal terminal EM1 and the second enable signal received by the second enable signal terminal EM2 during the light emitting stage.
  • the voltage signal of the terminal VDD is transmitted to the second node N2, and the current output by the driving transistor Td is transmitted to the light emitting device 40, so that the light emitting device 40 emits light.
  • the writing sub-circuit 30 is connected to the first node N1 (the gate of the driving transistor Td), and the first reset sub-circuit 20 is connected to the third node N3, which is connected to the pixel in the related art. Compared with the circuit, only the writing sub-circuit 30 is directly connected to the gate of the driving transistor Td. In this way, the influence on the gate voltage of the driving transistor Td is small.
  • the amount of change ⁇ V of the gate voltage of the driving transistor Td is reduced, so that the influence on the light-emitting performance of the light-emitting device 40 is reduced, and the Improve the light-emitting performance of the display panel and reduce the occurrence of the Flicker phenomenon.
  • the simulation result of the voltage of the gate of the driving transistor Td within one frame time is shown.
  • the voltage of the gate of the driving transistor Td of the driving circuit provided by the related art is changed from 3.4V to 2.2V, and the voltage variation ⁇ V reaches 1.2V.
  • the voltage of the gate of the driving transistor Td of the pixel circuit 100 is changed from 3.6V to 2.9V, and the voltage change ⁇ V is only 0.7V. It can be seen that the pixel circuit 100 provided by the embodiment of the present disclosure can effectively maintain the gate voltage of the driving transistor Td, which is beneficial to improve the Flicker phenomenon.
  • Some embodiments of the present disclosure provide a driving method of the above-mentioned pixel circuit 100. As shown in Figure 4, the method includes S1-S3.
  • Initialization phase of an image frame input a first reset signal to the first reset signal terminal RE1, so that the first reset sub-circuit 20 transmits the initialization signal from the initialization signal terminal INI to the third node N3.
  • the first scan signal is input to the first scan terminal G1, so that the writing sub-circuit 30 transmits the initialization signal on the third node N3 to the first node N1 to reset the first node N1.
  • the data writing stage of an image frame the first scanning signal is input to the first scanning terminal G1, the second scanning signal is input to the second scanning terminal G2, and the data signal is input to the data terminal DE, so that the writing sub
  • the circuit 20 writes the data signal received by the data terminal DE to the first node N1, and performs threshold voltage compensation on the driving transistor Td.
  • the light-emitting stage of an image frame the first enable signal is input to the first enable signal terminal EM1, and the second enable signal is input to the second enable signal terminal EM2, so that the light-emitting control sub-circuit 50 turns the first enable signal
  • the voltage signal of a voltage terminal VDD is transmitted to the second node N2, and the current output by the driving transistor Td is transmitted to the light emitting device 40, so that the light emitting device 40 emits light.
  • the driving method of the pixel circuit 100 further includes: inputting a data signal to the data terminal DE for precharging during the initialization phase of an image frame, which is advantageous for data signal writing.
  • the light emission control sub-circuit 50 includes a first sub-circuit 51 and a second sub-circuit 52.
  • the first sub-circuit 51 is connected to the second node N2, the first voltage terminal VDD and the first enable signal terminal EM1.
  • the first sub-circuit 51 is configured to transmit the voltage signal of the first voltage terminal VDD to the second node N2 under the control of the first enable signal of the first enable signal terminal EM1 during the light-emitting phase.
  • the second sub-circuit 52 is connected to the third node N3, the second enable signal terminal EM2 and the anode of the light emitting device 40.
  • the second sub-circuit 52 is configured to transmit the current output by the driving transistor Td to the light-emitting device 40 under the control of the second enable signal of the second enable signal terminal EM2 in the light-emitting phase.
  • the writing sub-circuit 30 includes a third sub-circuit 31 and a fourth sub-circuit 32.
  • the third sub-circuit 31 is connected to the second scan terminal G2, the data terminal DE and the second node N2.
  • the third sub-circuit 31 is configured to be turned on at least during the data writing phase under the control of the second scan signal from the second scan terminal G2, and transmit the data signal received by the data terminal DE to the second node N2.
  • the fourth sub-circuit 32 is connected to the first scanning terminal G1, the first node N1 and the third node N3.
  • the fourth sub-circuit 32 is configured to be turned on during the initialization phase and the data writing phase under the control of the first scan signal received by the first scan terminal G1, and to transmit the initialization signal on the third node N3 to the first scan terminal G1 during the initialization phase.
  • a node N1 writes the data signal of the second node N2 to the first node N1 and performs threshold voltage compensation on the driving transistor Td during the data writing phase.
  • the display panel further includes a plurality of first scan lines GL1, a plurality of second scan lines GL2, a plurality of first enable signal lines EML1, and a plurality of second enable signal lines EML2 and a plurality of first reset signal lines RL1.
  • the first scan terminal G1 and the second scan terminal G2 connected to all the pixel circuits 100 located in the same row are respectively connected to the first scan line GL1 and the second scan line GL2.
  • the first reset signal terminals RE1 connected to all the pixel circuits 100 located in the same row are connected to the same first reset signal line RL1.
  • the first enable signal terminals EM1 to which all the pixel circuits 100 located in the same row are connected are connected to the same first enable signal line EML1.
  • the second enable signal terminals EM2 connected to all the pixel circuits 100 located in the same row are connected to the same second enable signal line EML2.
  • the first scan line GL1 is configured to provide a first scan signal to the first scan terminal G1 connected to the pixel circuit 100 of a row.
  • the second scan line GL2 is configured to provide a second scan signal to the second scan terminal G2 connected to the pixel circuit 100 of a row.
  • the first reset signal line RL1 is configured to provide a first reset signal to the first reset signal terminal RE1 connected to the pixel circuit 100 of one row.
  • the first enable signal line EML1 is configured to provide a first enable signal to a first enable signal terminal EM1 connected to a row of pixel circuits 100.
  • the second enable signal line EML2 is configured to provide a second enable signal to the second enable signal terminal EM2 connected to the pixel circuit 100 of one row.
  • the display panel further includes a plurality of data signal lines DL and a plurality of initialization signal lines IL.
  • the data terminals DE connected to all the pixel circuits 100 located in the same column are connected to the same data signal line DL.
  • the initialization signal terminals INI connected to all the pixel circuits 100 located in the same column are connected to the same initialization signal line IL.
  • the data signal line DL is configured to provide a data signal to a data terminal DE connected to a column of pixel circuits 100.
  • the initialization signal line IL is configured to provide an initialization signal to the initialization signal terminal INI connected to a column of pixel circuits 100.
  • the first scanning terminal G1 and the second scanning terminal G2 are connected to the same scanning terminal.
  • the first scanning signal and the second scanning signal are the same scanning signal.
  • the display panel includes a plurality of scan lines GL, and the first scan terminal G1 and the second scan terminal G2 connected to all the pixel circuits 100 located in the same row are connected to one scan line GL. That is, the scan terminal G to which all the pixel circuits 100 located in the same row are connected is connected to one scan line GL.
  • the third sub-circuit 31 is configured to be turned on in both the initialization phase and the data writing phase under the control of the second scan signal from the second scan terminal G2.
  • the first enable signal terminal EM1 and the second enable signal terminal EM2 are connected to the same enable signal terminal. In the case where the first enable signal terminal EM1 and the second enable signal terminal EM2 are connected to the same enable signal terminal, the first enable signal and the second enable signal are the same enable signal.
  • the display panel includes a plurality of enable signal lines EML, and the first enable signal terminal EM1 and the second enable signal terminal EM2 connected to all the pixel circuits 100 in the same row are connected to one enable signal.
  • Line EML That is, the enable signal terminals EM to which all the pixel circuits 100 located in the same row are connected are connected to one enable signal line EML.
  • the first reset sub-circuit 20 includes a first transistor T1, the gate of the first transistor T1 is connected to the first reset signal terminal RE1, and the first electrode of the first transistor T1 is connected to the initialization signal terminal. INI, the second electrode of the first transistor T1 is connected to the third node N3.
  • the first reset sub-circuit 20 includes a plurality of first transistors T1 connected in parallel or in series.
  • the gates of the plurality of first transistors T1 are all connected to the first reset signal terminal RE1
  • the first electrodes of the plurality of first transistors T1 All are connected to the initialization signal terminal INI
  • the second electrodes of the plurality of first transistors T1 are all connected to the third node N3.
  • the first reset sub-circuit 20 includes a plurality of first transistors T1 connected in series
  • the plurality of first transistors T1 are connected in sequence (the second pole of the first first transistor T1 is connected to the second electrode of the second first transistor T1).
  • the first pole, and so on) the gates of the plurality of first transistors T1 are all connected to the first reset signal terminal RE1, and the first pole of the first transistor T1 of the plurality of first transistors T1 is connected to the initialization signal
  • the terminal INI, the second pole of the last first transistor T1 is connected to the third node N3.
  • the first sub-circuit 51 includes a third transistor T3, the gate of the third transistor T3 is connected to the first enable signal terminal EM1, and the first electrode of the third transistor T3 is connected to the first voltage.
  • the terminal VDD, the second electrode of the third transistor T3 is connected to the second node N2.
  • the first sub-circuit 51 includes a plurality of third transistors T3 connected in parallel or in series.
  • the gates of the plurality of third transistors T3 are all connected to the first enable signal terminal EM1
  • the first electrodes of the plurality of third transistors T3 All are connected to the first voltage terminal VDD
  • the second electrodes of the plurality of third transistors T3 are all connected to the second node N2.
  • the first sub-circuit 51 includes a plurality of third transistors T3 connected in series
  • the plurality of third transistors T3 are connected in sequence (the second pole of the first third transistor T3 is connected to the second pole of the second third transistor T3).
  • the gates of the plurality of third transistors T3 are all connected to the first enable signal terminal EM1
  • the first pole of the first third transistor T3 of the plurality of third transistors T3 is connected to the first The voltage terminal VDD
  • the second pole of the last third transistor T1 is connected to the second node N2.
  • the second sub-circuit 52 includes a fourth transistor T4, the gate of the fourth transistor T4 is connected to the second enable signal terminal EM2, and the first electrode of the fourth transistor T4 is connected to the third node. N3, the second electrode of the fourth transistor T4 is connected to the anode of the light emitting device 40.
  • the second sub-circuit 52 includes a plurality of fourth transistors T4 connected in parallel or in series.
  • the gates of the plurality of fourth transistors T4 are all connected to the second enable signal terminal EM2, and the first electrodes of the plurality of fourth transistors T4 All are connected to the third node N3, and the second electrodes of the plurality of fourth transistors T4 are all connected to the anode of the light emitting device 40.
  • the second sub-circuit 52 includes a plurality of fourth transistors T4 connected in series
  • the plurality of fourth transistors T4 are connected in sequence (the second pole of the first fourth transistor T4 is connected to the second pole of the second fourth transistor T4).
  • the gates of the plurality of fourth transistors T4 are all connected to the second enable signal terminal EM2
  • the first pole of the first fourth transistor T4 of the plurality of fourth transistors T4 is connected to the third At the node N3, the second electrode of the last fourth transistor T4 is connected to the anode of the light emitting device 40.
  • the third sub-circuit 31 includes a fifth transistor T5, the gate of the fifth transistor T5 is connected to the second scan terminal G2, the first electrode of the fifth transistor T5 is connected to the data terminal DE, and the first electrode of the fifth transistor T5 is connected to the data terminal DE.
  • the second electrode of the five transistor T5 is connected to the second node N2.
  • the third sub-circuit 31 includes a plurality of fifth transistors T5 connected in parallel or in series.
  • the gates of the plurality of fifth transistors T5 are all connected to the second scan terminal G2, and the first electrodes of the plurality of fifth transistors T5 are all connected to The data terminal DE and the second electrodes of the plurality of fifth transistors T5 are all connected to the second node N2.
  • the plurality of fifth transistors T5 are connected in sequence (the second pole of the first fifth transistor T5 is connected to the second pole of the second fifth transistor T5).
  • the gates of the plurality of fifth transistors T5 are all connected to the second scan terminal G2, and the first pole of the first fifth transistor T5 of the plurality of fifth transistors T5 is connected to the data terminal DE, The second pole of the last fifth transistor T5 is connected to the second node N2.
  • the fourth sub-circuit 32 includes a sixth transistor T6, the gate of the sixth transistor T6 is connected to the first scan terminal G1, and the first electrode of the sixth transistor T6 is connected to the third node N3, The second electrode of the sixth transistor T6 is connected to the first node N1.
  • the fourth sub-circuit 32 includes a plurality of sixth transistors T6 connected in parallel or in series.
  • the gates of the plurality of sixth transistors T6 are all connected to the first scan terminal G1, and the first electrodes of the plurality of sixth transistors T6 are all connected to The third node N3 and the second electrodes of the plurality of sixth transistors T6 are all connected to the first node N1.
  • the plurality of sixth transistors T6 are connected in sequence (the second pole of the first sixth transistor T6 is connected to the second pole of the second sixth transistor T6).
  • the gates of the plurality of sixth transistors T6 are all connected to the first scan terminal G1, and the first pole of the first sixth transistor T6 of the plurality of sixth transistors T6 is connected to the third node N3 , The second pole of the last sixth transistor T6 is connected to the first node N1.
  • the embodiments of the present disclosure do not limit the types of transistors in each sub-circuit, that is, the driving transistor Td, the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor are not limited.
  • the transistors T6 may all be P-type transistors or all N-type transistors.
  • the driving transistor Td, the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all P-type transistors.
  • the source and drain of the transistor on the first pole and the other of the source and drain of the transistor on the second pole. Since the source and drain of the transistor can be symmetrical in structure, the source and drain of the transistor can be structurally indistinguishable. That is to say, the first electrode and the second electrode of the transistor in the embodiment of the present disclosure The two poles can be indistinguishable in structure.
  • the second electrode is usually called the drain and the first electrode is called the source
  • the first electrode is usually called the drain and the second electrode is called the source. pole.
  • the driving process of the pixel circuit 100 in an image frame can be divided into an initialization phase P1, a data writing phase P2, and a light emitting phase P3.
  • the first reset sub-circuit 20 includes a first transistor T1
  • the first sub-circuit 51 includes a third transistor T3
  • the second sub-circuit 52 includes a fourth transistor T4
  • the third sub-circuit 31 includes a fifth transistor T5.
  • the fourth sub-circuit 32 includes a sixth transistor T6.
  • the first enable signal terminal EM1 and the second enable signal terminal EM2 are connected to the same enable signal terminal EM.
  • the potentials of the first reset signal output by the first reset terminal RE1 and the first scan signal output by the first scan terminal G1 are low, and the enable signal terminal EM outputs the enable The signal and the potential of the second scan signal output by the second scan terminal G2 are high.
  • the first reset sub-circuit 20 in FIG. 7 transmits the initialization signal from the initialization signal terminal INI to the third node N3 under the control of the first reset signal.
  • the fourth sub-circuit 32 transmits the initialization signal on the third node N3 to the first node N1 under the control of the first scan signal, so as to initialize the first node N1 through the initialization signal, so as to avoid the last frame remaining in the first node N1.
  • the electrical signal of node N1 affects the picture of this frame.
  • the first reset signal controls the first transistor T1 to turn on, and the initialization signal input from the initialization signal terminal INI is transmitted through the first transistor T1 To the third node N3.
  • the first scan signal controls the sixth transistor T6 to turn on, and the initialization signal is transmitted to the first node N1 through the sixth transistor T6.
  • the first sub-circuit 51, the second sub-circuit 52, and the third sub-circuit 31 are all in a closed state during the initialization phase P1.
  • the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all turned off.
  • the transistor in the off state is indicated by a "x".
  • the potential of the first node N1 is V init .
  • Data writing stage P2 the potentials of the first scan signal output by the first scan terminal G1 and the second scan signal output by the second scan terminal G2 are low, the first reset signal output by the first reset signal terminal RE1 and the The potential of the enable signal output by the enable signal terminal EM is high.
  • the third sub-circuit 31 in FIG. 7 transmits the data signal from the data terminal DE to the second node N2 under the control of the second scan signal.
  • the fourth sub-circuit 32 Under the control of the first scan signal, the fourth sub-circuit 32 short-circuits the second electrode and the gate of the driving transistor Td to form a diode structure, writes the data signal on the second node N2 to the first node N1, and Threshold voltage compensation is performed on the driving transistor Td.
  • FIG. 9B the equivalent circuit diagram of the pixel circuit 100 shown in FIG. 7 in the data writing phase P2
  • the potential of the first reset signal is high, and the first transistor T1 is turned off .
  • the potential of the second scan signal is low, and the fifth transistor T5 is controlled to turn on, and the data signal from the data terminal DE is transmitted to the second node N2 through the fifth transistor T5.
  • the sixth transistor T6 remains turned on, and the second electrode and the gate of the driving transistor Td are short-circuited to form a diode structure.
  • the data signal on the second node N2 is transmitted to the first node N1 through the driving transistor Td and the sixth transistor T6.
  • the driving transistor Td is turned off.
  • the potential of the first node N1 is V data +Vth, and the potential is stored in the storage capacitor Cst.
  • Light-emitting stage P3 the potential of the enable signal output by the enable signal terminal EM is low, the potential of the first scan signal output by the first scan terminal G1, the potential of the second scan signal output by the second scan terminal G2 and the first The potential of the first reset signal output by a reset signal terminal RE1 is high.
  • the first sub-circuit 51 in FIG. 7 transmits the voltage signal of the first voltage terminal VDD to the second node N2 under the control of the enable signal.
  • the driving transistor Td generates a driving current under the control of the voltage of the first node N1 and the voltage signal of the first voltage terminal VDD.
  • the second sub-circuit 52 transmits the driving current output by the driving transistor Td to the light emitting device 40 under the control of the enable signal.
  • the potential of the first reset signal is at a high level, and the first transistor T1 is turned off.
  • the potential of the first scan signal is at a high level, and the sixth transistor T6 is turned off.
  • the potential of the second scan signal is at a high level, and the fifth transistor T5 is turned off.
  • the potential of the enable signal is low, and the third transistor T3 and the fourth transistor T4 are turned on.
  • the voltage signal of the first voltage terminal VDD is transmitted to the second node N2 through the third transistor T3.
  • the driving transistor Td generates a driving current under the control of the voltage of the first node N1 and the voltage signal of the first voltage terminal VDD.
  • the driving current is transmitted to the light emitting device 40 through the fourth transistor T4, so that the light emitting device 40 emits light.
  • the potential of the first node N1 is V data + Vth
  • the potential of the second node N2 is Vdd
  • the driving transistor Td After the driving transistor Td is turned on, when the gate-source voltage Vgs of the driving transistor Td minus the threshold voltage Vth of the driving transistor Td is less than or equal to the drain-source voltage Vds of the driving transistor Td, that is, when Vgs-Vth ⁇ Vds, the driving The transistor Td can be in a saturated turn-on state. At this time, the driving current I flowing through the driving transistor Td is:
  • W/L is the width-to-length ratio of the driving transistor Td
  • Cox is the dielectric constant of the channel insulating layer
  • ⁇ is the channel carrier mobility
  • the above parameters are only related to the structure of the driving transistor Td, the data signal output from the data voltage terminal DE, and the voltage signal output from the first voltage terminal VDD, and have nothing to do with the threshold voltage Vth of the driving transistor Td, thereby eliminating the threshold voltage Vth of the driving transistor Td.
  • the influence on the light-emitting brightness of the light-emitting device 40 can thereby improve the brightness uniformity of the display panel.
  • the first scanning terminal G1 and the second scanning terminal G2 are connected to the same scanning terminal G. Based on this, the timing control diagram of the pixel circuit 100 shown in FIG. 10 is shown in FIG. 11.
  • the potential of the first reset signal output by the first reset signal terminal RE1 and the potential of the scan signal output by the scan terminal G are low, and the enable signal output by the enable signal terminal EM The potential is high.
  • the potential of the first reset signal is low, and the first transistor T1 is controlled to turn on, and the initialization signal
  • the initialization signal input from the terminal INI is transmitted to the third node N3 via the first transistor T1.
  • the potential of the scan signal is low, the sixth transistor T6 is turned on, and the initialization signal is transmitted to the first node N1 through the sixth transistor T6.
  • the potential of the enable signal is at a high level during the initialization phase P1, and the first sub-circuit 51 and the second sub-circuit 52 are in a closed state. As shown in FIGS. 11 and 12A, the third transistor T3 and the fourth transistor T4 are turned off.
  • the potential of the scan signal output by the scan terminal G is low, the potential of the first reset signal output by the first reset signal terminal RE1, and the enable signal output from the enable signal terminal EM
  • the potential of the energy signal is high.
  • the potential of the first reset signal is high and the first transistor T1 is turned off.
  • the potential of the scan signal is low, and the fifth transistor T5 and the sixth transistor T6 are controlled to turn on, and the data signal from the data terminal DE is transmitted to the second node N2 through the fifth transistor T5.
  • the sixth transistor T6 is turned on to short-circuit the second electrode and the gate of the driving transistor Td to form a diode structure.
  • the data signal on the second node N2 is transmitted to the first node N1 through the driving transistor Td and the sixth transistor T6.
  • the driving transistor Td is turned off.
  • the light-emitting phase P3, the turn-on state of each transistor and the signal transmission process are the same as the light-emitting phase P3 in the first possible embodiment, and will not be repeated here.
  • the fifth transistor T5 is also in the on state, and the data terminal DE will also input the data signal, but because The voltage difference between the data terminal DE and the first node N1 is smaller than the voltage difference between the data terminal DE and the initialization signal terminal INI, and the data signal of the data terminal DE is transmitted to the first node N1 through the fifth transistor T5, the driving transistor Td and For the sixth transistor T6, in the initialization phase P1, the data signal has a small influence on the voltage of the first node N1.
  • the pixel circuit 100 of the second possible embodiment is the simulation result of each signal during the driving process of an image frame. It can be seen from FIG. 13 that the first node N1 can perform normal initialization and data signal writing.
  • the first scan terminal G1 and the second scan terminal G2 connected to all the pixel circuits located in the same row are connected to one scan line GL, and all the pixel circuits 100 located in the nth row are connected to the first reset signal terminal RE1.
  • the scanning line GL(n-1) connected to the pixel circuit 100 in the n-1th row is connected.
  • the timing control diagram corresponding to the pixel circuit 100 is as shown in FIG. The difference is that in the third possible implementation manner, in the initialization phase P1, the first reset signal of the first reset signal terminal RE1(n) connected to the pixel circuit 100 of the nth row is changed from the first reset signal of the n-1th row Scan line GL(n-1) is provided.
  • n is a positive integer greater than or equal to 2.
  • the first reset signal terminal RE1(n) connected to all the pixel circuits 100 in the nth row is connected to the scanning line GL(n-1) corresponding to the pixel circuit 100 in the n-1th row, and the first reset signal line RL1 does not need to be separately provided , Can reduce the number of wiring of the display panel.
  • the initialization signal terminal INI is connected to the anode of the light emitting device 40.
  • the residual voltage of the anode of the light emitting device 40 can be used to reset the first node N1, so that the number of wires on the display panel can be reduced.
  • the structure of the pixel circuit 100 is shown in FIG. 17, and the corresponding timing control diagram is shown in FIG. 18.
  • the driving process of the pixel circuit 100 is similar to that in the first possible implementation manner. The difference is that in the fourth possible implementation manner, in the initialization phase P1, the first node N1 is reset by using the residual voltage of the anode of the light-emitting device 40.
  • the pixel circuit 100 of the fourth possible embodiment of the present disclosure is the simulation result of each signal during the driving process of an image frame. It can be seen from FIG. 19 that the first node N1 can perform normal initialization and data signal writing.
  • the second sub-circuit 52 is multiplexed with the first reset sub-circuit 20, and the first reset signal terminal RE1 and the second enable signal terminal EM2 are the same signal terminal EM_S.
  • the signal terminal EM_S is configured to output the first reset signal during the initialization phase P1, and output the second enable signal during the light-emitting phase P3.
  • the structure of the pixel circuit 100 is shown in FIG. 21, and the corresponding timing control diagram is shown in FIG. 22.
  • the driving process of the pixel circuit 100 is as follows.
  • the signal terminal EM_S outputs a control signal
  • the control signal includes a first reset signal and a second enable signal.
  • the first scan terminal G1 outputs a first scan signal
  • the second scan terminal G2 outputs a second scan signal.
  • the first enable signal terminal EM1 outputs the first enable signal.
  • the potential of the first reset signal is low.
  • the potential of the first scan signal is low.
  • the potentials of the first enable signal and the second scan signal are both high.
  • the potential of the first reset signal is low, and the fourth transistor T4 is controlled to turn on, and the light emitting device
  • the anode voltage of 40 is transferred to the third node N3 through the fourth transistor T4.
  • the potential of the first scan signal is a low-level turn-on signal, the sixth transistor T6 is turned on, and the voltage of the third node N3 is transmitted to the first node N1 through the sixth transistor T6, thereby resetting the first node N1.
  • the first sub-circuit 51 and the third sub-circuit 31 are in a closed state during the initialization phase P1. In this case, as shown in FIG. 23A, the third transistor T3 and the fifth transistor T5 are turned off.
  • Data writing phase P2 The potentials of the first scan signal and the second scan signal are low.
  • the potential of the control signal is high.
  • the potential of the first enable signal is high.
  • the potential of the control signal is high and the fourth transistor T4 is turned off.
  • the potential of the second scan signal is low, and the fifth transistor T5 is controlled to turn on, and the data signal from the data terminal DE is transmitted to the second node N2 through the fifth transistor T5.
  • the potential of the first scan signal is still low, the sixth transistor T6 remains on, and the second electrode and the gate of the driving transistor Td are short-circuited to form a diode structure ,
  • the data signal on the second node N2 is transmitted to the first node N1 through the driving transistor Td and the sixth transistor T6.
  • the driving transistor Td is turned off.
  • Light-emitting stage P3 the potential of the first enable signal is low.
  • the potential of the second enable signal is low.
  • the potentials of the first scan signal and the second scan signal are high.
  • the potential of the first scan signal is at a high level, and the sixth transistor T6 is turned off.
  • the potential of the second scan signal is at a high level, and the fifth transistor T5 is turned off.
  • the potential of the first enable signal and the potential of the second enable signal are both low, and the third transistor T3 and the fourth transistor T4 are turned on.
  • the voltage signal of the first voltage terminal VDD is transmitted to the second node N2 through the third transistor T3.
  • the driving transistor Td generates a driving current under the control of the voltage signal of the first node N1 and the first voltage terminal VDD.
  • the driving current is transmitted to the light emitting device 40 through the fourth transistor T4, so that the light emitting device 40 emits light.
  • the second sub-circuit 52 is multiplexed with the first reset sub-circuit 20, so that at least one transistor can be reduced, and the pixel circuit 100 can be further simplified.
  • the pixel circuit 100 is the simulation result of each signal during the driving process of an image frame. It can be seen from FIG. 24 that the first node N1 can perform normal initialization and data signal writing.
  • the fourth sub-circuit 32 includes a seventh transistor T7 and an eighth transistor T8.
  • the gate of the seventh transistor T7 is connected to the first scan terminal G1, the first electrode of the seventh transistor T7 is connected to the third node N3, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.
  • the gate of the eighth transistor T8 is connected to the first scan terminal G1, the first electrode of the eighth transistor T8 is connected to the fourth node N4, and the second electrode of the eighth transistor T8 is connected to the first node N1.
  • the first reset sub-circuit 20 includes a ninth transistor T9 and the aforementioned seventh transistor T7.
  • the gate of the ninth transistor T9 is connected to the first reset signal terminal RE1, the first electrode of the ninth transistor T9 is connected to the initialization signal terminal INI, and the second electrode of the ninth transistor T9 is connected to the fourth node N4.
  • the structures of the first sub-circuit 51, the second sub-circuit 52, and the third sub-circuit 31 can refer to the first sub-circuit 51, the second sub-circuit 52, and the third sub-circuit 31 in the first possible implementation manner, which will not be omitted here. Go into details.
  • the first scanning terminal G1 and the second scanning terminal G2 are connected to the same scanning terminal G.
  • the first enable signal terminal EM1 and the second enable signal terminal EM2 are connected to the same enable signal terminal EM.
  • the timing control diagram corresponding to the pixel circuit 100 is shown in FIG. 26.
  • the first reset signal terminal RE1 outputs the first reset signal
  • the scan signal output from the scan terminal G
  • the enable signal terminal EM outputs an enable signal
  • the initialization signal terminal INI outputs an initialization signal.
  • Initialization stage P1 the potential of the first reset signal and the potential of the scan signal are low, and the potential of the enable signal is high.
  • the potential of the first reset signal is low, and the ninth transistor T9 is controlled to turn on.
  • the initialization signal output from the initialization signal terminal INI is transmitted to the fourth node N4 via the ninth transistor T9.
  • the potential of the initialization signal is the first level, for example, -2.5V.
  • the potential of the scan signal is low, the seventh transistor T7 and the eighth transistor T8 are turned on, and the first level is transmitted to the first node N1 and the third node N3 through the seventh transistor T7 and the eighth transistor T8, respectively.
  • the potential of the enable signal is high, and the third transistor T3 and the fourth transistor T4 are turned off.
  • the data terminal DE may also input a data signal for precharging, which is beneficial to the writing of the data signal.
  • Data writing phase P2 the potential of the scan signal is low, and the potential of the first reset signal and the potential of the enable signal are high.
  • the potential of the first reset signal is high, and the ninth transistor T9 is turned off .
  • the potential of the scan signal is low, the fifth transistor T5 is turned on, and the data signal from the data terminal DE is transmitted to the second node N2 through the fifth transistor T5.
  • the seventh transistor T7 and the eighth transistor T8 are turned on to short-circuit the second electrode and the gate of the driving transistor Td to form a diode structure.
  • the data signal on the second node N2 passes through the driving transistor Td, the seventh transistor T7 and the eighth transistor T8 is transmitted to the first node N1.
  • the driving transistor Td is turned off.
  • Light-emitting stage P3 the potentials of the first reset signal and the enable signal are low, and the potential of the scan signal is high.
  • the potential of the first reset signal is low, and the ninth transistor T9 is controlled to turn on.
  • the potential of the initialization signal is at the second level, and the second level is transmitted to the fourth node N4 via the ninth transistor T9.
  • the second level is, for example, 4.5V.
  • the potential of the scan signal is at a high level, and the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.
  • the potential of the enable signal is low, and the third transistor T3 and the fourth transistor T4 are turned on.
  • the voltage signal of the first voltage terminal VDD is transmitted to the second node N2 through the third transistor T3.
  • the driving transistor Td generates a driving current under the control of the potential of the first node N1 and the voltage signal of the first voltage terminal VDD.
  • the driving current is transmitted to the light emitting device 40 through the fourth transistor T4, so that the light emitting device 40 emits light.
  • the second level of the initialization signal is transmitted to the fourth node N4 through the ninth transistor T9, and the second level is high, so that the first node N1 and the fourth node N1
  • the voltage difference between the nodes N4 is reduced, thereby reducing the leakage current from the first node N1 to the fourth node N4, thereby better maintaining the voltage of the first node N1 within a frame time, and further reducing the occurrence of the Flicker phenomenon probability.
  • the pixel circuit 100 is the simulation result of each signal during the driving process of an image frame. It can be seen from FIG. 28 that the first node N1 can perform normal initialization and data signal writing.
  • the voltage of the gate of the driving transistor Td of the pixel circuit 100 provided by the related art is changed from 5V to 3.4V, and the voltage variation ⁇ V reaches 1.6V; the driving transistor of the pixel circuit 100 provided by the embodiment of the present disclosure
  • the voltage of the gate of Td is changed from 5V to 4.9V, and the voltage change ⁇ V is only 0.1V.
  • the pixel circuit 100 provided by the embodiment of the present disclosure can effectively maintain the gate voltage of the driving transistor Td, is beneficial to improve the Flicker phenomenon, and can be used in display panels such as ultra-low frequency (for example, 1 Hz).
  • the pixel circuit 100 further includes a second reset sub-circuit 60 which is connected to emit light The anode of the device 40, the second reset signal terminal RE2 and the initialization signal terminal INI.
  • the second reset signal terminal RE2 is configured to receive the second reset signal and output the second reset signal to the second reset sub-circuit 60.
  • the initialization signal terminal INI is also configured to output the initialization signal to the second reset sub-circuit 60.
  • the second reset sub-circuit 60 is configured to transmit the initialization signal from the initialization signal terminal INI to the light emitting device under the control of the second reset signal received by the second reset signal terminal RE2 during the initialization phase P1 or the data writing phase P2
  • the anode of 40 resets the anode of the light-emitting device 40.
  • the second reset sub-circuit 60 can reset the anode of the light-emitting device 40 to avoid the influence of the residual voltage of the anode of the light-emitting device 40 on the next frame when one frame of picture ends.
  • the second reset signal terminal RE2 and the first reset signal terminal RE1 are connected to the same reset signal terminal. In this way, the structure of the pixel circuit 100 can be simplified.
  • the second reset sub-circuit 60 is configured to transmit the initialization signal from the initialization signal terminal INI to the anode of the light-emitting device 40 during the initialization phase P1 to reset the anode of the light-emitting device 40.
  • the second reset sub-circuit 60 includes a second transistor T2, the gate of the second transistor T2 is connected to the second reset signal terminal RE2, and the first electrode of the second transistor T2 is connected to the initialization signal terminal. INI, the second electrode of the second transistor T2 is connected to the anode of the light emitting device 40.
  • the second reset sub-circuit 60 includes a plurality of second transistors T2 connected in parallel or in series.
  • the gates of the plurality of second transistors T2 are all connected to the second reset signal terminal RE2
  • the first electrodes of the plurality of second transistors T2 All are connected to the initialization signal terminal INI
  • the second electrodes of the plurality of second transistors T2 are all connected to the anode of the light-emitting device 40.
  • the second reset sub-circuit 60 includes a plurality of second transistors T2 connected in series
  • the plurality of second transistors T2 are connected in sequence (the second pole of the first second transistor T2 is connected to the second transistor T2 The first pole, and so on), the gates of the plurality of second transistors T2 are all connected to the second reset signal terminal RE2, and the first pole of the first second transistor T2 of the plurality of second transistors T2 is connected to the initialization signal The terminal INI, the second pole of the last second transistor T2 is connected to the anode of the light emitting device 40.

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Abstract

一种像素电路（100），包括：驱动子电路（10）、第一复位子电路（20）、写入子电路（30）、发光器件（40）和发光控制子电路（50）。驱动子电路（10）包括驱动晶体管（Td）和存储电容（Cst）；驱动晶体管（Td）的栅极与第一节点（N1）连接，第一极与第二节点（N2）连接，第二极与第三节点（N3）连接；存储电容（Cst）包括第一存储电极和第二存储电极，第一存储电极与第一节点（N1）连接，第二存储电极与第一电压端（VDD）连接。第一复位子电路（20）至少连接第三节点（N3）、第一复位信号端（RE1）和初始化信号端（INI）。写入子电路（30）连接第一扫描端（G1）、第二扫描端（G2）、数据端（DE）、第一节点（N1）、第二节点（N2）和第三节点（N3）。发光器件（40），包括阳极和阴极，阴极连接第二电压端（VSS）。发光控制子电路（50）连接第二节点（N2）、第三节点（N3）、第一电压端（VDD）、第一使能信号端（EM1）、第二使能信号端（EM2）和发光器件（40）的阳极。像素电路（100）能够降低显示装置的闪烁现象。

Description

像素电路及其驱动方法、显示面板
本申请要求于2020年05月29日提交的、申请号为202010479787.X的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、显示面板。
背景技术
随着显示技术的发展，自发光显示装置，例如，有机发光二极管(organic light emitting diode，OLED)、微型发光二极管(Micro Light Emitting Diode，Micro LED)，迷你发光二极管(Mini Light Emitting Diode，Mini LED)等显示装置因具有自发光、对比度高、能耗低、视角广、响应速度快等特点，具有广阔的发展前景。
发明内容
一方面，本公开实施例提供一种像素电路，该像素电路包括：驱动子电路、第一复位子电路、写入子电路、发光器件和发光控制子电路。所述驱动子电路包括：驱动晶体管和存储电容；所述驱动晶体管的栅极与第一节点连接，驱动晶体管的第一极与第二节点连接，驱动晶体管的第二极与第三节点连接；存储电容，包括第一存储电极和第二存储电极，所述第一存储电极与所述第一节点连接，所述第二存储电极与第一电压端连接。所述第一复位子电路，至少连接所述第三节点、第一复位信号端和初始化信号端；所述第一复位子电路被配置为在初始化阶段，至少在所述第一复位信号端接收的第一复位信号的控制下，将来自所述初始化信号端的初始化信号传输至所述第三节点。所述写入子电路，连接第一扫描端、第二扫描端、数据端、所述第一节点、所述第二节点和所述第三节点；所述写入子电路被配置为在所述初始化阶段，在所述第一扫描端接收的第一扫描信号的控制下，将所述第三节点上的所述初始化信号传输至所述第一节点，以对所述第一节点进行复位；在数据写入阶段，在所述第一扫描端接收的所述第一扫描信号和所述第二扫描端的接收的第二扫描信号的控制下，将所述数据端接收的数据信号写入至所述第一节点并对所述驱动晶体管进行阈值电压补偿。所述发光器件，包括阳极和阴极，所述阴极连接第二电压端。所述发光控制子电路，连接所述第二节点、所述第三节点、所述第一电压端、第一使能信号端、第二使能 信号端和所述发光器件的阳极；所述发光控制子电路被配置为在发光阶段，在所述第一使能信号端接收的第一使能信号和所述第二使能信号端接收的第二使能信号的控制下，将所述第一电压端的电压信号传输至所述第二节点，并将所述驱动晶体管输出的电流传输至所述发光器件，以使所述发光器件发光。
在一些实施例中，所述像素电路还包括：第二复位子电路。所述第二复位子电路，连接所述发光器件的阳极、第二复位信号端和所述初始化信号端；所述第二复位子电路被配置为在所述初始化阶段或所述数据写入阶段，在所述第二复位信号端接收的第二复位信号的控制下，将来自所述初始化信号端的所述初始化信号传输至所述发光器件的阳极，对所述阳极进行复位。
在一些实施例中，所述第一复位信号端和所述第二复位信号端连接同一复位信号端。
在一些实施例中，所述发光控制子电路包括第一子电路和第二子电路。所述第一子电路连接所述第二节点、所述第一电压端和所述第一使能信号端；所述第一子电路被配置为在发光阶段，在所述第一使能信号端的所述第一使能信号的控制下，将所述第一电压端的电压信号传输至所述第二节点；所述第二子电路连接所述第三节点、所述第二使能信号端和所述发光器件的阳极；所述第二子电路被配置为在发光阶段，在所述第二使能信号端的所述第二使能信号的控制下，将所述驱动晶体管输出的电流传输至所述发光器件。
在一些实施例中，所述第一使能信号端、所述第二使能信号端连接同一使能信号端。
在一些实施例中，所述初始化信号端与所述发光器件的阳极连接。
在一些实施例中，所述第二子电路与所述第一复位子电路复用，所述第一复位信号端与所述第二使能信号端为同一信号端；所述信号端被配置在所述初始化阶段输出所述第一复位信号，在所述发光阶段输出所述第二使能信号。
在一些实施例中，所述第一扫描端和所述第二扫描端连接同一扫描端。
在一些实施例中，所述写入子电路包括第三子电路和第四子电路。所述第三子电路连接所述第二扫描端、所述数据端和所述第二节点；所述第三子电路被配置为在所述第二扫描端的所述第二扫描信号的控制下， 至少在数据写入阶段开启，将所述数据端接收的数据信号传输至所述第二节点；所述第四子电路连接所述第一扫描端、所述第一节点和所述第三节点，所述第四子电路被配置为在所述第一扫描端接收的所述第一扫描信号的控制下，在所述初始化阶段和所述数据写入阶段开启，并在所述初始化阶段将所述第三节点上的所述初始化信号传输至所述第一节点，在所述数据写入阶段将所述第二节点的所述数据信号写入至所述第一节点并对所述驱动晶体管进行阈值电压补偿。
在一些实施例中，所述第一复位子电路包括第一晶体管，所述第一晶体管的栅极连接所述第一复位信号端，所述第一晶体管的第一极连接所述初始化信号端，所述第一晶体管的第二极连接所述第三节点。
在一些实施例中，所述第二复位子电路包括第二晶体管，所述第二晶体管的栅极连接所述第二复位信号端，所述第二晶体管的第一极连接所述初始化信号端，所述第二晶体管的第二极连接所述发光器件的阳极。
在一些实施例中，所述第一子电路包括第三晶体管，所述第三晶体管的栅极连接所述第一使能信号端，所述第三晶体管的第一极连接所述第一电压端，所述第三晶体管的第二极连接所述第二节点；所述第二子电路包括第四晶体管，所述第四晶体管的栅极连接所述第二使能信号端，所述第四晶体管的第一极连接所述第三节点，所述第四晶体管的第二极连接所述发光器件的阳极。
在一些实施例中，所述第三子电路包括第五晶体管，所述第五晶体管的栅极连接所述第二扫描端，所述第五晶体管的第一极连接所述数据端，所述第五晶体管的第二极连接所述第二节点。
在一些实施例中，所述第四子电路包括第六晶体管，所述第六晶体管的栅极连接所述第一扫描端，所述第六晶体管的第一极连接所述第三节点，所述第六晶体管的第二极连接所述第一节点。
在一些实施例中，所述第四子电路包括第七晶体管和第八晶体管；所述第七晶体管的栅极与所述第一扫描端连接，所述第七晶体管的第一极与所述第三节点连接，所述第七晶体管的第二极与第四节点连接；所述第八晶体管的栅极与所述第一扫描端连接，所述第八晶体管的第一极与所述第四节点连接，所述第八晶体管的第二极与所述第一节点连接。
在一些实施例中，所述第一复位子电路包括第九晶体管和所述第七晶体管；所述第九晶体管的栅极与所述第一复位信号端连接，所述第九晶体管的第一极与所述初始化信号端连接，所述第九晶体管的第二极与 所述第四节点连接。
另一方面，本公开实施例提供一种显示面板，包括上述像素电路。
在一些实施例中，所述显示面板具有多个呈阵列排布的亚像素区，每个亚像素区设置有一个所述像素电路。所述显示面板还包括多条扫描线，位于同一行的所有像素电路连接的第一扫描端和第二扫描端均连接一条扫描线；或者，所述显示面板还包括多条第一扫描线和多条第二扫描线，位于同一行的所有像素电路连接的第一扫描端和第二扫描端分别连接第一扫描线和第二扫描线。
在一些实施例中，位于同一行的所有像素电路连接的第一扫描端和第二扫描端均连接一条扫描线，位于第n行的所有像素电路连接的第一复位信号端连接与第n-1行像素电路对应的所述扫描线。
再一方面，本公开实施例提供一种上述像素电路的驱动方法，包括：在一图像帧的初始化阶段：向第一复位信号端输入第一复位信号，以使所述第一复位子电路将来自初始化信号端的初始化信号传输至所述第三节点；向第一扫描端输入第一扫描信号，以使所述写入子电路将所述第三节点上的所述初始化信号传输至第一节点，以对所述第一节点进行复位；在一图像帧的数据写入阶段：向第一扫描端输入所述第一扫描信号，向第二扫描端输入第二扫描信号，并向数据端输入数据信号，以使所述写入子电路将所述数据端接收的数据信号写入至所述第一节点，对所述驱动晶体管进行阈值电压补偿；在一图像帧的发光阶段：向第一使能信号端输入第一使能信号，并向第二使能信号端输入第二使能信号，以使所述发光控制子电路将第一电压端的电压信号传输至第二节点，并将所述驱动晶体管输出的电流传输至所述发光器件，使所述发光器件发光。
在一些实施例中，所述驱动方法还包括：在一图像帧的初始化阶段，向所述数据端输入所述数据信号。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1A为相关技术提供的一种驱动电路的结构图；
图1B为相关技术提供的另一种驱动电路的结构图；
图1C为相关技术提供的一种像素电路中驱动晶体管栅极电压变化的示意图；
图2为本公开实施例提供的一种显示面板的俯视结构图；
图3A为本公开实施例提供的一种像素电路的结构图；
图3B为本公开实施例提供的一种像素电路和相关技术提供的一种像素电路中的驱动晶体管栅极电压的模拟结果图；
图4为本公开实施例提供的一种像素电路的驱动方法流程图；
图5为本公开实施例提供的另一种像素电路的结构图；
图6A为本公开实施例提供的一种显示面板的电路连接图；
图6B为本公开实施例提供的另一种显示面板的电路连接图；
图6C为本公开实施例提供的又一种显示面板的电路连接图；
图7为本公开实施例提供的一种像素电路的具体结构图；
图8为图7所示的像素电路的时序控制图；
图9A为图7所示的像素电路在初始化阶段的示意图；
图9B为图7所示的像素电路在数据写入阶段的示意图；
图9C为图7所示的像素电路在发光阶段的示意图；
图10为本公开实施例提供的另一种像素电路的具体结构图；
图11为图10所示的像素电路的时序控制图；
图12A为图10所示的像素电路在初始化阶段的示意图；
图12B为图10所示的像素电路在数据写入阶段的示意图；
图13为本公开实施例提供的一种像素电路中各信号的模拟结果图；
图14为本公开实施例提供的又一种显示面板的电路连接图；
图15为图14所示显示面板中像素电路的时序控制图；
图16为本公开实施例提供的又一种像素电路的结构图；
图17为图16所示的像素电路的具体结构图；
图18为图17所示的像素电路的时序控制图；
图19为本公开实施例提供的另一种像素电路中各信号的模拟结果图；
图20为本公开实施例提供的又一种像素电路的结构图；
图21为图20所示的像素电路的具体结构图；
图22为图21所示的像素电路的时序控制图；
图23A为图21所示的像素电路在初始化阶段的示意图；
图23B为图21所示的像素电路在数据写入阶段的示意图；
图23C为图21所示的像素电路在发光阶段的示意图；
图24为本公开实施例提供的另一种像素电路中各信号的模拟结果图；
图25为本公开实施例提供的又一种像素电路的具体结构图；
图26为图25所示的像素电路的时序控制图；
图27A为图25所示的像素电路在初始化阶段的示意图；
图27B为图25所示的像素电路在数据写入阶段的示意图；
图27C为图25所示的像素电路在发光阶段的示意图；
图28为本公开实施例提供的另一种像素电路中各信号的模拟结果图；
图29为本公开实施例提供的另一种像素电路和相关技术提供的一种像素电路中的驱动晶体管栅极电压的模拟结果图；
图30A为本公开实施例提供的又一种像素电路的结构图；和
图30B为图30A所示的像素电路的具体结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在 本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。
发光二极管(例如有机发光二极管)为电流驱动型器件，如图1A所示为相关技术中的一种用于驱动该发光二极管的驱动电路，该驱动电路由一个驱动晶体管Td、一个开关晶体管Ts和一个存储电容Cst组成。在该驱动电路驱动发光二极管L发光时，开关晶体管Ts的栅极接收扫描信号端G的扫描信号，开关晶体管Ts导通，数据信号端DE的数据信号通过开关晶体管Ts输入到驱动晶体管Td的栅极，驱动晶体管Td打开，第一电压端VDD、发光二极管L和第二电压端VSS导通，驱动晶体管Td产生的驱动电流驱动发光二极管L发光。在此过程中，数据信号端DE上的数据信号向导通的开关晶体管Ts所连接的存储电容Cst进行充电，存储电容Cst存储的电能使驱动晶体管Td保持开启，以维持一帧画面显示所需的时间。
驱动晶体管Td的饱和电流公式为：
I＝K(V gs-V th) 2  (1)
其中，K为与驱动晶体管Td本身特性有关的系数，Vgs为驱动晶体管Td的栅源电压，Vth为驱动晶体管Td的阈值电压。
在显示装置中，显示装置通常包括多个发光二极管L，相应的驱动这些发光二极管L发光的驱动电路也有多个。由于工艺制程的差异以及温度、器件老化等原因的影响，驱动晶体管Td的阈值电压Vth会产生漂移的现象，从而导致驱动晶体管Td提供给发光二极管L的驱动电流偏离目标电流值。由于不同驱动电路中的各个驱动晶体管Td的阈值电压Vth可能不同，因此，可能会导致各发光二极管L的发光亮度不一致，从而导致显示装置的显示不均匀。
为了改善驱动晶体管Td的阈值电压Vth漂移造成的影响，如图1B所示，在如图1A所示的驱动电路基础上增加了阈值电压补偿子电路101，以在驱动电路驱动发光二极管L发光前对驱动晶体管Td的阈值电压Vth进行补偿，消除阈值电压Vth漂移对显示装置的影响。
此外，在一帧画面显示完成，进行下一帧画面显示前，驱动晶体管Td的栅极可能存在残余电压。为了消除一帧画面残余的电压对下一帧画面显示的影响，如图1B所示，驱动电路中还包括复位子电路102，以在下一帧画面显示前，对驱动晶体管Td的栅极进行复位。
在相关技术中，如图1B所示，阈值电压补偿子电路101和复位子电路 102均电连接至第一节点N1(驱动晶体管Td的栅极)，导致第一节点N1的电压受到阈值电压补偿子电路101和复位子电路102中的晶体管的影响。由于阈值电压补偿子电路101和复位子电路102均包括至少一个晶体管，晶体管存在漏电流，因此，会影响第一节点N1上的电压，从而导致Vgs发生变化。由公式1可知，Vgs变化，可能导致驱动电流I发生变化，从而导致发光二极管L的发光亮度改变，导致显示装置的显示画面发生闪烁(Flicker)现象。
在相关技术中，Flicker测试结果如表1所示。
表1
Figure PCTCN2021087044-appb-000001
如表1所示，在显示装置以低驱动频率(例如低于40Hz)驱动的情况下，显示装置M1和显示装置M2均存在Flicker现象，且随着驱动频率的降低，Flicker现象越严重。例如在驱动频率为40Hz时，Flicker现象为等级一(L1)，在驱动频率为20Hz时，Flicker现象为等级三(L3)。当驱动频率为15Hz时，显示装置出现滚动异常显示，当驱动频率为7.5Hz时，显示装置出现严重的滚动异常显示。
上述Flicker现象产生原因为：如图1C所示，在发光阶段开始时，第一节点N1的电压为V1，在发光阶段持续时间内，阈值电压补偿子电路101和复位子电路102中的晶体管处于关闭状态，由于晶体管存在漏电流，导致在发光阶段，第一节点N1的电压不断变化。在发光阶段结束时，第一节点N1的电压为V2，在发光阶段的持续时间内，第一节点N1的电压变化量为△V。频率越低，一帧的时间越长，△V越大，发光二极管LED的亮度改变越剧烈，从而Flicker现象越严重。
本公开的一些实施例提供一种显示面板，如图2所示，该显示面板包括多个像素电路100。
在一些实施例中，如图2所示，该显示面板具有多个呈阵列排布的亚像素区P，每个亚像素区P设置有一个像素电路100。
如图3A所示，本公开一些实施例提供的像素电路100包括：驱动子电路10、第一复位子电路20、写入子电路30、发光器件40和发光控制子电路50。
驱动子电路10包括：驱动晶体管Td和存储电容Cst。驱动晶体管Td的栅极与第一节点N1连接，驱动晶体管Td的第一极与第二节点N2连接，驱动晶体管Td的第二极与第三节点N3连接。存储电容Cst包括第一存储电极和第二存储电极，第一存储电极与第一节点N1连接，第二存储电极与第一电压端VDD连接。
驱动晶体管Td是指向发光器件40提供驱动电流的晶体管，驱动晶体管Td的宽长比大于起开关作用的晶体管的宽长比。
第一复位子电路20，至少连接第三节点N3、第一复位信号端RE1和初始化信号端INI。第一复位信号端RE1被配置为接收第一复位信号，并向第一复位子电路20输出该第一复位信号。初始化信号端INI被配置为接收初始化信号，并向第一复位子电路20输出该初始化信号。
第一复位子电路20被配置为在初始化阶段，至少在第一复位信号端RE1接收的第一复位信号的控制下，将来自初始化信号端INI的初始化信号传输至第三节点N3。
写入子电路30，连接第一扫描端G1、第二扫描端G2、数据端DE、第一节点N1、第二节点N2和第三节点N3。第一扫描端G1被配置为接收第一扫描信号，并向写入子电路30输出该第一扫描信号。第二扫描端G2被配置为接收第二扫描信号，并向写入子电路30输出该第二扫描信号。数据端DE被配置为接收数据信号并向写入子电路30输出该数据信号。
写入子电路30被配置为：在初始化阶段，在第一扫描端G1接收的第一扫描信号的控制下，将第三节点N3上的初始化信号传输至第一节点N1，以对第一节点N1进行复位；在数据写入阶段，在第一扫描端G1接收的第一扫描信号和第二扫描端G2的接收的第二扫描信号的控制下，将数据端DE接收的数据信号写入至第一节点N1并对驱动晶体管Td进行阈值电压补偿。
发光器件40，包括阳极和阴极，阴极连接第二电压端VSS。示例地，该发光器件为有机发光二极管(organic light emitting diode，OLED)、微型发光二极管(Micro Light Emitting Diode，Micro LED)，迷你发光二极管(Mini Light Emitting Diode，Mini LED)等。
发光控制子电路50，连接第二节点N2、第三节点N3、第一电压端VDD、第一使能信号端EM1、第二使能信号端EM2和发光器件40的阳极。第一电压端VDD被配置为接收电压信号，并向发光控制子电路50输出该电压信号。 第一使能信号端EM1被配置为接收第一使能信号，并向发光控制子电路50输出该第一使能信号。第二使能信号端EM2被配置为接收第二使能信号，并向发光控制子电路50输出该第二使能信号。此处，第一电压端VDD的电压信号为高电压信号，第二电压端VSS的电压信号为低电平信号。
发光控制子电路50被配置为在发光阶段，在第一使能信号端EM1接收的第一使能信号和第二使能信号端EM2接收的第二使能信号的控制下，将第一电压端VDD的电压信号传输至第二节点N2，并将驱动晶体管Td输出的电流传输至发光器件40，以使发光器件40发光。
本公开一些实施例提供的像素电路100，写入子电路30与第一节点N1(驱动晶体管Td的栅极)连接，第一复位子电路20与第三节点N3连接，与相关技术中的像素电路相比，只有写入子电路30与驱动晶体管Td的栅极直接连接。这样一来，对驱动晶体管Td的栅极电压的影响较小，在发光阶段，驱动晶体管Td的栅极的电压的变化量△V减小，从而对发光器件40的发光性能影响降低，进而可以改善显示面板的发光性能，降低Flicker现象的发生几率。
如图3B所示，为本公开的实施例提供的像素电路100以及相关技术提供的驱动电路中，驱动晶体管Td的栅极在一帧时间内的电压的模拟结果图。由图3B所示，在发光阶段，相关技术提供的驱动电路的驱动晶体管Td的栅极的电压由3.4V变为2.2V，电压变化量△V达到1.2V。本公开实施例提供的像素电路100的驱动晶体管Td的栅极的电压由3.6V变为2.9V，电压变化量△V仅为0.7V。由此可知，本公开实施例提供的像素电路100能够有效保持驱动晶体管Td的栅极电压，有利于改善Flicker现象。
本公开的一些实施例提供一种上述像素电路100的驱动方法。如图4所示，该方法包括S1-S3。
S1、在一图像帧的初始化阶段：向第一复位信号端RE1输入第一复位信号，以使第一复位子电路20将来自初始化信号端INI的初始化信号传输至第三节点N3。向第一扫描端G1输入第一扫描信号，以使写入子电路30将第三节点N3上的初始化信号传输至第一节点N1，以对第一节点N1进行复位。
S2、在一图像帧的数据写入阶段：向第一扫描端G1输入第一扫描信号，向第二扫描端G2输入第二扫描信号，并向数据端DE输入数据信号，以使写入子电路20将数据端DE接收的数据信号写入至第一节点N1，对驱动晶体管Td进行阈值电压补偿。
S3、在一图像帧的发光阶段：向第一使能信号端EM1输入第一使能信号， 并向第二使能信号端EM2输入第二使能信号，以使发光控制子电路50将第一电压端VDD的电压信号传输至第二节点N2，并将驱动晶体管Td输出的电流传输至发光器件40，使发光器件40发光。
在一些实施例中，像素电路100的驱动方法还包括：在一图像帧的初始化阶段，向数据端DE输入数据信号，以进行预充电，这样有利于数据信号写入。
在一些实施例中，如图5所示，发光控制子电路50包括第一子电路51和第二子电路52。
第一子电路51连接第二节点N2、第一电压端VDD和第一使能信号端EM1。
第一子电路51被配置为在发光阶段，在第一使能信号端EM1的第一使能信号的控制下，将第一电压端VDD的电压信号传输至第二节点N2。
第二子电路52连接第三节点N3、第二使能信号端EM2和发光器件40的阳极。
第二子电路52被配置为在发光阶段，在第二使能信号端EM2的第二使能信号的控制下，将驱动晶体管Td输出的电流传输至发光器件40。
在一些实施例中，如图5所示，写入子电路30包括第三子电路31和第四子电路32。
第三子电路31连接第二扫描端G2、数据端DE和第二节点N2。
第三子电路31被配置为在第二扫描端G2的第二扫描信号的控制下，至少在数据写入阶段开启，将数据端DE接收的数据信号传输至第二节点N2。
第四子电路32连接第一扫描端G1、第一节点N1和第三节点N3。
第四子电路32被配置为在第一扫描端G1接收的第一扫描信号的控制下，在初始化阶段和数据写入阶段开启，并在初始化阶段将第三节点N3上的初始化信号传输至第一节点N1，在数据写入阶段将第二节点N2的数据信号写入至第一节点N1并对驱动晶体管Td进行阈值电压补偿。
以显示面板上的2×2个阵列排布的亚像素区P为例。在一些实施例中，如图6A所示，显示面板还包括多条第一扫描线GL1、多条第二扫描线GL2、多条第一使能信号线EML1、多条第二使能信号线EML2和多条第一复位信号线RL1。
位于同一行的所有像素电路100连接的第一扫描端G1和第二扫描端G2分别连接第一扫描线GL1和第二扫描线GL2。位于同一行的所有像素电路100连接的第一复位信号端RE1连接同一条第一复位信号线RL1。位于同一行的 所有像素电路100连接的第一使能信号端EM1连接同一条第一使能信号线EML1。位于同一行的所有像素电路100连接的第二使能信号端EM2连接同一条第二使能信号线EML2。
第一扫描线GL1被配置为向一行像素电路100连接的第一扫描端G1提供第一扫描信号。第二扫描线GL2被配置为向一行像素电路100连接的第二扫描端G2提供第二扫描信号。第一复位信号线RL1被配置为向一行像素电路100连接的第一复位信号端RE1提供第一复位信号。第一使能信号线EML1被配置为向一行像素电路100连接的第一使能信号端EM1提供第一使能信号。第二使能信号线EML2被配置为向一行像素电路100连接的第二使能信号端EM2提供第二使能信号。
如图6A所示，显示面板还包括多条数据信号线DL和多条初始化信号线IL。
在一些实施例中，位于同一列的所有像素电路100连接的数据端DE连接同一条数据信号线DL。位于同一列的所有像素电路100连接的初始化信号端INI连接同一条初始化信号线IL。
数据信号线DL被配置为向一列像素电路100连接的数据端DE提供数据信号。初始化信号线IL被配置为向一列像素电路100连接的初始化信号端INI提供初始化信号。
在一些实施例中，第一扫描端G1和第二扫描端G2连接同一扫描端。在第一扫描端G1和第二扫描端G2连接同一扫描端的情况下，第一扫描信号和第二扫描信号为相同的扫描信号。
示例地，如图6B所示，显示面板包括多条扫描线GL，位于同一行的所有像素电路100连接的第一扫描端G1和第二扫描端G2均连接一条扫描线GL。即，位于同一行的所有像素电路100连接的扫描端G连接一根扫描线GL。
在此情况下，第三子电路31被配置为在第二扫描端G2的第二扫描信号的控制下，在初始化阶段和数据写入阶段均开启。
在一些实施例中，第一使能信号端EM1和第二使能信号端EM2连接同一使能信号端。在第一使能信号端EM1和第二使能信号端EM2连接同一使能信号端的情况下，第一使能信号和第二使能信号为相同的使能信号。
示例地，如图6C所示，显示面板包括多条使能信号线EML，位于同一行的所有像素电路100连接的第一使能信号端EM1和第二使能信号端EM2连接一条使能信号线EML。即，位于同一行的所有像素电路100连接的使能 信号端EM连接一条使能信号线EML。
在一些示例中，如图7所示，第一复位子电路20包括第一晶体管T1，第一晶体管T1的栅极连接第一复位信号端RE1，第一晶体管T1的第一极连接初始化信号端INI，第一晶体管T1的第二极连接第三节点N3。
在另一些示例中，第一复位子电路20包括并联或串联的多个第一晶体管T1。在第一复位子电路20包括并联的多个第一晶体管T1的情况下，该多个第一晶体管T1的栅极均连接第一复位信号端RE1，该多个第一晶体管T1的第一极均连接初始化信号端INI，该多个第一晶体管T1的第二极均连接第三节点N3。在第一复位子电路20包括串联的多个第一晶体管T1的情况下，该多个第一晶体管T1依次连接(第一个第一晶体管T1的第二极连接第二个第一晶体管T1的第一极，依次类推)，该多个第一晶体管T1的栅极均连接第一复位信号端RE1，该多个第一晶体管T1中的第一个第一晶体管T1的第一极连接初始化信号端INI，最后一个第一晶体管T1的第二极连接第三节点N3。上述仅仅是对第一复位子电路20的举例说明，其它与该第一复位子电路20功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
在一些示例中，如图7所示，第一子电路51包括第三晶体管T3，第三晶体管T3的栅极连接第一使能信号端EM1，第三晶体管T3的第一极连接第一电压端VDD，第三晶体管T3的第二极连接第二节点N2。
在另一些示例中，第一子电路51包括并联或串联的多个第三晶体管T3。在第一子电路51包括并联的多个第三晶体管T3的情况下，该多个第三晶体管T3的栅极均连接第一使能信号端EM1，该多个第三晶体管T3的第一极均连接第一电压端VDD，该多个第三晶体管T3的第二极均连接第二节点N2。在第一子电路51包括串联的多个第三晶体管T3的情况下，该多个第三晶体管T3依次连接(第一个第三晶体管T3的第二极连接第二个第三晶体管T3的第一极，依次类推)，该多个第三晶体管T3的栅极均连接第一使能信号端EM1，该多个第三晶体管T3中的第一个第三晶体管T3的第一极连接第一电压端VDD，最后一个第三晶体管T1的第二极连接第二节点N2。上述仅仅是对第一子电路51的举例说明，其它与该第一子电路51功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
在一些示例中，如图7所示，第二子电路52包括第四晶体管T4，第四晶体管T4的栅极连接第二使能信号端EM2，第四晶体管T4的第一极连接第三节点N3，第四晶体管T4的第二极连接发光器件40的阳极。
在另一些示例中，第二子电路52包括并联或串联的多个第四晶体管T4。 在第二子电路52包括并联的多个第四晶体管T4的情况下，该多个第四晶体管T4的栅极均连接第二使能信号端EM2，该多个第四晶体管T4的第一极均连接第三节点N3，该多个第四晶体管T4的第二极均连接发光器件40的阳极。在第二子电路52包括串联的多个第四晶体管T4的情况下，该多个第四晶体管T4依次连接(第一个第四晶体管T4的第二极连接第二个第四晶体管T4的第一极，依次类推)，该多个第四晶体管T4的栅极均连接第二使能信号端EM2，该多个第四晶体管T4中的第一个第四晶体管T4的第一极连接第三节点N3，最后一个第四晶体管T4的第二极连接发光器件40的阳极。上述仅仅是对第二子电路52的举例说明，其它与该第二子电路52功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
在一些示例中，如图7所示，第三子电路31包括第五晶体管T5，第五晶体管T5的栅极连接第二扫描端G2，第五晶体管T5的第一极连接数据端DE，第五晶体管T5的第二极连接第二节点N2。
在另一些示例中，第三子电路31包括并联或串联的多个第五晶体管T5。在第三子电路31包括并联的多个第五晶体管T5的情况下，该多个第五晶体管T5的栅极均连接第二扫描端G2，该多个第五晶体管T5的第一极均连接数据端DE，该多个第五晶体管T5的第二极均连接第二节点N2。在第三子电路31包括串联的多个第五晶体管T5的情况下，该多个第五晶体管T5依次连接(第一个第五晶体管T5的第二极连接第二个第五晶体管T5的第一极，依次类推)，该多个第五晶体管T5的栅极均连接第二扫描端G2，该多个第五晶体管T5中的第一个第五晶体管T5的第一极连接数据端DE，最后一个第五晶体管T5的第二极连接第二节点N2。上述仅仅是对第三子电路31的举例说明，其它与该第三子电路31功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
在一些示例中，如图7所示，第四子电路32包括第六晶体管T6，第六晶体管T6的栅极连接第一扫描端G1，第六晶体管T6的第一极连接第三节点N3，第六晶体管T6的第二极连接第一节点N1。
在另一些示例中，第四子电路32包括并联或串联的多个第六晶体管T6。在第四子电路32包括并联的多个第六晶体管T6的情况下，该多个第六晶体管T6的栅极均连接第一扫描端G1，该多个第六晶体管T6的第一极均连接第三节点N3，该多个第六晶体管T6的第二极均连接第一节点N1。在第四子电路32包括串联的多个第六晶体管T6的情况下，该多个第六晶体管T6依次连接(第一个第六晶体管T6的第二极连接第二个第六晶体管T6的第一极，依 次类推)，该多个第六晶体管T6的栅极均连接第一扫描端G1，该多个第六晶体管T6中的第一个第六晶体管T6的第一极连接第三节点N3，最后一个第六晶体管T6的第二极连接第一节点N1。上述仅仅是对第四子电路32的举例说明，其它与该第四子电路32功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
需要说明的是，本公开实施例对各个子电路中的晶体管的类型不做限定，即上述驱动晶体管Td、第一晶体管T1、第三晶体管T3、第四晶体管T4以及第五晶体管T5、第六晶体管T6可以均为P型晶体管或者均为N型晶体管。以下以上述驱动晶体管Td、第一晶体管T1、第三晶体管T3、第四晶体管T4以及第五晶体管T5、第六晶体管T6均为P型晶体管进行说明。
此外，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。对于P型驱动晶体管Td，通常将第二极称为漏极，将第一极称为源极；对于N型驱动晶体管Td，通常将第一极称为漏极，将第二极称为源极。
下面提供几种可能的实施方式，以对像素电路100及其驱动过程，进行说明。
像素电路100在一图像帧的驱动过程可以分为初始化阶段P1、数据写入阶段P2和发光阶段P3。
第一种可能的实施方式：
如图7所示，第一复位子电路20包括第一晶体管T1，第一子电路51包括第三晶体管T3，第二子电路52包括第四晶体管T4，第三子电路31包括第五晶体管T5，第四子电路32包括第六晶体管T6。第一使能信号端EM1和第二使能信号端EM2连接同一使能信号端EM。
如图8所示，在初始化阶段P1：第一复位端RE1输出的第一复位信号和第一扫描端G1输出的第一扫描信号的电位为低电平，使能信号端EM输出的使能信号以及第二扫描端G2输出的第二扫描信号的电位为高电平。
图7中第一复位子电路20在第一复位信号的控制下，将来自初始化信号端INI的初始化信号传输至第三节点N3。第四子电路32在第一扫描信号的控制下，将第三节点N3上的初始化信号传输至第一节点N1，以通过初始化信号对第一节点N1进行初始化，避免上一帧残留于第一节点N1的电信号对本帧画面造成影响。
如图9A(为图7所示的像素电路100在初始化阶段P1的等效电路图)所示，第一复位信号控制第一晶体管T1开启，初始化信号端INI输入的初始化信号经第一晶体管T1传输至第三节点N3。第一扫描信号控制第六晶体管T6开启，初始化信号经第六晶体管T6传输至第一节点N1。
此外，第一子电路51、第二子电路52和第三子电路31在初始化阶段P1均处于关闭状态。在此情况下，如图9A所示，第三晶体管T3、第四晶体管T4和第五晶体管T5均截止。如图9A所示，处于截止状态的晶体管以打“×”表示。
在初始化阶段P1结束时，第一节点N1的电位为V init。
数据写入阶段P2：第一扫描端G1输出的第一扫描信号和第二扫描端G2输出的第二扫描信号的电位为低电平，第一复位信号端RE1输出的第一复位信号以及使能信号端EM输出的使能信号的电位为高电平。
图7中第三子电路31在第二扫描信号的控制下，将来自数据端DE的数据信号传输至第二节点N2。第四子电路32在第一扫描信号的控制下，将驱动晶体管Td的第二极和栅极短接，形成二极管结构，将第二节点N2上的数据信号写入至第一节点N1，并对驱动晶体管Td进行阈值电压补偿。
如图9B(为图7所示的像素电路100在数据写入阶段P2的等效电路图)所示，在数据写入阶段P2，第一复位信号的电位为高电平，第一晶体管T1截止。第二扫描信号的电位为低电平，控制第五晶体管T5开启，来自数据端DE的数据信号经第五晶体管T5传输至第二节点N2。与初始化阶段P1相同，在数据写入阶段P2第一扫描信号的电位仍为低电平，第六晶体管T6保持开启，将驱动晶体管Td的第二极和栅极短接，形成二极管结构，第二节点N2上的数据信号通过驱动晶体管Td和第六晶体管T6传输至第一节点N1。当第一节点N1的电位与第二节点N2的电位的压差减小至驱动晶体管Td的阈值电压Vth时，驱动晶体管Td截至。
在数据写入阶段P2结束时，第一节点N1的电位为V data+Vth，并将该电位存储于存储电容Cst中。
发光阶段P3：使能信号端EM输出的使能信号的电位为低电平，第一扫描端G1输出的第一扫描信号的电位、第二扫描端G2输出的第二扫描信号的电位和第一复位信号端RE1输出的第一复位信号的电位均为高电平。
图7中第一子电路51在使能信号的控制下，将第一电压端VDD的电压信号传输至第二节点N2。驱动晶体管Td在第一节点N1的电压和第一电压端VDD的电压信号的控制下，产生驱动电流。第二子电路52在使能信号的控 制下，将驱动晶体管Td输出的驱动电流，传输至发光器件40。
如图9C(为图7所示的像素电路100在数据发光阶段P3的等效电路图)所示，第一复位信号的电位为高电平，第一晶体管T1截止。第一扫描信号的电位为高电平，第六晶体管T6截止。第二扫描信号的电位为高电平，第五晶体管T5截止。使能信号的电位为低电平，第三晶体管T3和第四晶体管T4开启。第一电压端VDD的电压信号经过第三晶体管T3传输至第二节点N2。驱动晶体管Td在第一节点N1的电压和第一电压端VDD的电压信号的控制下，产生驱动电流。驱动电流经第四晶体管T4传输至发光器件40，使发光器件40进行发光。
在发光阶段P3，第一节点N1的电位为V data+Vth，第二节点N2的电位为Vdd，驱动晶体管Td的Vgs＝Vg-Vs＝V data+Vth-Vdd。
驱动晶体管Td开启后，当驱动晶体管Td的栅-源电压Vgs减去驱动晶体管Td的阈值电压Vth得到的值小于等于驱动晶体管Td的漏-源电压Vds时，即Vgs-Vth≤Vds时，驱动晶体管Td能够处于饱和开启状态，此时流过驱动晶体管Td的驱动电流I为：
Figure PCTCN2021087044-appb-000002
其中，W/L为驱动晶体管Td的宽长比，Cox为沟道绝缘层的介电常数，μ为沟道载流子迁移率。
上述参数只与驱动晶体管Td的结构、数据电压端DE输出的数据信号和第一电压端VDD输出的电压信号有关，与驱动晶体管Td的阈值电压Vth无关，从而消除了驱动晶体管Td的阈值电压Vth对发光器件40的发光亮度的影响，从而可提高显示面板的亮度均一性。
第二种可能的实施方式：
如图10所示，在第一种可能的实施方式基础上，第一扫描端G1和第二扫描端G2连接同一扫描端G。基于此，图10所示的像素电路100的时序控制图如图11所示。
如图11所示，在初始化阶段P1：第一复位信号端RE1输出的第一复位信号的电位和扫描端G输出的扫描信号的电位为低电平，使能信号端EM输出的使能信号的电位为高电平。
如图12A(为图10所示的像素电路100在初始化阶段P1的等效电路图)所示，在初始化阶段P1，第一复位信号的电位为低电平，控制第一晶体管T1开启，初始化信号端INI输入的初始化信号经第一晶体管T1传输至第三节点N3。扫描信号的电位为低电平，第六晶体管T6开启，初始化信号经第六晶体管T6传输至第一节点N1。
此外，使能信号的电位在初始化阶段P1为高电平，第一子电路51和第二子电路52处于关闭状态。如图11和图12A所示，第三晶体管T3和第四晶体管T4截止。
如图11所示，在数据写入阶段P2：扫描端G输出的扫描信号的电位为低电平，第一复位信号端RE1输出的第一复位信号的电位、使能信号端EM输出的使能信号的电位为高电平。
如图12B(为图10所示的像素电路100在初始化阶段P2的等效电路图)所示，在数据写入阶段P2，第一复位信号的电位为高电平，第一晶体管T1截止。扫描信号的电位为低电平，控制第五晶体管T5和第六晶体管T6开启，来自数据端DE的数据信号经第五晶体管T5传输至第二节点N2。第六晶体管T6开启，将驱动晶体管Td的第二极和栅极短接，形成二极管结构，第二节点N2上的数据信号通过驱动晶体管Td和第六晶体管T6传输至第一节点N1。当第一节点N1的电位与第二节点N2的电位的压差减小至驱动晶体管Td的阈值电压Vth时，驱动晶体管Td截至。
发光阶段P3，各晶体管的开启状态以及信号的传输过程，与第一种可能的实施方式中发光阶段P3相同，此处不再赘述。
需要说明的是，在第二种可能的实施方式中，在初始化阶段P1，由于扫描信号的电位为低电平，第五晶体管T5也处于开启状态，数据端DE也会输入数据信号，但是由于数据端DE和第一节点N1的电压压差小于数据端DE和初始化信号端INI的电压压差，并且数据端DE的数据信号传输到第一节点N1需要经过第五晶体管T5、驱动晶体管Td和第六晶体管T6，因此在初始化阶段P1，数据信号对第一节点N1的电压的影响较小。
如图13所示，为第二种可能的实施方式的像素电路100在一图像帧的驱动过程中，各信号的模拟结果。由图13可见，第一节点N1能够进行正常的初始化和数据信号的写入。
第三种可能的实施方式：
如图14所示，位于同一行的所有像素电路连接的第一扫描端G1和第二扫描端G2均连接一条扫描线GL，位于第n行的所有像素电路100连接的第 一复位信号端RE1(n)连接与第n-1行像素电路100连接的扫描线GL(n-1)。在此情况下，该像素电路100对应的时序控制图如图15所示，其驱动过程与上述第二种可能的实施方式相似，此处不再赘述。所不同的是，在第三种可能的实施方式中，在初始化阶段P1，与第n行像素电路100连接的第一复位信号端RE1(n)的第一复位信号由第n-1行的扫描线GL(n-1)提供。此处，n为大于等于2的正整数。
位于第n行的所有像素电路100连接的第一复位信号端RE1(n)连接与第n-1行像素电路100对应的扫描线GL(n-1)，不用单独设置第一复位信号线RL1，可以减少显示面板的布线数量。
第四种可能的实施方式：
如图16所示，初始化信号端INI与发光器件40的阳极连接。在此情况下，可用发光器件40的阳极的残留电压对第一节点N1进行复位，从而可以减少显示面板上的布线数量。
示例地，像素电路100的结构如图17所示，对应的时序控制图如图18所示，该像素电路100的驱动过程与上述第一种可能的实施方式中相似。所不同的是，在第四种可能的实施方式中，在初始化阶段P1，利用发光器件40的阳极的残留电压对第一节点N1进行复位。
如图19所示，为本公开第四种可能的实施方式的像素电路100在一图像帧的驱动过程中，各信号的模拟结果。由图19可见，第一节点N1能够进行正常的初始化和数据信号的写入。
第五种可能的实施方式：
如图20所示，第二子电路52与第一复位子电路20复用，第一复位信号端RE1与第二使能信号端EM2为同一信号端EM_S。
该信号端EM_S被配置在初始化阶段P1输出第一复位信号，在发光阶段P3输出第二使能信号。
示例地，像素电路100的结构如图21所示，对应的时序控制图如图22所示。该像素电路100的驱动过程如下。
如图22所示，信号端EM_S输出控制信号，该控制信号包括第一复位信号和第二使能信号。第一扫描端G1输出第一扫描信号，第二扫描端G2输出第二扫描信号。第一使能信号端EM1输出第一使能信号。
在初始化阶段P1：第一复位信号的电位为低电平。第一扫描信号的电位为低电平。第一使能信号和第二扫描信号的电位均为高电平。
如图23A(为图21所示的像素电路100在初始化阶段P1的等效电路图) 所示，在初始化阶段P1，第一复位信号的电位为低电平，控制第四晶体管T4开启，发光器件40的阳极电压经第四晶体管T4传输至第三节点N3。第一扫描信号的电位为低电平开启信号，第六晶体管T6开启，第三节点N3的电压经第六晶体管T6传输至第一节点N1，从而对第一节点N1进行复位。
第一子电路51和第三子电路31在初始化阶段P1处于关闭状态。在此情况下，如图23A所示，第三晶体管T3和第五晶体管T5截止。
数据写入阶段P2：第一扫描信号和第二扫描信号的电位为低电平。控制信号的电位为高电平。第一使能信号的电位为高电平。
如图23B(为图21所示的像素电路100在数据写入阶段P2的等效电路图)所示，在数据写入阶段P2，控制信号的电位为高电平，第四晶体管T4截止。第二扫描信号的电位为低电平，控制第五晶体管T5开启，来自数据端DE的数据信号经第五晶体管T5传输至第二节点N2。与初始化阶段P1相同，在数据写入阶段P2中，第一扫描信号的电位仍为低电平，第六晶体管T6保持开启，将驱动晶体管Td的第二极和栅极短接，形成二极管结构，第二节点N2上的数据信号通过驱动晶体管Td和第六晶体管T6传输至第一节点N1。当第一节点N1的电位与第二节点N2的电位的压差减小至驱动晶体管Td的阈值电压Vth时，驱动晶体管Td截至。
发光阶段P3：第一使能信号的电位为低电平。第二使能信号的电位为低电平。第一扫描信号、第二扫描信号的电位为高电平。
如图23C(为图21所示的像素电路100在数据发光阶段P3的等效电路图)所示，在发光阶段P3，第一扫描信号的电位为高电平，第六晶体管T6截止。第二扫描信号的电位为高电平，第五晶体管T5截止。第一使能信号的电位和第二使能信号的电位均为低电平，第三晶体管T3和第四晶体管T4开启。第一电压端VDD的电压信号经过第三晶体管T3传输至第二节点N2。驱动晶体管Td在第一节点N1和第一电压端VDD的电压信号的控制下，产生驱动电流。驱动电流经第四晶体管T4传输至发光器件40，使发光器件40进行发光。
将第二子电路52与第一复位子电路20复用，从而可减少至少一个晶体管，进一步简化像素电路100。
如图24所示，为本公开第五种可能的实施方式的像素电路100在一图像帧的驱动过程中，各信号的模拟结果。由图24可见，第一节点N1能够进行正常的初始化和数据信号的写入。
第六种可能的实施方式：
如图25所示，第四子电路32包括第七晶体管T7和第八晶体管T8。
第七晶体管T7的栅极与第一扫描端G1连接，第七晶体管T7的第一极与第三节点N3连接，第七晶体管T7的第二极与第四节点N4连接。第八晶体管T8的栅极与第一扫描端G1连接，第八晶体管T8的第一极与第四节点N4连接，第八晶体管T8的第二极与第一节点N1连接。
在此基础上，如图25所示，第一复位子电路20包括第九晶体管T9和上述第七晶体管T7。
第九晶体管T9的栅极与第一复位信号端RE1连接，第九晶体管T9的第一极与初始化信号端INI连接，第九晶体管T9的第二极与第四节点N4连接。
第一子电路51、第二子电路52、第三子电路31的结构可参考第一种可能实施方式中第一子电路51、第二子电路52、第三子电路31，在此不再赘述。
第一扫描端G1和第二扫描端G2连接同一扫描端G。第一使能信号端EM1和第二使能信号端EM2连接同一使能信号端EM。
该像素电路100对应的时序控制图如图26所示。第一复位信号端RE1输出第一复位信号，扫描端G输出的扫描信号，使能信号端EM输出使能信号，初始化信号端INI输出初始化信号。
初始化阶段P1：第一复位信号的电位和扫描信号的电位为低电平，使能信号的电位为高电平。
如图27A(为图25所示的像素电路100在初始化阶段P1的等效电路图)所示，在初始化阶段P1，第一复位信号的电位为低电平，控制第九晶体管T9开启。初始化信号端INI输出的初始化信号经第九晶体管T9传输至第四节点N4。示例的，在初始化阶段P1，初始化信号的电位为第一电平，例如为-2.5V。扫描信号的电位为低电平，第七晶体管T7和第八晶体管T8开启，第一电平经第七晶体管T7和第八晶体管T8分别传输至第一节点N1和第三节点N3。
在初始化阶段P1，使能信号的电位为高电平，第三晶体管T3和第四晶体管T4截止。
示例地，在初始化阶段P1，数据端DE也可以输入数据信号，以进行预充电，有利于数据信号写入。
数据写入阶段P2：扫描信号的电位为低电平，第一复位信号的电位和使能信号的电位为高电平。
如图27B(为图25所示的像素电路100在数据写入阶段P2的等效电路图)所示，在数据写入阶段P2，第一复位信号的电位为高电平，第九晶体管T9截止。扫描信号的电位为低电平，第五晶体管T5开启，来自数据端DE的 数据信号经第五晶体管T5传输至第二节点N2。第七晶体管T7和第八晶体管T8开启，使驱动晶体管Td的第二极和栅极短接，形成二极管结构，第二节点N2上的数据信号通过驱动晶体管Td、第七晶体管T7和第八晶体管T8传输至第一节点N1。当第一节点N1的电位与第二节点N2的电位的压差减小至驱动晶体管Td的阈值电压Vth时，驱动晶体管Td截至。
发光阶段P3：第一复位信号和使能信号的电位为低电平，扫描信号的电位为高电平。
如图27C(为图25所示的像素电路100在数据发光阶段P3的等效电路图)所示，在发光阶段P3，第一复位信号的电位为低电平，控制第九晶体管T9开启。初始化信号的电位为第二电平，该第二电平经第九晶体管T9传输至第四节点N4。示例的，在发光阶段P3，第二电平例如为4.5V。
扫描信号的电位为高电平，第五晶体管T5、第七晶体管T7和第八晶体管T8截止。
使能信号的电位为低电平，第三晶体管T3和第四晶体管T4开启。第一电压端VDD的电压信号经过第三晶体管T3传输至第二节点N2。驱动晶体管Td在第一节点N1的电位和第一电压端VDD的电压信号的控制下，产生驱动电流。驱动电流经第四晶体管T4传输至发光器件40，使发光器件40进行发光。
在该像素电路中，在发光阶段P3，初始化信号的第二电平经第九晶体管T9传输至第四节点N4，且该第二电平为高电平，这样使第一节点N1和第四节点N4之间的压差减小，从而减小第一节点N1向第四节点N4的漏电流，进而可以更好地保持第一节点N1在一帧时间内的电压，进一步降低Flicker现象的发生几率。
如图28所示，为本公开第六种可能的实施方式的像素电路100在一图像帧的驱动过程中，各信号的模拟结果。由图28可见，第一节点N1能够进行正常的初始化和数据信号的写入。
如图29所示，为本公开第六种可能的实施方式的像素电路100以及相关技术提供的像素电路100的驱动晶体管Td的栅极在一帧时间内的电压的模拟结果图。在一帧时间内，相关技术提供的像素电路100的驱动晶体管Td的栅极的电压由5V变为3.4V，电压变化量△V达到1.6V；本公开实施例提供的像素电路100的驱动晶体管Td的栅极的电压由5V变为4.9V，电压变化量△V仅为0.1V。本公开实施例提供的像素电路100能够有效保持驱动晶体管Td的栅极电压，有利于改善Flicker现象，可用于超低频率(例如1Hz)等显示 面板。
第七种可能的实施方式：
在第一种、第二种、第三种、第六种可能的实施方式基础上，如图30A所示，像素电路100还包括第二复位子电路60，该第二复位子电路60连接发光器件40的阳极、第二复位信号端RE2和初始化信号端INI。第二复位信号端RE2被配置为接收第二复位信号，并向第二复位子电路60输出该第二复位信号。初始化信号端INI还被配置为向第二复位子电路60输出该初始化信号。
第二复位子电路60被配置为在初始化阶段P1或数据写入阶段P2，在第二复位信号端RE2接收的第二复位信号的控制下，将来自初始化信号端INI的初始化信号传输至发光器件40的阳极，对发光器件40的阳极进行复位。
第二复位子电路60可对发光器件40的阳极进行复位，避免在一帧画面结束时，发光器件40的阳极的残留电压对下一帧画面的影响。
在一些实施例中，上述第二复位信号端RE2和第一复位信号端RE1连接同一复位信号端。这样可简化像素电路100的结构。
需要说明的是，在第一复位信号端RE1和第二复位信号端RE2连接同一复位信号端的情况下，第一复位信号和第二复位信号为相同的复位信号。在此情况下，第二复位子电路60被配置为在初始化阶段P1，将来自初始化信号端INI的初始化信号传输至发光器件40的阳极，对发光器件40的阳极进行复位。
在一些示例中，如图30B所示，第二复位子电路60包括第二晶体管T2，第二晶体管T2的栅极连接第二复位信号端RE2，第二晶体管T2的第一极连接初始化信号端INI，第二晶体管T2的第二极连接发光器件40的阳极。
在另一些示例中，第二复位子电路60包括并联或串联的多个第二晶体管T2。在第二复位子电路60包括并联的多个第二晶体管T2的情况下，该多个第二晶体管T2的栅极均连接第二复位信号端RE2，该多个第二晶体管T2的第一极均连接初始化信号端INI，该多个第二晶体管T2的第二极均连接发光器件40的阳极。在第二复位子电路60包括串联的多个第二晶体管T2的情况下，该多个第二晶体管T2依次连接(第一个第二晶体管T2的第二极连接第二个第二晶体管T2的第一极，依次类推)，该多个第二晶体管T2的栅极均连接第二复位信号端RE2，该多个第二晶体管T2中的第一个第二晶体管T2的第一极连接初始化信号端INI，最后一个第二晶体管T2的第二极连接发光器件40的阳极。上述仅仅是对第二复位子电路60的举例说明，其它与该第二复位子电路60功能相同的结构在此不再一一赘述，但都应当属于本公开的 保护范围。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种像素电路，包括：
    驱动子电路，所述驱动子电路包括：
    驱动晶体管，所述驱动晶体管的栅极与第一节点连接，驱动晶体管的第一极与第二节点连接，驱动晶体管的第二极与第三节点连接；
    存储电容，包括第一存储电极和第二存储电极，所述第一存储电极与所述第一节点连接，所述第二存储电极与第一电压端连接；
    第一复位子电路，至少连接所述第三节点、第一复位信号端和初始化信号端；所述第一复位子电路被配置为在初始化阶段，至少在所述第一复位信号端接收的第一复位信号的控制下，将来自所述初始化信号端的初始化信号传输至所述第三节点；
    写入子电路，连接第一扫描端、第二扫描端、数据端、所述第一节点、所述第二节点和所述第三节点；所述写入子电路被配置为在所述初始化阶段，在所述第一扫描端接收的第一扫描信号的控制下，将所述第三节点上的所述初始化信号传输至所述第一节点，以对所述第一节点进行复位；在数据写入阶段，在所述第一扫描端接收的所述第一扫描信号和所述第二扫描端的接收的第二扫描信号的控制下，将所述数据端接收的数据信号写入至所述第一节点并对所述驱动晶体管进行阈值电压补偿；
    发光器件，包括阳极和阴极，所述阴极连接第二电压端；
    发光控制子电路，连接所述第二节点、所述第三节点、所述第一电压端、第一使能信号端、第二使能信号端和所述发光器件的阳极；所述发光控制子电路被配置为在发光阶段，在所述第一使能信号端接收的第一使能信号和所述第二使能信号端接收的第二使能信号的控制下，将所述第一电压端的电压信号传输至所述第二节点，并将所述驱动晶体管输出的电流传输至所述发光器件，以使所述发光器件发光。
  2. 根据权利要求1所述的像素电路，还包括：
    第二复位子电路，连接所述发光器件的阳极、第二复位信号端和所述初始化信号端；所述第二复位子电路被配置为在所述初始化阶段或所述数据写入阶段，在所述第二复位信号端接收的第二复位信号的控制下，将来自所述初始化信号端的所述初始化信号传输至所述发光器件的阳极，对所述阳极进行复位。
  3. 根据权利要求2所述的像素电路，其中，所述第一复位信号端和所述第二复位信号端连接同一复位信号端。
  4. 根据权利要求1所述的像素电路，其中，所述发光控制子电路包括第 一子电路和第二子电路；
    所述第一子电路连接所述第二节点、所述第一电压端和所述第一使能信号端；所述第一子电路被配置为在发光阶段，在所述第一使能信号端的所述第一使能信号的控制下，将所述第一电压端的电压信号传输至所述第二节点；
    所述第二子电路连接所述第三节点、所述第二使能信号端和所述发光器件的阳极；所述第二子电路被配置为在发光阶段，在所述第二使能信号端的所述第二使能信号的控制下，将所述驱动晶体管输出的电流传输至所述发光器件。
  5. 根据权利要求4所述的像素电路，其中，所述第一使能信号端、所述第二使能信号端连接同一使能信号端。
  6. 根据权利要求4所述的像素电路，其中，所述初始化信号端与所述发光器件的阳极连接。
  7. 根据权利要求4所述的像素电路，其中，所述第二子电路与所述第一复位子电路复用，所述第一复位信号端与所述第二使能信号端为同一信号端；
    所述信号端被配置在所述初始化阶段输出所述第一复位信号，在所述发光阶段输出所述第二使能信号。
  8. 根据权利要求1所述的像素电路，其中，所述第一扫描端和所述第二扫描端连接同一扫描端。
  9. 根据权利要求1所述的像素电路，其中，所述写入子电路包括第三子电路和第四子电路；
    所述第三子电路连接所述第二扫描端、所述数据端和所述第二节点；所述第三子电路被配置为在所述第二扫描端的所述第二扫描信号的控制下，至少在数据写入阶段开启，将所述数据端接收的数据信号传输至所述第二节点；
    所述第四子电路连接所述第一扫描端、所述第一节点和所述第三节点，所述第四子电路被配置为在所述第一扫描端接收的所述第一扫描信号的控制下，在所述初始化阶段和所述数据写入阶段开启，并在所述初始化阶段将所述第三节点上的所述初始化信号传输至所述第一节点，在所述数据写入阶段将所述第二节点的所述数据信号写入至所述第一节点并对所述驱动晶体管进行阈值电压补偿。
  10. 根据权利要求8所述的像素电路，其中，所述第一复位子电路包括第一晶体管，所述第一晶体管的栅极连接所述第一复位信号端，所述第一晶体管的第一极连接所述初始化信号端，所述第一晶体管的第二极连接所述第三节点。
  11. 根据权利要求2所述的像素电路，其中，所述第二复位子电路包括第二晶体管，所述第二晶体管的栅极连接所述第二复位信号端，所述第二晶体管的第一极连接所述初始化信号端，所述第二晶体管的第二极连接所述发光器件的阳极。
  12. 根据权利要求4所述的像素电路，其中，所述第一子电路包括第三晶体管，所述第三晶体管的栅极连接所述第一使能信号端，所述第三晶体管的第一极连接所述第一电压端，所述第三晶体管的第二极连接所述第二节点；
    所述第二子电路包括第四晶体管，所述第四晶体管的栅极连接所述第二使能信号端，所述第四晶体管的第一极连接所述第三节点，所述第四晶体管的第二极连接所述发光器件的阳极。
  13. 根据权利要求9所述的像素电路，其中，所述第三子电路包括第五晶体管，所述第五晶体管的栅极连接所述第二扫描端，所述第五晶体管的第一极连接所述数据端，所述第五晶体管的第二极连接所述第二节点。
  14. 根据权利要求13所述的像素电路，其中，所述第四子电路包括第六晶体管，所述第六晶体管的栅极连接所述第一扫描端，所述第六晶体管的第一极连接所述第三节点，所述第六晶体管的第二极连接所述第一节点。
  15. 根据权利要求13所述的像素电路，其中，所述第四子电路包括第七晶体管和第八晶体管；
    所述第七晶体管的栅极与所述第一扫描端连接，所述第七晶体管的第一极与所述第三节点连接，所述第七晶体管的第二极与第四节点连接；
    所述第八晶体管的栅极与所述第一扫描端连接，所述第八晶体管的第一极与所述第四节点连接，所述第八晶体管的第二极与所述第一节点连接。
  16. 根据权利要求15所述的像素电路，其中，所述第一复位子电路包括第九晶体管和所述第七晶体管；
    所述第九晶体管的栅极与所述第一复位信号端连接，所述第九晶体管的第一极与所述初始化信号端连接，所述第九晶体管的第二极与所述第四节点连接。
  17. 一种显示面板，包括至少一个如权利要求1-16任一项所述的像素电路。
  18. 根据权利要求17所述的显示面板，其中，所述显示面板具有多个呈阵列排布的亚像素区，每个亚像素区设置有一个所述像素电路；
    所述显示面板还包括多条扫描线，位于同一行的所有像素电路连接的第一扫描端和第二扫描端均连接一条扫描线；
    或者，
    所述显示面板还包括多条第一扫描线和多条第二扫描线，位于同一行的所有像素电路连接的第一扫描端和第二扫描端分别连接第一扫描线和第二扫描线。
  19. 根据权利要求18所述的显示面板，其中，位于同一行的所有像素电路连接的第一扫描端和第二扫描端均连接一条扫描线，位于第n行的所有像素电路连接的第一复位信号端连接与第n-1行像素电路对应的所述扫描线。
  20. 一种如权利要求1所述的像素电路的驱动方法，包括：
    在一图像帧的初始化阶段：向第一复位信号端输入第一复位信号，以使所述第一复位子电路将来自初始化信号端的初始化信号传输至所述第三节点；向第一扫描端输入第一扫描信号，以使所述写入子电路将所述第三节点上的所述初始化信号传输至第一节点，以对所述第一节点进行复位；
    在一图像帧的数据写入阶段：向第一扫描端输入所述第一扫描信号，向第二扫描端输入第二扫描信号，并向数据端输入数据信号，以使所述写入子电路将所述数据端接收的数据信号写入至所述第一节点，对所述驱动晶体管进行阈值电压补偿；
    在一图像帧的发光阶段：向第一使能信号端输入第一使能信号，并向第二使能信号端输入第二使能信号，以使所述发光控制子电路将第一电压端的电压信号传输至第二节点，并将所述驱动晶体管输出的电流传输至所述发光器件，使所述发光器件发光。
  21. 根据权利要求20所述的驱动方法，还包括：
    在一图像帧的初始化阶段，向所述数据端输入所述数据信号。
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