WO2020056685A1

WO2020056685A1 - Transmission gate circuit, matrix switch and electronic device

Info

Publication number: WO2020056685A1
Application number: PCT/CN2018/106770
Authority: WO
Inventors: 邹小卫; 鲁海生; 李赞
Original assignee: 华为技术有限公司
Priority date: 2018-09-20
Filing date: 2018-09-20
Publication date: 2020-03-26
Also published as: CN112689959B; CN112689959A; CN117220662A

Abstract

A transmission gate circuit, a matrix switch, and an electronic device. The transmission gate circuit comprises a first transmission gate and a second transmission gate. An input end of the first transmission gate is used to transmit an input signal or an output signal of a load circuit connected to the first transmission gate, a control end of the first transmission gate is used to input a first control signal, and an output end of the first transmission gate is also connected to an output end of the second transmission gate; and an input end of the second transmission gate is used to input an electric leakage adjustment signal, and a control end of the second transmission gate is used to input a second control signal. When the first transmission gate is in a turned-on state under the control of the first control signal, the second transmission gate is in a turned-off state under the control of the second control signal, and when the first transmission gate is in a turned-off state under the control of the first control signal, the second transmission gate is in a turned-on state under the control of the second control signal; and the electric leakage adjustment signal is used to reduce a leakage current of the first transmission gate when the first transmission gate is turned off and the second transmission gate is turned on.

Description

Transmission gate circuit, matrix switch and electronic equipment

Technical field

The present application relates to the field of electronic communication technology, and particularly to the field of semiconductor technology.

Background technique

Transmission gate (TG) is a controllable switch circuit that can transmit both digital and analog signals. It is one of the most common structures in integrated circuit devices. It is used to control the connection between the input signal and the load circuit. The path is turned on or off.

Because the transmission gate is a semiconductor device, there is still a certain leakage current flowing through the path where the transmission gate is located when the transmission gate is in the off state. The path where the transmission gate is located and other paths connected to the path where the transmission gate is located are connected. The path affects, especially for large-scale programming circuits. The input signals on the bus are connected to the corresponding load circuit through multiple transmission gates. The user-defined addressing signal can be used to connect the bus to only one load circuit at a time. The load circuit remains disconnected. As shown in Figure 1, when transmission gate TG _{0 is} turned on and other transmission gates TG ₁ to TG _{n are} turned off, the leakage currents I _leak1 to I _leakn in the turned-off transmission gates are all Superimposed on the path where the conductive transmission gate is located, it affects the signal I _total in the path where the conductive transmission gate is located.

The traditional transmission gate design reduces the leakage current when the transmission gate is turned off by reducing the size of the transmission gate. However, the smaller the size of the transmission gate, the smaller the driving capability of the transmission gate when it is in the conducting state. Therefore, the design of such a transmission gate is not suitable for switching circuit applications that have certain requirements for the driving capability.

Summary of the Invention

The application provides a transmission gate circuit, a matrix switch, and an electronic device to reduce leakage current of the transmission gate.

In a first aspect, the present application provides a transmission gate circuit, the transmission gate circuit including a first transmission gate and a second transmission gate, wherein an input terminal of the first transmission gate is used to transmit an input signal of a load circuit or An output signal, the load circuit is connected to the output end of the first transmission gate, the control end of the first transmission gate is used to input a first control signal, and the output end of the first transmission gate is also connected to the first transmission gate The output ends of the two transmission gates are connected; the input end of the second transmission gate is used to input a leakage adjustment signal, and the control end of the second transmission gate is used to input a second control signal.

When the first transmission gate is in an on state under the control of the first control signal, the second transmission gate is in an off state under the control of the second control signal. When the gate is in the off state under the control of the first control signal, the second transmission gate is in the on state under the control of the second control signal; the leakage adjustment signal is used for the first When the transmission gate is in the off state and the second transmission gate is in the on state, the leakage current of the first transmission gate is reduced.

With the above solution, when the first transmission gate in the transmission gate circuit is in an on state under the control of the first control signal, the second transmission gate in the transmission gate circuit is under the control of the second control signal In the off state, the input signal input to the first transmission gate is transmitted to the load circuit of the first stage of the first transmission gate, that is, the second transmission gate has no effect on the load circuit of the path where the first transmission gate is located. Effect; when the first transmission gate is in an off state under the control of the first control signal, the second transmission gate is in an on state under the control of the second control signal, and the first transmission gate is input The leakage adjustment signals of the two transmission gates can pass through the second transmission gate and adjust the voltage of the output end of the first transmission gate to reduce the leakage current generated when the first transmission gate is in the off state, and it is not necessary Limiting the size of the first transmission gate will not affect the driving capability of the first transmission gate and ensure that the first transmission gate has a larger driving capability.

In addition, the leakage adjustment signal can be flexibly configured according to the opening voltage of the first transmission gate to adjust the clamping voltage transmitted by the second transmission gate, which can achieve the results obtained by the advanced processing technology with large fluctuations in processing technology. Transmission gate performance fluctuation immunity is that the leakage adjustment function of the second transmission gate can adapt to transmission gate performance fluctuations.

In a possible implementation manner, a size of the second transmission gate is smaller than a size of the first transmission gate, and a size of the first transmission gate is determined according to a driving capability of the transmission gate circuit.

In a possible implementation manner, the transmission gate circuit may be specifically implemented by, but not limited to, any one of the following five methods:

Manner 1: The first transmission gate is a first complementary metal oxide semiconductor CMOS transmission gate, and the second transmission gate is a second CMOS transmission gate. The control terminal of the first CMOS transmission gate includes a first control terminal and a second control terminal. The first control terminal is used to input a first sub-control signal, and the second control terminal is used to input a second sub-control signal. Control signal; the control end of the second CMOS transmission gate includes a third control end and a fourth control end, the third control end is used to input a third sub-control signal, and the fourth control end is used to input a fourth Sub control signal

The first control signal includes the first sub-control signal and the second sub-control signal, and the second control signal includes the third sub-control signal and the fourth sub-control signal; the second The sub-control signal is an inverted signal of the first sub-control signal, the third sub-control signal is an inverted signal of the first sub-control signal, and the fourth sub-control signal is the second sub-control The inverted signal of the signal.

Manner 2: The first transmission gate is a first P-channel metal-oxide-semiconductor PMOS transmission gate, the second transmission gate is a second PMOS transmission gate, and the second control signal is a signal of the first control signal. Inverted signal.

Manner 3: The first transmission gate is a first N-channel metal oxide semiconductor NMOS transmission gate, the second transmission gate is a second NMOS transmission gate, and the second control signal is a signal of the first control signal. Inverted signal.

Manner 4: The first transmission gate is a P-channel metal-oxide-semiconductor PMOS transmission gate, and the second transmission gate is an N-channel metal-oxide-semiconductor NMOS transmission gate; the second control signal and the first The control signals are the same.

Manner 5: The first transmission gate is an N-channel metal oxide semiconductor NMOS transmission gate, and the second transmission gate is a P-channel metal oxide semiconductor PMOS transmission gate; the second control signal and the first The control signals are the same.

It should be noted that when the first transmission gate or the second transmission gate is a PMOS transmission gate, the first transmission gate or the second transmission gate may include one or more PMOS transistors. When the first transmission gate or the second transmission gate is an NMOS transmission gate, the first transmission gate or the second transmission gate may include one or more NMOS transistors.

In a second aspect, an embodiment of the present application further provides a matrix switch. The matrix switch includes multiple switches, and the multiple switches are transmission gate circuits according to any one of the possible implementation manners of the first aspect. The plurality of switches constitute a switch array, and for any one of the switches in the switch array, the input end of the switch is connected to the input end of each switch in the row where the switch is located, and the output end where the switch is located is connected to the switch where The output terminal of each switch in the column is connected, and the control terminal of the switch is used to input the first control signal and the second control signal.

According to a third aspect, an embodiment of the present application further provides an electronic device, where the electronic device includes the matrix switch and the controller according to any one of the possible implementation manners of the second aspect, where the controller is configured to generate The first control signal and the second control signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic structural diagram of a matrix switch in the prior art; FIG.

FIG. 2 is a schematic structural diagram of an NMOS transistor; FIG.

3 is a schematic structural diagram of a transmission gate circuit according to an embodiment of the present application;

4 is a schematic diagram of a specific structure of a transmission gate circuit according to an embodiment of the present application;

5 is a second schematic diagram of a specific structure of a transmission gate circuit according to an embodiment of the present application;

FIG. 6 is a third specific schematic structural diagram of a transmission gate circuit according to an embodiment of the present application; FIG.

FIG. 7 is a fourth specific structural schematic diagram of a transmission gate circuit according to an embodiment of the present application;

FIG. 8 is a fifth specific structural schematic diagram of a transmission gate circuit according to an embodiment of the present application; FIG.

9 is a schematic structural diagram of a matrix switch according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a specific structure of a matrix switch according to an embodiment of the present application; FIG.

FIG. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

detailed description

Transmission gates are widely used in various integrated circuits to achieve the functions of switches, multiplexers, and logic functional devices, such as programmable logic devices. The transmission gate can be composed of semiconductor devices such as bipolar transistors (BJT) or metal-oxide semiconductor (MOS) transistors, and an NMOS transmission gate composed of a single N (negative) channel MOS transistor is Example, its structure is shown in Figure 2. The NMOS transmission gate includes a P-type semiconductor silicon substrate with a lower doping concentration, and two N-regions with a higher doping concentration formed on the P-type semiconductor substrate by a semiconductor photolithography and diffusion process. The electrodes on the two N regions are the source (source, S) and the drain (drain, D), and the electrode on the P-type semiconductor between the source and the drain is the gate (gate, G).

When a forward voltage V _GS is applied between the gate and the source of the NMOS transmission gate, an electric field is generated in the silicon dioxide SiO2 insulating layer between the gate and the silicon substrate and the gate points toward the P-type silicon substrate. The holes in the P-type substrate near the gate are repelled, leaving immovable acceptor ions (negative ions) to form a depletion layer, and the electrons (majority) in the P-type substrate are attracted to the substrate surface. . When V _{GS is} small, the electric field is not capable of attracting electrons, and a conductive channel cannot be formed between the drain and the source. As V _GS increases, more electrons are attracted to the surface layer of the P substrate. When V _GS When the turn-on voltage value V _TH of the NMOS transmission gate is reached, an N-type conductive channel is formed from the drain to the source, and its conductivity type is opposite to that of the P substrate, so it is also called an inversion layer. After the conductive channel is formed, the NMOS transmission gate is in a conducting state, and a forward voltage V _DS is applied between the drain and the source, and a current is generated between the drain and the source.

Ideally, when V _GS <V _TH , the NMOS transmission gate is in an off state, and no current flows between the drain and the source, but between the drain and the substrate of the NMOS transmission gate, the source There are two PN junctions between the electrode and the substrate. Even if there is no conductive channel in the NMOS transmission gate, there is still a reverse saturation current between the drain and the source, which is the so-called leakage current.

The leakage current will not only increase the power consumption of the transmission gate, but also affect the signals of other paths connected to the path where the transmission gate is located. The traditional transmission gate design reduces the leakage current when the transmission gate is turned off by reducing the size of the transmission gate. However, the smaller the size of the transmission gate, the smaller the driving capability of the transmission gate when it is in the on state.

In order to solve the above problems, the present application proposes a transmission gate circuit, a matrix switch, and an electronic device, so as to reduce the leakage current of the transmission gate when it is turned off without reducing the driving capability of the transmission gate.

In addition, it should be understood that in the description of the present application, "multiple" means two or more; words such as "first" and "second" are used only for the purpose of distinguishing descriptions, and cannot be understood as The relative importance of indication or implication cannot be understood as the order of indication or implication.

In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings.

The present application provides a transmission gate circuit that adjusts the leakage current when the transmission gate is turned off by adding a transmission gate for adjusting the leakage current to control the on or off of the path between the input signal and the load circuit. As shown in FIG. 3, the transmission gate circuit 300 includes a first transmission gate 310 and a second transmission gate 320, wherein an input terminal of the first transmission gate 310 is used to transmit an input signal or an output signal of a load circuit, The load circuit is connected to an output terminal of the first transmission gate 310, a control terminal of the first transmission gate 310 is used to input a first control signal, and an output terminal of the first transmission gate 310 is also connected to the first transmission gate 310. The output ends of the two transmission gates 320 are connected; the input end of the second transmission gate 320 is used to input a leakage adjustment signal, and the control end of the second transmission gate 320 is used to input a second control signal.

When the first transmission gate 310 is in an on state under the control of the first control signal, the second transmission gate 320 is in an off state under the control of the second control signal. When a transmission gate 310 is in an off state under the control of the first control signal, the second transmission gate 320 is in an on state under the control of the second control signal; the leakage adjustment signal is used for When the first transmission gate 310 is in the off state and the second transmission gate 320 is in the on state, the leakage current of the first transmission gate 310 is reduced.

The leakage adjustment signal can be flexibly configured according to an opening voltage of the first transmission gate 310, so that the second transmission gate 320 changes the first transmission gate 310 when the first transmission gate 310 is turned off. The voltage at the output terminal of the MOSFET is further reduced to reduce the leakage current when the first transmission gate 310 is turned off.

Since the input signal is transmitted to the load circuit through the first transmission gate 310, rather than to the load circuit through the second transmission gate 320, the driving capability of the transmission gate circuit 300 is mainly It depends on the driving capability of the first transmission gate 310. The driving capability of the transmission gate is determined by the size of the transmission gate. The larger the size of the transmission gate, the greater the driving capability of the transmission gate. That is, the size of the first transmission gate 310 is determined by the size of the first transmission gate 310. The driving capability is determined. The size of the second transmission gate 320 may be smaller than the size of the first transmission gate 310, and the size of the transmission gate circuit 300 may be reduced.

Among them, the size of the transmission gate is generally characterized by the width W of the conductive channel of the transmission gate and the length L of the control end of the transmission gate (for example, when the transmission gate is a PMOS transistor, L is the length of the gate of the PMOS transistor), which can be expressed as

Means. That is, the size of the first transmission gate 310 may be the ratio of the width W ₁ of the conductive channel of the first transmission gate 310 to the length L ₁ of the control end of the first transmission gate 310.

It is indicated that the size of the second transmission gate 320 may be the ratio of the width W ₂ of the conductive channel of the second transmission gate 320 to the length L ₂ of the control end of the second transmission gate 320.

Means.

In implementation, the transmission gates can be realized by MOS transistors, including PMOS transmission gates, NMOS transmission gates, and complementary metal oxide semiconductor (CMOS) transmission gates. At this time, the transmission gate circuit 300 may be specifically implemented in any one of the following five ways:

Method A. The first transmission gate 310 is a first CMOS transmission gate, and the second transmission gate 320 is a second CMOS transmission gate, as shown in FIG. 4. The control terminal of the first CMOS transmission gate includes a first control terminal and a second control terminal. The first control terminal is used to input a first sub-control signal, and the second control terminal is used to input a second sub-control signal. Control signal; the control end of the second CMOS transmission gate includes a third control end and a fourth control end, the third control end is used to input a third sub-control signal, and the fourth control end is used to input a fourth A sub-control signal; the first control signal includes the first sub-control signal and the second sub-control signal, and the second control signal includes the third sub-control signal and the fourth sub-control signal.

The second sub-control signal is an inverted signal of the first sub-control signal, the third sub-control signal is an inverted signal of the first sub-control signal, and the fourth sub-control signal is the An inverted signal of a second sub-control signal, so that when the first CMOS transmission gate is in a conducting state under the control of the first sub-control signal and the second sub-control signal, the second CMOS transmission gate The gate is in an off state under the control of the third sub-control signal and the fourth sub-control signal. The first CMOS transmission gate is controlled by the first sub-control signal and the second sub-control signal. When it is in the off state, the second CMOS transmission gate is in the on state under the control of the third sub-control signal and the fourth sub-control signal.

When the first CMOS transmission gate 310 and the second CMOS transmission gate 320 are each composed of a PMOS transistor and an NMOS transistor, the first control terminal is a PMOS transistor in the first CMOS transmission gate 310. Gate, the second control terminal is the gate of the NMOS transistor in the first CMOS transmission gate 310, and the third control terminal is the gate of the PMOS transistor in the second CMOS transmission gate 320, so The fourth control terminal is a gate of an NMOS transistor in the second CMOS transmission gate 320.

Since the structure of the MOS transistor is symmetrical, the input terminal of the first CMOS transmission gate 310 may be the source of the PMOS transistor and the NMOS transistor in the first CMOS transmission gate 310, or the first CMOS transmission. PMOS transistor in gate 310 and drain of NMOS transistor. When an input terminal of the first CMOS transmission gate 310 is a drain of a PMOS transistor and an NMOS transistor in the first CMOS transmission gate 310, an output terminal of the first CMOS transmission gate 310 is the first CMOS The source of the PMOS transistor and the NMOS transistor in the transmission gate 310. When the input terminal of the first CMOS transmission gate 310 is the source of the PMOS transistor and the NMOS transistor in the first CMOS transmission gate, the first An output terminal of the CMOS transmission gate 310 is a drain of a PMOS transistor and an NMOS transistor in the first CMOS transmission gate 310.

Method B. The first transmission gate 310 is a first PMOS transmission gate, and the second transmission gate 320 is a second PMOS transmission gate, as shown in FIG. 5, wherein the second control signal is the first transmission gate. An inverted signal of a control signal, so that when the first PMOS transmission gate is in an on state under the control of the first control signal, the second PMOS transmission gate is in a state under the control of the second control signal When the first PMOS transmission gate is in the off state under the control of the first control signal, the second PMOS transmission gate is in the on state under the control of the second control signal.

It should be noted that the first PMOS transmission gate may include one or more PMOS transistors, and the second PMOS transmission gate may include one or more PMOS transistors. In FIG. 5, only the first PMOS transmission is used. The gate includes a PMOS transistor, and the second PMOS transmission gate includes a PMOS transistor as an example, which does not limit the embodiment of the present application.

When the first PMOS transmission gate includes a PMOS transistor, a control terminal of the first PMOS transmission gate is a gate of the PMOS transistor, and an input terminal of the first PMOS transmission gate is a drain of the PMOS transistor. An output terminal of the first PMOS transmission gate is a gate of the PMOS transistor, or a control terminal of the first PMOS transmission gate is a gate of the PMOS transistor, and an input terminal of the first PMOS transmission gate is The gate of the PMOS transistor, and the output of the first PMOS transmission gate is the drain of the PMOS transistor. When the second PMOS transmission gate includes a PMOS transistor, the input terminal, the control terminal, and the output terminal of the second PMOS transmission gate are similar to the first PMOS transmission gate. See above for the first PMOS transistor. The related description is not repeated here.

Method C. The first transmission gate 310 is a first NMOS transmission gate, and the second transmission gate 320 is a second NMOS transmission gate, as shown in FIG. 6, wherein the second control signal is the first An inverted signal of a control signal, so that when the first NMOS transmission gate is in an on state under the control of the first control signal, the second NMOS transmission gate is in a state under the control of the second control signal When the first NMOS transmission gate is in the off state under the control of the first control signal, the second NMOS transmission gate is in the on state under the control of the second control signal.

The first NMOS transmission gate may include one or more NMOS transistors, and the second NMOS transmission gate may include one or more NMOS transistors. In FIG. 5, only the first NMOS transmission gate is included. An NMOS transistor, and the second NMOS transmission gate includes an NMOS transistor as an example, which does not limit the embodiment of the present application.

When the first NMOS transmission gate includes an NMOS transistor, a control terminal of the first NMOS transmission gate is a gate of the NMOS transistor, and an input terminal of the first NMOS transmission gate is a drain of the NMOS transistor. The output terminal of the first NMOS transmission gate is the gate of the NMOS transistor, or the control terminal of the first NMOS transmission gate is the gate of the NMOS transistor, and the input terminal of the first NMOS transmission gate is the The gate of the NMOS transistor, and the output of the first NMOS transmission gate is the drain of the NMOS transistor. When the second NMOS transmission gate includes an NMOS transistor, the input terminal, the control terminal, and the output terminal of the second NMOS transmission gate are similar to the first NMOS transmission gate. See above for the first NMOS transistor. The related description is not repeated here.

Method D. The first transmission gate 310 is a PMOS transmission gate, and the second transmission gate 320 is an NMOS transmission gate. As shown in FIG. 7, the second control signal is the same as the first control signal. When the PMOS transmission gate is in the on state under the control of the first control signal, the NMOS transmission gate is in the off state under the control of the second control signal, and the PMOS transmission gate is in all states. When the first control signal is in the off state, the NMOS transmission gate is in the on state under the control of the second control signal.

Method E. The first transmission gate 310 is an NMOS transmission gate, and the second transmission gate 320 is a PMOS transmission gate, as shown in FIG. 8, wherein the second control signal is the same as the first control signal. When the NMOS transmission gate is in an on state under the control of the first control signal, the PMOS transmission gate is in an off state under the control of the second control signal, and the NMOS transmission gate is in When the first control signal is in the off state, the PMOS transmission gate is in the on state under the control of the second control signal.

It should be understood that the PMOS transmission gate may include one or more PMOS transistors, and the NMOS transmission gate may include one or more NMOS transistors. In FIG. 7 and FIG. 8, only the PMOS transmission gate is included. A PMOS transistor, and the NMOS transmission gate includes an NMOS transistor as an example, which does not limit the embodiment of the present application.

Specifically, when the PMOS transmission gate includes a PMOS transistor, the control end of the PMOS transmission gate is the gate of the PMOS transistor, and the input end of the PMOS transmission gate is the drain of the PMOS transistor. The output terminal of the PMOS transmission gate is the gate of the PMOS transistor, or the control terminal of the PMOS transmission gate is the gate of the PMOS transistor, and the input terminal of the PMOS transmission gate is the gate of the PMOS transistor. The output of the PMOS transmission gate is the drain of the PMOS transistor. When the NMOS transmission gate includes an NMOS transistor, a control terminal of the NMOS transmission gate is a gate of the NMOS transistor, an input terminal of the NMOS transmission gate is a drain of the NMOS transistor, and the first NMOS The output end of the transmission gate is the gate of the NMOS transistor, or the control end of the NMOS transmission gate is the gate of the NMOS transistor, the input end of the NMOS transmission gate is the gate of the NMOS transistor, and the NMOS The output of the transmission gate is the drain of the NMOS transistor.

It should be noted that the first transmission gate 310 and the second transmission gate 320 may also be implemented by a bipolar transistor (ie, a triode), where the emitter (E) and the base of the bipolar transistor The (base, B) and the collector (C) correspond to the source, gate, and drain of the MOS transistor, respectively. Their functions are similar. The collector is usually used as the input, and the emitter is usually used as the output. When the first transmission gate 310 and the second transmission gate 320 are implemented by a bipolar transistor, the specific implementation manner of the transmission gate circuit 300 is similar to the foregoing manners A to E, and is not repeated here.

According to the above solution, when the first transmission gate 310 in the transmission gate circuit 300 is in an on state under the control of the first control signal, the second transmission gate 320 in the transmission gate circuit 300 is in the second control It is in the off state under the control of the signal, and the input signal input to the first transmission gate 310 is transmitted to the subsequent-stage load circuit of the first transmission gate 310, that is, the second transmission gate 320 controls the first transmission gate. The load circuit of the path where 310 is located has no effect; when the first transmission gate 310 is in the off state under the control of the first control signal, the second transmission gate 320 is under the control of the second control signal It is in a conducting state, and the leakage adjustment signal input to the second transmission gate 320 can pass through the second transmission gate 320 and adjust the voltage at the output terminal of the first transmission gate 310 to reduce the first transmission gate. The leakage current generated when the 310 is in the off state does not need to limit the size of the first transmission gate 310, and thus does not affect the driving ability of the first transmission gate 310, ensuring that the first transmission gate 310 has a large Driving capacity.

In addition, the leakage adjustment signal can be flexibly configured according to the opening voltage of the first transmission gate 310 to adjust the clamping voltage transmitted by the second transmission gate 320, which can realize an advanced processing process with large fluctuations in processing technology The obtained transmission gate performance fluctuation immunity is that the leakage adjustment function of the second transmission gate 320 can adapt to the transmission gate performance fluctuation.

Based on the above embodiment, this application further provides a matrix switch. As shown in FIG. 9, the matrix switch 900 includes multiple switches, and the multiple switches are transmissions described in any one of the foregoing possible implementation manners. Gate circuit 300. The plurality of switches constitute a switch array. For any one of the switches in the switch array, the input terminal of the switch is connected to the input terminal of each switch in the row where the switch is located, and the output terminal of the switch is connected to the switch. An output terminal of each switch in the column is connected, and a control terminal of the switch is used to input the first control signal and the second control signal.

The control signal (including the first control signal and the second control signal) and the leakage current adjustment signal of each of the switches may be generated by the same circuit (or device), or may be generated by different circuits ( Or device).

For example, when the matrix switch 900 is an n × 1 switch array, its specific structure is shown in FIG. 10. It should be noted that this is only an example and does not limit the embodiments of the present application. The matrix switch 900 may also be an n × m switch array, where n and m are positive integers.

Through the above solution, each switch in the matrix switch 900 is implemented by the transmission gate circuit 300, which can effectively reduce the total of the matrix switch 900 while ensuring that the matrix switch 900 has a large driving capability. Leakage current.

Based on the above embodiments, this application further provides an electronic device. As shown in FIG. 11, the electronic device 1100 includes the matrix switch 900 and the controller 1110 described in any one of the foregoing possible implementation manners. The controller 1110 is configured to generate the first control signal and the second control signal.

It should be noted that the embodiment of the present application does not limit the manner of generating the leakage adjustment signal. The leakage adjustment signal may be generated by an external signal generating device or a signal generating circuit in the electronic device 1110. Or generated by the controller 1110.

Through the above solution, the matrix switch 900 in the electronic device 1100 has a large driving capability, and the total leakage current of the matrix switch 900 is small, so that when one of the switches in the matrix switch 900 is gated, the The leakage current generated by other switches in the off state of the matrix switch has less influence on the signal on the path where the switch is located. For example, for an electronic device 1110 applied to a multi-channel gating measurement scenario, when the electronic device 1110 measures a load circuit connected to one of the switches of the matrix switch 900, the other switches in the matrix switch 900 are in the off state. The leakage current generated by the switch in the off state has less influence on the signal on the path where the switch is located, so the measurement accuracy of the electronic device can be effectively improved.

Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. In this way, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these changes and variations.

Claims

A transmission gate circuit, comprising: a first transmission gate and a second transmission gate;

The input end of the first transmission gate is used to transmit an input signal or an output signal of a load circuit, the load circuit is connected to the output end of the first transmission gate, and the control end of the first transmission gate is used to A first control signal is input, and an output end of the first transmission gate is also connected to an output end of the second transmission gate; an input end of the second transmission gate is used to input a leakage adjustment signal, and the second transmission gate A control terminal for inputting a second control signal;

When the first transmission gate is in an on state under the control of the first control signal, the second transmission gate is in an off state under the control of the second control signal. When the gate is in an off state under the control of the first control signal, the second transmission gate is in an on state under the control of the second control signal;

The leakage adjustment signal is used to reduce a leakage current of the first transmission gate when the first transmission gate is in an off state and the second transmission gate is in an on state.
The transmission gate circuit according to claim 1, wherein a size of the second transmission gate is smaller than a size of the first transmission gate.
The transmission gate circuit according to claim 1 or 2, wherein the first transmission gate is a first complementary metal oxide semiconductor CMOS transmission gate, and the second transmission gate is a second CMOS transmission gate;

The control terminal of the first CMOS transmission gate includes a first control terminal and a second control terminal. The first control terminal is used to input a first sub-control signal, and the second control terminal is used to input a second sub-control signal. The control end of the second CMOS transmission gate includes a third control end and a fourth control end, the third control end is used to input a third sub-control signal, and the fourth control end is used to input a fourth sub-control signal;

The first control signal includes the first sub-control signal and the second sub-control signal, and the second control signal includes the third sub-control signal and the fourth sub-control signal; the second The sub-control signal is an inverted signal of the first sub-control signal, the third sub-control signal is an inverted signal of the first sub-control signal, and the fourth sub-control signal is the second sub-control The inverted signal of the signal.
The transmission gate circuit according to claim 1 or 2, wherein the first transmission gate is a first P-channel metal oxide semiconductor PMOS transmission gate, and the second transmission gate is a second PMOS transmission gate; The second control signal is an inverted signal of the first control signal.
The transmission gate circuit according to claim 1, wherein the first transmission gate is a first N-channel metal oxide semiconductor NMOS transmission gate, and the second transmission gate is a second NMOS transmission gate; The second control signal is an inverted signal of the first control signal.
The transmission gate circuit according to claim 1 or 2, wherein the first transmission gate is a P-channel metal oxide semiconductor (PMOS) transmission gate, and the second transmission gate is an N-channel metal oxide semiconductor (NMOS). Transmission gate; the second control signal is the same as the first control signal.
The transmission gate circuit according to claim 1 or 2, wherein the first transmission gate is an N-channel metal oxide semiconductor NMOS transmission gate, and the second transmission gate is a P-channel metal oxide semiconductor PMOS Transmission gate; the second control signal is the same as the first control signal.
A matrix switch, comprising a plurality of switches, wherein the plurality of switches are transmission gate circuits according to any one of claims 1-7;

The plurality of switches constitute a switch array. For any one of the switches in the switch array, the input terminal of the switch is connected to the input terminal of each switch in the row where the switch is located, and the output terminal of the switch is connected to the switch. An output terminal of each switch in the column is connected, and a control terminal of the switch is used to input the first control signal and the second control signal.
An electronic device, comprising the matrix switch and the controller according to claim 8, wherein the controller is configured to generate the first control signal and the second control signal.