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WO2020052292A1 - 基于工业互联网的集成电路测试信息化管理系统 - Google Patents

基于工业互联网的集成电路测试信息化管理系统 Download PDF

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Publication number
WO2020052292A1
WO2020052292A1 PCT/CN2019/090313 CN2019090313W WO2020052292A1 WO 2020052292 A1 WO2020052292 A1 WO 2020052292A1 CN 2019090313 W CN2019090313 W CN 2019090313W WO 2020052292 A1 WO2020052292 A1 WO 2020052292A1
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WIPO (PCT)
Prior art keywords
test
data
integrated circuit
analysis
wafer
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PCT/CN2019/090313
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English (en)
French (fr)
Inventor
罗斌
祁建华
凌俭波
刘惠巍
汤雪飞
季海英
Original Assignee
上海华岭集成电路技术股份有限公司
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Application filed by 上海华岭集成电路技术股份有限公司 filed Critical 上海华岭集成电路技术股份有限公司
Priority to GB1910775.4A priority Critical patent/GB2581861B/en
Priority to US16/521,926 priority patent/US11042680B2/en
Publication of WO2020052292A1 publication Critical patent/WO2020052292A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
    • G06F16/25—Integrating or interfacing systems involving database management systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
    • G06F16/27—Replication, distribution or synchronisation of data between databases or within a distributed database system; Distributed database system architectures therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/30—Computing systems specially adapted for manufacturing

Definitions

  • the invention relates to the technical field of integrated circuit testing, in particular to an information management method for integrated circuit testing, an information management system for integrated circuit testing, and a machine-readable storage medium.
  • the technical problem mainly solved by the present invention is to provide an information management method for integrated circuit testing, an information management system for integrated circuit testing, and a machine-readable storage medium, which can provide technology for the value reflection of test data generated during integrated circuit testing. stand by.
  • a technical solution adopted by the present invention is to provide an information management method for integrated circuit testing.
  • the method includes: providing test data generated by an integrated circuit test platform for integrated circuit testing, and the integrated circuit.
  • the test platform is an integrated circuit test platform of more than one level, and each level of the integrated circuit test platform includes a plurality of test instruments; provides resource data related to the integrated circuit test except the test data; according to the integration
  • the test data and the resource data of the circuit test analyze the integrated circuit test to obtain result data related to the integrated circuit test.
  • the integrated circuit test includes at least one of a design verification stage test and a production link test;
  • the design verification stage test includes a wafer test;
  • the production link test includes a wafer manufacturing process process At least one of testing, wafer testing, and finished product testing.
  • the test data generated by the integrated circuit test platform for integrated circuit testing includes: obtaining original test data of different formats generated by the integrated circuit test platform for the integrated circuit test; and converting the original test data into Conversion test data in a uniform format.
  • the integrated circuit test is a wafer test, and the test data is generated by a plurality of different types of test machines.
  • the test data includes test data for each wafer, and the resource data includes each wafer.
  • Test record data the test record data of each wafer corresponds to the test data of each wafer; wherein the resource data also includes basic information data of each wafer, and each of the wafers The basic information data corresponds to the test data of each of the wafers; wherein the resource data also includes the state record data of the test probe station during each wafer test, and the state record data of the probe station Corresponds to the test data of each wafer; wherein the result data includes the yield of each wafer of the test product, the daily yield fluctuations, and the change trend of key parameters; the method further includes: The result data is automatically pushed to the relevant person; wherein the result data is automatically pushed to the relevant person via email or WeChat.
  • the providing resource data related to the integrated circuit test and other than the test data includes: establishing, managing, and updating the test flow of the integrated circuit test in real time; registering and managing the integrated circuit test Information of test products; registration and management of test information of the integrated circuit test; monitoring and management of task status of the integrated circuit test; monitoring and management of test information of the production link; test UID of the test product and the server The UID is verified, and the verification result and the test version number are recorded in real time; the wafer map related information of the test product tested by the integrated circuit is modified, added, and deleted; wherein the integrated circuit test is a production link Test; the integrated circuit test is a wafer test or a finished product test in the production process.
  • the analysis includes test parameter index analysis, test yield analysis, test time analysis, wafer map information analysis, test summary inspection and analysis, probe pin height analysis, result data feedback requirement analysis, and test record historical information. At least one of analysis; wherein the analyzing the integrated circuit test according to the test data and the resource data of the integrated circuit test to obtain result data related to the integrated circuit test includes: Receiving inputted first related information for querying resource data, the first related information including a test product name, a test instrument, a test lot number, and a test machine number; receiving inputted second related information for querying resource data, The second related information includes a start time and an end time; third input information used for querying resource data is received, and the third related information is wafer test or finished product test; and input input is used for querying resource data
  • the fourth related information, the third related information is data or local data of a query database ; Based on the first information, second information, third information and fourth information, read the relevant data file data and real-time display of progress and the read parameter information;
  • the result data is presented in at least one form of a file, a report, and a chart;
  • the method further includes:
  • the result data is displayed on a visual interface in at least one of a file, a report form, and a chart; wherein the result data corresponding to the test parameter index analysis includes each die on the wafer.
  • the station corresponding to the X coordinate, Y coordinate, and XY coordinate on the wafer, the pass or fail result of the XY coordinate, the pass or fail result of the test item, and the specific test value of the test item; wherein, the The corresponding result data of the test parameter index analysis is after excluding the value that the wafer fails, the value that the test item fails, the value of the interquartile range greater than 1.5 times the test value, and the value of the interquartile range greater than 3 times the test value.
  • the result data corresponding to the test parameter index analysis is presented in the form of a first chart; wherein the first chart includes: a normal distribution chart, a scatter chart, and a bar Histogram, box plot, and map of test items; wherein the marker types of the first chart include: upper limit, lower limit, maximum value, minimum value, average value, median value, standard deviation, average value plus 3 Times standard deviation, average minus 3 times standard deviation, first quartile, third quartile; where numerical analysis is to perform numerical average and standard deviation analysis of values; wherein, the test yield analysis
  • the corresponding result data includes: final yield, initial yield, retest rate, response rate, final pass, initial pass, retest number, reply number, test machine number, and pin card number;
  • the result data corresponding to the rate analysis is presented in the form of a second chart, wherein the second chart includes: a rectification batch yield analysis chart, a probe card yield analysis chart, a station yield analysis linear chart, and a failure serial number analysis chart.
  • a single station failure analysis chart and multiple station linear charts refers to displaying the values of different batches of test products in different colors for analysis of yield difference between test product batches ;
  • the probe card yield analysis diagram refers to forming different test conditions into a test yield analysis diagram for analyzing the yield difference between different hardware;
  • the workstation yield analysis linear diagram refers to different workstations.
  • the failure sequence analysis chart refers to the order of all the failure sequence numbers from large to small, and the sequence numbers of each test result and the sequence numbers of all previous test results Accumulate the number, and make a cumulative percentage line for analysis of which test result serial numbers are the main failures and how much impact;
  • the single station failure analysis chart refers to the highest number of three failure serial numbers to do An overlay histogram is used to analyze the yield difference of the workstation through the height of each workstation;
  • the multiple workstation linear diagram refers to taking the highest number of three failure serial numbers to make a linear diagram for analysis of whether the workstation is different The number of failures caused is increased; wherein, the result data corresponding to the test time analysis includes: total test time, normal test time, retest test time, and normal test process.
  • the analysis of the wafer map information includes: the distribution of the serial numbers of all test results, the distribution of the serial numbers of retests and response test results, and the analysis by multiple analysis algorithms. If the map is abnormal, multiple maps can be superimposed to analyze the distribution of the failure serial number.
  • the result data corresponding to the wafer map information analysis includes: the number of test result serial numbers, the percentage of the test result serial numbers, and the workstation. The number of differences, the percentage of station differences, and specific station information; wherein the result data corresponding to the wafer Map information analysis is distinguished by colors
  • the form of repeat / retest is presented.
  • the color distinguished reply / retest can analyze the level of the response rate, determine whether there are obvious pattern graphics for analyzing hardware differences, and guide subsequent tests and improve yield.
  • the integrated circuit test is a test in the production process; the integrated circuit test is a wafer test or a finished product test in the production process.
  • the method further includes: performing remote real-time monitoring of the integrated circuit test based on visualization technology; and performing the remote real-time monitoring of the integrated circuit test based on visualization technology includes: Real-time remote monitoring of the test probe station and testing machine during the test; remote real-time monitoring of data acquisition, data processing, data analysis, and data storage in the integrated circuit test based on visualization technology; the integration based on visualization technology The entire process of circuit testing is monitored and managed remotely in real time; the method further comprises: when an abnormality occurs in the test workshop, an alarm signal is issued; in response to the alarm signal, the abnormality is processed on a visual interface;
  • the remote real-time monitoring of the test probe station based on the visualization technology includes: recording and displaying the number of continuous defective products; if the number of recorded continuous defective products is greater than the misjudgment threshold input, sending a stop to the automated test probe station Test instructions while sending alarms The instruction indicates the alarm; wherein the integrated circuit test is a test in the production link; the integrated circuit test is a wafer test or a finished product test
  • an information management system for integrated circuit testing includes: a processor, a memory, and a communication circuit, and the processor is respectively coupled to the processor.
  • a memory and the communication circuit, and the system is connected to an integrated circuit test platform through the communication circuit to collect test data generated by the integrated circuit test platform for integrated circuit testing, wherein the processor, the memory, and When the communication circuit is in operation, the steps in the method according to any one of the foregoing can be implemented.
  • the system includes a device interconnection and data source fusion subsystem including a processor, a memory, and a communication circuit.
  • the device interconnection and data source fusion subsystem is connected to the integrated circuit test platform through the communication circuit.
  • the processor, the memory, and the communication circuit can realize the steps of providing test data generated by the integrated circuit test platform for integrated circuit testing during operation;
  • a resource management subsystem includes a processor, a memory, and a communication circuit.
  • the memory and the communication circuit can implement the steps of providing resource data related to the integrated circuit test and other than the test data when the data is in operation;
  • the data analysis subsystem includes a processor, a memory, and a communication circuit, the processor,
  • the memory and the communication circuit can realize a step of analyzing the integrated circuit test according to the test data and the resource data of the integrated circuit test to obtain result data related to the integrated circuit test;
  • Device interconnection and data source fusion subsystem The resource management subsystem, and the data analysis subsystem connected by respective communication circuits.
  • the device interconnection and data source fusion subsystem includes a central server, a data preprocessing server, and a first database server;
  • the resource management subsystem includes a second database server;
  • the data analysis subsystem includes an analysis server;
  • the A data pre-processing server, the first database server, the second database server, the analysis server, and the test machine are respectively connected to the central server, and the second database server is also connected to the test machine,
  • the data pre-processing server is also connected to the first database server, and the analysis server is also connected to the first database server; during each wafer test, a corresponding test is stored in the second database server.
  • Record data write the corresponding basic information data of each of the wafers, and also write the state record data of the test probe station during each wafer test; the original tests produced by many different types of test machines Data is stored in the central server, and the central server is based on the second database
  • the test record data of the wafer in the server distributes the corresponding original test data to the data preprocessing server.
  • the data preprocessing server preprocesses the original test data, converts the converted test data into a unified format, extracts key parameters, and
  • the pre-processed data is stored in the first database server.
  • the central server issues an analysis task to the analysis server, and the analysis task carries the analysis time stored in the second database server.
  • the analysis server obtains the preprocessed data from the first database server according to the analysis task, analyzes and generates the result data, and automatically sends the result data to the email or WeChat account. Relevant personnel push, so that relevant personnel can grasp the yield of each piece of the test product, the daily yield fluctuation, and the change trend of key parameters in real time; wherein the first database server is a MongoDB database server and the second database server Is the SQL database server.
  • the system further includes: an unmanned workshop-type industrial-level application subsystem including a processor, a memory, and a communication circuit, and the unmanned workshop-type industrial-level application subsystem is tested with the integrated circuit through the communication circuit, respectively.
  • the platform, the device interconnection and data source fusion subsystem, the resource management subsystem, and the data analysis subsystem are connected, and the processor, the memory, and the communication circuit can implement the visualization-based Steps for remote real-time monitoring of integrated circuit testing.
  • another technical solution adopted by the present invention is to provide a machine-readable storage medium on which a machine executable instruction is stored, and the instruction is configured to enable the machine to execute as described in any one of the preceding items. Steps in the method.
  • the information management system and method for integrated circuit testing of the present invention provides test data generated by the integrated circuit test platform for integrated circuit testing, and on the other hand, it provides Resource data related to integrated circuit tests, other than test data, analyze integrated circuit tests according to the test data and resource data of integrated circuit tests to obtain result data related to integrated circuit tests.
  • the result data uses not only test data, but also resource data
  • resource data is all data related to integrated circuit testing, except for test data. According to different test needs, test phases, and test purposes, different resource data can be used. Combined with test data, different analysis can be performed to obtain different result data. According to different result data, combined with different test requirements, test stages, test purposes, etc., the value of test data can be used flexibly and separately.
  • FIG. 1 is a schematic flowchart of an embodiment of an information management method for integrated circuit testing according to the present invention
  • FIG. 2 is a schematic structural diagram of an embodiment of an information management system for integrated circuit testing according to the present invention
  • FIG. 3 is a schematic structural diagram of another embodiment of an information management system for integrated circuit testing according to the present invention.
  • FIG. 4 is a schematic structural diagram of another embodiment of an information management system for integrated circuit testing according to the present invention.
  • FIG. 5 is a schematic structural diagram of another embodiment of an information management system for integrated circuit testing according to the present invention.
  • FIG. 6 is a schematic structural diagram of another embodiment of an information management system for integrated circuit testing according to the present invention.
  • FIG. 7 is a schematic diagram of displaying parameter information in a sixth step
  • FIG. 8 is a schematic diagram showing specific data displayed in the analysis of test parameter indicators
  • FIG. 9 is a schematic diagram of numerical analysis
  • FIG. 10 is a schematic diagram of specific data display
  • FIG. 11 is a schematic diagram of a site yield analysis linear diagram
  • FIG. 12 is a schematic diagram of a site linear diagram
  • FIG. 13 is a schematic diagram showing specific data in a time analysis
  • Figure 14 is a schematic diagram of TouchDown analysis
  • FIG. 15 is a schematic diagram showing specific data of TskMap
  • FIG. 16 is a schematic diagram of Recover / Retest color discrimination
  • FIG. 17 is a schematic diagram of SummaryCheck
  • FIG. 18 is a schematic structural diagram of another embodiment of an information management system for integrated circuit testing according to the present invention.
  • FIG. 19 is a schematic structural diagram of another embodiment of an information management system for integrated circuit testing according to the present invention.
  • 20 is a schematic structural diagram of another embodiment of an information management system for integrated circuit testing according to the present invention.
  • 21 is a schematic structural diagram of another embodiment of an information management system for integrated circuit testing according to the present invention.
  • 22 is a schematic structural diagram of another embodiment of an information management system for integrated circuit testing according to the present invention.
  • FIG. 1 is a schematic flowchart of an embodiment of an information management method for integrated circuit testing of the present invention
  • FIG. 2 is a schematic structural diagram of an embodiment of an information management system for integrated circuit testing of the present invention.
  • the information management system of the embodiment can implement the information management method of the embodiment of the present invention.
  • the information management method of integrated circuit test and the information management system of integrated circuit test are described in detail here. .
  • the integrated circuit testing information management system 100 includes a processor 1, a memory 2, and a communication circuit 3.
  • the processor 1 is coupled to the memory 2 and the communication circuit 3, respectively.
  • the system 100 is connected to the integrated circuit test platform 200 through the communication circuit 3.
  • processor 1, memory 2 and communication circuit 3 can implement the steps in any of the following information management methods for integrated circuit testing during operation.
  • the information management method of the integrated circuit test includes:
  • Step S101 Provide test data generated by an integrated circuit test platform for integrated circuit testing.
  • the integrated circuit test platform is an integrated circuit test platform of more than one level, and each level of the integrated circuit test platform includes multiple test instruments.
  • Step S102 Provide resource data related to integrated circuit testing other than test data.
  • Step S103 Analyze the integrated circuit test according to the test data and resource data of the integrated circuit test to obtain result data related to the integrated circuit test.
  • the scope of the integrated circuit test platform can determine the size and amount of test data and the size and amount of resource data.
  • the scope of the integrated circuit test platform is divided into different ways according to the purpose of the test, the test phase, or the purpose to be achieved by using the relevant data of the integrated circuit test.
  • the design verification phase R & D phase
  • the production link phase another example: a company's design verification phase for a product, a company's design verification phase for multiple different products, and multiple companies' Design verification stage, design verification stage for multiple products by multiple companies, production link stage for multiple batches of products from a company, production link stage for multiple batches of products from multiple companies, etc.
  • test data and resource data can be selected for analysis to obtain the required result data.
  • the test data is the data obtained by directly testing the test equipment. It can be specific quantitative data (specific voltage values, current values, etc.), or qualitative data (for example: test passed and failed, etc. Wait).
  • Resource data is data related to integrated circuit testing, not directly tested by test equipment, such as: basic information data (lot number, transfer date, time, place, test product UID, etc.), test process, test instrument information , Test items, test parameters, test records, etc.
  • the result data is obtained by analyzing the integrated circuit test based on the test data and resource data.
  • a pile of products is a mixture of multiple batches. After testing by a testing instrument, the test data is qualitative "pass” and "fail". If you only analyze the test data, you can get the number of products in this pile of products " "pass”, how many products "fail”, can also get the pass rate and failure rate of this bunch of products. If a batch number (resource data) is recorded for each product in this pile of products, the product obtained by further analysis can be a product with a certain batch number. If not all products in this batch number are "fail”, and each product in this bunch of products also records raw materials (resource data), you can further analyze that the products in "fail” are products of a certain batch number of raw materials. It can be seen that the test data combined with the resource data related to the test can get more in-depth result data, which is more helpful to dig deeper into the problem in order to solve the problem in a targeted and efficient manner.
  • processor 1, memory 2 and communication circuit 3 of the information management system 100 for integrated circuit testing can implement the steps in the above information management method during operation, but in practical applications, the processor 1 and memory
  • the specific deployment of 2 and communication circuit 3 need to be determined according to the specific application, that is, there are many specific deployments of processor 1, memory 2, and communication circuit 3.
  • the embodiments of the present invention do not limit the information management system for integrated circuit testing. 100 specific deployments.
  • the integrated circuit testing information management system 100 includes a device interconnection and data source fusion subsystem 10, a resource management subsystem 20, and a data analysis subsystem 30.
  • Each subsystem includes a processor 1, a memory 2, and a communication circuit. 3.
  • the device interconnection and data source fusion subsystem 10 is connected to the integrated circuit test platform 200 through the communication circuit 3, and the processor 1, the memory 2 and the communication circuit 3 can implement step S101 during operation; the processor 1 of the resource management subsystem 20 Memory 2 and communication circuit 3 can implement step S102 during operation; processor 1, memory 2 and communication circuit 3 of data analysis subsystem 30 can implement step S103 during operation; device interconnection and data source fusion subsystem 10, resource management
  • the subsystem 20 and the data analysis subsystem 30 are connected through respective communication circuits 3 according to actual application needs.
  • the device interconnection and data source fusion subsystem 10 is based on a test instrument of an integrated circuit test platform. Starting from its bottom layer, it uses a data source to integrate a user interface (UI, User Interface) to integrate complex and diverse test data for integrated circuit testing. ;
  • UI user interface
  • the device interconnection and data source fusion subsystem 10 allows the test instrument to generate original test data through an improved test operation interface (OI, Operator), and performs all preprocessing in the cloud through calculation and screening.
  • the resource management subsystem 20 performs resource information fusion, system function upgrade, and manages and automates real-time updates to the test process.
  • the data analysis subsystem 30 uses the intelligent test and analysis method of the integrated ecological chain of the integrated circuit according to the test data and resource data to finally obtain the result data, such as a grid table of the final yield, initial yield, retest rate, and response rate of the R & D. Visualization, test time, wafer map, and more.
  • the information management system and method for integrated circuit testing provide test data generated by an integrated circuit test platform for integrated circuit testing on the one hand, and resource data related to integrated circuit testing and other than test data on the other.
  • the integrated circuit test is analyzed to obtain the result data related to the integrated circuit test.
  • resource data is all data related to integrated circuit testing, except for test data.
  • different test needs, test phases, and test purposes different resource data can be used.
  • different analysis can be performed to obtain different result data.
  • the value of test data can be used flexibly and separately.
  • the integrated circuit test includes at least one of the design verification stage test and the production link test; the design verification stage test includes the wafer test; the production link test includes the process process test, wafer test in the wafer manufacturing stage, and At least one of finished product tests.
  • step S101 may specifically include: obtaining an integrated circuit test platform for integration The original test data in different formats generated by the circuit test; the original test data is converted into the converted test data in a uniform format. If the format of the original test data generated by the integrated circuit test platform is the same and meets the analyzed data format, this step can be omitted.
  • the integrated circuit test is a wafer test
  • the test data is generated by a variety of different types of test machines.
  • the test data includes test data for each wafer.
  • the wafer test is a relatively small-scale test, such as wafer testing in the R & D verification phase, or the result data is not required, for example, the test of the production process does not require much result data, and the resource data can be less data.
  • the corresponding result data is not much.
  • the resource data includes test record data of each wafer, and the test record data of each wafer corresponds to the test data of each wafer.
  • the resource data also includes basic information data of each wafer, and the basic information data of each wafer corresponds to the test data of each wafer.
  • the resource data also includes the state record data of the test probe station during each wafer test, and the state record data of the probe station corresponds to the test data of each wafer.
  • the result data includes the yield of each test product, the daily fluctuation of yield, and the trend of key parameters.
  • the information management method further includes: automatically pushing the result data to the relevant person; wherein the result data is automatically pushed to the relevant person via email or WeChat.
  • the above methods can all be implemented by the three subsystems of the information management system for integrated circuit testing, and the three subsystems of the information management system for integrated circuit testing can be further specifically deployed.
  • the wafer test is a relatively small-scale test, or the result data is not much, the three subsystems can be easily deployed.
  • the device interconnection and data source fusion subsystem 10 includes a central server 101, a data preprocessing server 102, and a first database server 103;
  • the resource management subsystem 20 includes a second database server 201
  • the data analysis subsystem 30 includes an analysis server 301; a data pre-processing server 102, a first database server 103, a second database server 201, an analysis server 301, and a test machine 2001 are respectively connected to the central server 101, and the second database server 201 is also connected to The testing machine 2001 is connected, the data pre-processing server 102 is also connected to the first database server 103, and the analysis server 301 is also connected to the first database server 103.
  • the corresponding test record data is stored in the second database server 201, the corresponding basic information data of each wafer is written, and the test probe table of each wafer is also written at the same time.
  • Status record data; raw test data generated by a variety of different types of testing machines are stored in the central server 101, and the central server 101 distributes the corresponding raw test data to the data pre-processing server 102 according to the test record data of the wafer in the second database server 201
  • the data pre-processing server 102 pre-processes the original test data, converts the converted test data into a unified format, extracts key parameters, and stores the pre-processed data in the first database server 103.
  • the central server 101 An analysis task is sent to the analysis server 301.
  • the analysis task carries resource data stored in the second database server 201 and is used during analysis.
  • the analysis server 201 obtains preprocessed data from the first database server 103 according to the analysis task, and analyzes the analysis data. And generate result data, and automatically send the result data via email or WeChat Relevant personnel to push for real-time control personnel to test each piece of product yield, daily yield fluctuations, trends of key parameters.
  • the first database server 103 is a MongoDB database server
  • the second database server 201 is a SQL database server.
  • the original test data includes, but is not limited to, raw unprocessed data (RawData) and a standard test data format (STDF, Standard Test Data Format) unrelated to the test system.
  • RawData raw unprocessed data
  • STDF Standard Test Data Format
  • the test starts and ends on each wafer (Wafer).
  • the necessary Wafer basic information is stored in the second database server 201 (SQL Server), so that the central server 101 can query Wafer test records for use.
  • the operation interface (OI) is required at the beginning and end of each wafer.
  • the second database server 201 (SQL Server) writes the basic information of Wafer, including the Wafer's product name, batch number, film number, start test time, end test time, test machine used, test probe station (Prober) , Probe card (ProberCard), etc., in order to quickly analyze the Wafer when detailed data analysis is not needed. At the same time, it is also necessary to record the status of the test probe station (Prober) to the second database server 201 (SQL Server) in order to monitor the test environment.
  • the test data is stored in the central server 101, and the central server 101 distributes data processing tasks to the data preprocessing server 102 and the analysis server 301 according to Wafer's test records in the second database server 201 (SQL Server).
  • the data pre-processing server 102 stores the pre-processed data in the first database server 103 (MongoDB) after pre-processing the data, so that the analysis server 103 can subsequently generate a report of the result data.
  • the data pre-processing server 102 and the analysis server 301 may be completed by multiple servers, and the workload is dynamically allocated according to the intensity of the data and analysis processing tasks.
  • the first database server 103 (MongoDB) is used to record the preprocessed data.
  • the generated preprocessed data is stored in the first database server 103 (MongoDB).
  • the preprocessed data includes but is not limited to WaferMap, detailed data of all Die key parameters
  • the data preprocessing server 102 is assigned data processing tasks by the central server 101. Because different products focus on different parameters, the preprocessed data is also different.
  • master + script master refers to the test software interface
  • script is an optimization program written separately, not integrated in the software, and can be called) to process data. Different products use different processing scripts. The key parameters of the product to be processed are listed in the product processing script. Extract and save it to the first database server 103 (MongoDB).
  • the central server 101 sends an analysis task to the analysis server 301.
  • the analysis server 301 obtains the preprocessed data from the first database server 103 (MongoDB) according to the analysis task distributed by the center server 101, analyzes and generates The analysis report corresponding to the result data.
  • the system finally automatically pushes the analysis report to the product-related engineers and other users through email and WeChat, so that they can grasp the yield of each piece of the tested product in real time, the daily fluctuation of yield, and key parameters. Trends.
  • the embodiment of the present invention uses a central server, a data preprocessing server, an analysis server, a second database server (SQL Server), and a first database server (MongoDB) to test a multi-level integrated circuit composed of various internationally advanced large-scale automated test instruments.
  • the integrated circuit test data sources generated by the platform are integrated, and the original test data generated by different types of test equipment is planned to be converted to a unified format as the data source.
  • the test data format includes detailed data in RawData and STDF (Standard Test Data Format) formats.
  • STDF Standard Test Data Format
  • the integrated circuit test is a test of the production link; the integrated circuit test is a wafer test or a finished product test of the production link; Step S102 may specifically include: establishing, managing, and updating the test flow of the integrated circuit test in real time; registering and managing the integrated circuit test Information of test products; register and manage information of test equipment for integrated circuit testing; monitor and manage task status of integrated circuit testing; monitor and manage test information of production links; perform test UIDs of test products and UIDs in the server Verify, and record the verification result and test version number in real time; modify, add, delete management of wafer map related information of test products for integrated circuit testing.
  • the above method can be implemented by the resource management subsystem 20.
  • the resource management subsystem 20 can be deployed in a complex manner.
  • the related functions of the resource management subsystem 20 and the resource data provided by it can be selectively used.
  • the resource management subsystem 20 may be divided into several functional modules, and each functional module corresponds to the specific steps in step S102 described above.
  • the resource management subsystem 20 includes: a test task model module 202, a product information registration and management module 203, a product test instrument information module 204, a test task status monitoring module 204, a test production management module 206, A matrix identification number (DiagUid) verification and management module 207 and a map editing (MAPEDIT) information management module 208.
  • test task model module 202 which is used to establish, manage, and update the test flow of integrated circuit testing in real time; a test product information registration and management module 203, which is used to register and manage information on test products for integrated circuit testing; test instrument information module 204 For registering and managing information of test instruments for integrated circuit testing; test task status monitoring module 205 for monitoring and managing task status of integrated circuit testing; test production management module 206 for monitoring and managing testing of production links Information; DiagUid verification and management module 207 is used to verify the test UID of the test product and the UID in the server, and records the verification result and test version number in real time; MAPEDIT information management module 208 is used to test the integrated circuit Modify, add, and delete information about the wafer map of your test product.
  • test product information and test requirements register and store in advance.
  • the information can be used whenever the product list needs to be called.
  • the product name is the only one that cannot be repeated, including the test product name, test equipment (DEVICE), Test procedures and test probe card names, etc.
  • DEVICE test equipment
  • Test procedures test probe card names
  • test instrument information is divided into three categories: "prober”, “tester”, and “pe”. Any test instrument can be an accessory of another instrument, that is, it belongs to "ID ", Fill in the ID of the attached instrument, and it will be reflected in the operation engineer version list of the instrument list.
  • the setting file is called according to the "product name", and the process that requires processing and testing is also called.
  • the default number of tasks in the book is the number of incoming materials.
  • the system supports temporary changes, additions, and deletions. These information can be automatically modified and updated in the system. .
  • test task label is unique, that is, a test task book label can only be the only test program, test process, and Test instrument information, etc.
  • This module is applied in the process of rectification of integrated circuits. It has security, uniqueness and traceability.
  • the system verifies the UID of the tested product and the UID information in the server, and records the test version number and verification result in real time. Verify the correctness of the testing process.
  • the main verification information includes the test result serial number (bin) total number, the difference comparison of each station (site), the number of mistested dies at each station (site), and the number of test dies at each site (site) , The total number of test dies, etc., check and verify through multiple dimensions to ensure the uniqueness of each test.
  • the test algorithm is as follows:
  • MAPEDIT information management mainly manages more than 100 items of information such as the coordinates (XY), pass (PASS), and fail (FAIL) of each test chip of the product, including the lot ID (LOT ID), component type (Part Type), Job Name, Tester Type, Setup Time, Start Time, Operator Name, Sublot ID, Test Code (Test Code), Job Speed (Job, Rev), Execution Type (Executive Type), Execution Version (Execion Version), Test Temperature (Test Temp), Flow ID (Flow ID) and more than 100 items of information.
  • lot ID LOT ID
  • Part Type component type
  • Job Name Job Name
  • Tester Type Setup Time, Start Time, Operator Name, Sublot ID
  • Test Code Test Code
  • Job Speed Job Speed
  • Execution Type Execution Type
  • Execution Version Execution Version
  • Test Temperature Test Temp
  • Flow ID Flow ID
  • the system will automatically obtain the test product information and set the corresponding rules and Configuration, the process is to import the test range required by the customer into the system through the basic map (Basic Map, that is, the test yield distribution map that is expected to achieve the ideal state), and check the test items through the integrated wiring (BDF, Building Distribution Frame) software module
  • Basic Map that is, the test yield distribution map that is expected to achieve the ideal state
  • BDF Building Distribution Frame
  • the information of the test probe card used is released through the probe card (ProberCard Release, that is, the number of times the test probe is stuck, which will affect the test result) is imported into the system, and the information verification is finally performed.
  • the system verification After the system verification is correct, it is scheduled according to the test requirements, intelligently allocates and decides, starts the test, integrates the test data collection area information, monitors the test data in real time, and uploads the server to complete the information management.
  • the integrated circuit test is a test in the production link; the integrated circuit test is a wafer test or a finished product test in the production link.
  • the resource management subsystem of the embodiment of the present invention integrates a complete set of information registration and information management from test product storage to storage, complete functions, practical and simple, controllable process, and can be controlled remotely through secure online remote control. It is a set of modules Management, visualization, perfect, standardized resource management subsystem, its functions include test process, product registration, test program call, device call, probe card management, test equipment, incoming materials registration, test tasks, test process card management , Production process tracking, progress query, product registration, DiagUid, automatic update, MAPEDIT, Map data statistics, password modification, test Map offset check and other integrated circuit test information registration and management to facilitate test monitoring, query, analysis and traceability .
  • the analysis includes analysis of test parameter indicators, test yield analysis, test time analysis, wafer map information analysis, test summary inspection and analysis, probe stuck pin height analysis, result data feedback requirement analysis, and test record historical information analysis. At least one.
  • step S103 may specifically include: receiving inputted first related information for querying resource data, the first related information including a test product name, a test instrument, a test batch number, and a test machine number; and receiving input for querying resource data
  • the second related information includes the start time and the end time; the third related information used for querying the resource data is input, and the third related information is the wafer test or the finished product test; the input is used for the query
  • the fourth related information of the resource data, the third related information is data of a query database or local data; and according to the first related information, the second related information, the third related information, and the fourth related information, reading a related file of the material data, It displays the read progress and parameter information in real time; receives the input analysis function information corresponding to the actual needs, and displays the corresponding data format; according to the analysis function information, the analysis result data is generated.
  • the result data is presented in at least one of a file, a report, and a chart.
  • the method further includes: analyzing the integrated circuit test according to the feedback requirements of the test data, resource data, and result data of the integrated circuit test to obtain the result data related to the integrated circuit test and corresponding to the feedback request; the result data is filed At least one of the forms, reports, and charts is displayed on the visual interface.
  • the result data corresponding to the analysis of the test parameter index includes the X coordinate, Y coordinate, station corresponding to the XY coordinate of each die on the wafer, the result of passing or failing the XY coordinate, and the passing of the test item. Or failed results, the specific test value of the test item.
  • the result data corresponding to the test parameter index analysis is the value of the wafer failure value, the test item failure value, the interquartile range value greater than 1.5 times the test value, and the interquartile range value greater than 3 times the test value. Obtained after culling.
  • the result data corresponding to the test parameter index analysis is presented in the form of a first chart.
  • the first chart includes: a normal distribution chart, a scatter chart, a histogram, a box chart, and a map of the test items.
  • the first chart's mark types include: upper limit, lower limit, maximum value, minimum value, and average value. , Median value, standard deviation, average value plus 3 times standard deviation, average value minus 3 times standard deviation, first quartile, third quartile; numerical analysis is to average values, standard Poor analysis.
  • the result data corresponding to the test yield analysis includes: final yield, initial yield, retest rate, response rate, final number of passes, initial number of passes, number of retests, number of responses, test machine number, and pin card number;
  • the result data corresponding to the test yield analysis is presented in the form of a second chart; the second chart includes: rectification batch yield analysis chart, probe card yield analysis chart, workstation yield analysis linear chart, failure serial number analysis chart, single Work station failure analysis chart and multiple station linear charts; rectification batch yield analysis chart refers to displaying the values of different batches of test products in different colors for analysis of yield difference between test product batches;
  • probe card Yield analysis chart refers to forming different test conditions into a test yield analysis chart for analyzing the difference in yield between different hardware;
  • Work station yield analysis linear chart refers to making a linear chart of different stations for Analyze the difference in yield between stations;
  • the FailBin analysis chart refers to the order of all the failed serial numbers from large to small, and each test result serial number (bin)
  • the single station failure analysis chart refers to the highest number of three failure serial numbers.
  • An overlay histogram is used to analyze the difference in station yield through the height of each station;
  • a multi-station linear chart refers to taking the highest number of three failure numbers to make a linear chart for analysis of whether it is caused by the station difference The number of failures increases.
  • the result data corresponding to the test time analysis includes: total test time, normal test time, retest test time, pause time during normal test, total test time, pause time during retest, total test time, retest
  • the first wafer time, test machine number, and pin card number; the result data corresponding to the test time analysis is presented in the form of a rectification batch yield analysis chart.
  • the rectification batch yield analysis chart refers to displaying the values of different batches in different colors. Come out for analysis of test time differences between batches.
  • the TouchDown analysis refers to the time when the height of each probe is displayed.
  • the wafer map information analysis includes: the distribution of all test result serial numbers, the distribution of retesting and response test serial numbers, and the analysis of multiple analysis algorithms to determine whether the map is abnormal. Multiple maps can be superimposed and analyzed. Failure serial number distribution; the corresponding result data of wafer map information analysis includes: the number of test result serial numbers, the percentage of test result serial numbers, the number of station differences, the percentage of station differences, and specific station information; the wafer map
  • the result data corresponding to the information analysis is presented in the form of color-differentiated reply / retest.
  • the color-differentiated reply / retest can analyze the level of the response rate, determine whether there are obvious pattern graphics for analyzing hardware differences, and guide subsequent tests and tests. Increase yield.
  • the integrated circuit test is a test in the production link; the integrated circuit test is a wafer test or a finished product test in the production link.
  • the above methods can all be implemented by the data analysis subsystem 30.
  • the specific functions of the data analysis subsystem 30 of the information management system for integrated circuit testing are as follows:
  • the data analysis subsystem 30 includes a data acquisition layer, a big data processing analysis layer, and an application layer.
  • the data acquisition layer mainly obtains test data and resource data from the device interconnection and data source fusion subsystem 10 and the resource management subsystem 20, respectively.
  • the data processing and analysis layer mainly analyzes and processes the acquired test data and resource data
  • the application layer mainly uses the result data after analysis and processing.
  • the data analysis subsystem 30 provides integrated circuit test parameter index analysis, wafer test yield analysis, test time analysis, wafer MAP map information analysis, summary check and analysis, and probe pin height Analysis, report (Report), test record (SQLHistory) analysis.
  • Each subsystem of the information management system tested by this integrated circuit has the characteristics of data intercommunication and data backup, high security, and the data analysis subsystem 30 can realize the function of data retrieval, tracking, and analysis of the information of the entire ecological chain, which is beneficial to the follow-up Monitor test results in real time.
  • Step 1 Enter the product name, test device (Lot), tester number (Tester) and other information values in R1.
  • the default is blank, that is, a full search is performed.
  • Step 2 Select the required start time and end time in R3.
  • the default start time is 30 days before the tool start time, and the default end time is the tool start time.
  • Step 3 Select wafer test (CP) or finished product test (FT) in R4, which is related to the searched database location.
  • Step 4 Select whether to use the database data or local data in R5, then all the eligible information will be displayed in L1, and finally select which specific data needs to be read according to the actual needs, and read the temp file or csv file.
  • the main data query methods include: "SQL Search” is used to query the temp file in the SQL database; “SQL Read” is used to read the temp file in the SQL database; “SQL DCParameter” is used to read the csv file in the SQL database; “Local “Search” is to get the temp file in the local drive letter; “Local Read” is to read the temp file in the local drive letter; “Local DCParameter” is to read the csv file in the local drive letter.
  • Step 5 The file being read will show the progress in R5, and after the reading is completed, it will be shown in R7, showing the number and progress of the read in real time.
  • Step 6 If the CSV file is read, all parameter information will be displayed in L1, including the following full parameter information:
  • TC is the total number of tests
  • RC is the number of retests
  • WC is the total number of tests minus the number of retests.
  • L12 Product name. There can be multiple product names.
  • L15 statistical information of the lot number of the product name, LC is the lot number, TC is the total number of products tested; RC is the number of retests of the product; WC is the total number of tests of the product minus the retested number.
  • L16 The statistical information of the specified batch number.
  • TC is the total number of tests for this batch number;
  • RC is the number of retests for this batch number;
  • WC is the total number of tests for this batch number minus the number of retests.
  • Step 7 Select the special function button in U1.
  • Different functions will display different data formats in C1.
  • the main functions are as follows: “Test parameter index analysis”, which mainly analyzes specific parameters of DC parameters; “Yield analysis”, which mainly analyzes yield information and specific site and Bin information of wafer or FT files; “Time analysis”, mainly Analyze the test time information and touchdown information of wafer or FT files; “TskMap”, mainly view the map information of wafer and various map-related inspection functions; “SummaryCheck”, mainly view the summary and analysis results of wafer or FT files; “TouchDown “, Mainly analyzes the actual touchdown number and site test number of a complete wafer;” Report “, which mainly generates different reports required by different customers;” SQLHistory “, which mainly views information in the SQL database, including CP test records, FT Test records, etc.
  • Step 8 Select the corresponding function in U1 according to the actual needs and generate new analysis data.
  • Step 9 Select different tabs of C1, which can be displayed on multiple terminals such as WeChat push, email push, and local save.
  • U311 X, Y, Site, and FlowPF are fixed columns, XY represents its XY coordinates on the wafer, Site represents the specific station where this coordinate was tested, and FlowPF represents whether the final result of this coordinate is pass or fail .
  • the following columns will display different data according to the selected test items. One test item has two columns, the first column is the pass / fail result of the test item, and the second column is the specific test value of the test item.
  • Remove ItemFail remove the value of this test item as fail
  • Remove Outliers removes interquartile values greater than 1.5 times the test value
  • RemoveExOutliers removes the interquartile value greater than 3 times the test value
  • the value of the interquartile range refers to the degree of dispersion in statistics, which means Sort the values of each variable in order of magnitude, and then divide this sequence into quartiles.
  • the difference between the value on the third quartile and the value on the first quartile; the value of the interquartile range of the test value It refers to arranging each test value in order of size, and then dividing this sequence into four equal parts.
  • the difference between the value on the third quartile and the value on the first quartile; the difference reflects the middle 50% of the data.
  • the degree of dispersion the smaller the value, the more concentrated the data in the middle; the larger the value, the more scattered the data in the middle.
  • test parameter index analysis By converting hundreds or even thousands of test parameters into intuitive visual charts, at the same time, any test parameter can be distributed on a map to form a test value Map, which can be changed by color. It can clearly see whether it has regionality and trend, and can more intuitively judge whether there is a problem with the wafer itself.
  • the test value distribution of the entire map is also very important for the factory that manufactures the wafer.
  • ProberCard yield analysis chart form a test yield analysis chart according to different test conditions to see the yield difference between different hardware
  • Site yield analysis linear diagram make different sites a linear diagram to visually see the yield difference between sites, as shown in Figure 11;
  • FailBin analysis chart arrange the number of all failbins from large to small, and accumulate the number of each test result number and the number of all previous test result numbers, and make a cumulative percentage line to see which tests are the main failure The result of the serial number, and how much the impact.
  • Multi-site (Site) linear diagram Take the highest number of three failbins to make a linear diagram, and see if the number of fail caused by the difference in workstations becomes larger, as shown in Figure 12.
  • Test yield analysis advantage analyze the test yield map from multiple dimensions such as Lot yield, ProberCard influencing factors, test sites, and FailBin factors. From the final yield, the initial yield, the retest rate, and the response rate, fast Statistics of each Lot's summary can clearly see and analyze regional and trending.
  • U331 The column headings are fixed parameters, including TotalTime, NormalTestTime, TestTestTime, NormalPauseTime, NormalTotalTime, TestPauseTime, TestTotalTime, TestFirstDieTime, TesterID, PCID, which represent the total test time, normal test time, retest test time, normal test Pause time in the process, total time of normal test, pause time in the process of retest, total time of retest, first die time of retest, test machine number, pin card number.
  • U332 Select the number of source data, as many rows as there are data files.
  • TouchDown analysis TouchDowndetail, showing the time of each touchdown, as shown in Figure 14.
  • Time analysis advantage By looking at the test time of each piece, you can get the actual test time of each piece. And for films with a long test time, you can use touchdown to see the time interval and find the reason for the longer time, thereby improving production efficiency.
  • MAP map of the CP test includes the distribution of the serial numbers of all test results, the distribution of the serial numbers of retesting and reply test results, and determining whether the MAP map is abnormal after various algorithms, etc. It is also possible to superimpose multiple maps and analyze the failure. Distribution of sequence numbers.
  • U351 The first 4 columns of the column header are fixed parameters, including BinCount, BinYield, S2S, Count, and S2S Yield, which respectively represent the number of test result serial numbers, the percentage of test result serial numbers, the number of workstation differences, and the percentage of workstation differences , followeded by specific station information, there are as many columns of data as there are stations, representing the number of serial number of each station.
  • U332 Select the number of source data, as many rows as there are data files.
  • Recover / Retest color differentiation visually see the level of the response rate. If there is a clear pattern, it means that there is a difference in the hardware. Guidance is provided for subsequent tests and improving the yield, as shown in Figure 16.
  • the data analysis subsystem 30 of this embodiment also has other advantages:
  • the system function is automatically updated. In order to ensure that the exe used by everyone is the latest version, it is necessary to make a judgment on the exe version. If it is lower than the latest version, a new exe executable file will be downloaded from the server again. When the tool opens, find its version number at the top.
  • the implementation code is as follows:
  • the data analysis subsystem 30 has a large number of configuration files, and each configuration file has its corresponding function. For example, device setting configures the scope of the map and yield setting configures Product judgment rules. If the administrator updated the profile, others should also use the latest profile. After any operation on the configuration file, you can choose to upload the modified configuration file to the server. Each time you use the configuration file, the configuration file on the server is downloaded to the local use. In addition, if there is any misoperation or uncertainty, you can also choose not to upload the modified configuration file and only update the local configuration file. After confirming that there is no error, you can choose to upload the server to avoid misoperation and make all configuration files used by everyone Was updated by mistake.
  • the specific content of the horizontal and vertical continuous failure algorithm of the Map is: with a fail as the center, first look for the fail on both sides of the X axis. If the number of consecutive fail is greater than expected, it will fail. If there is a pass, it will be all cleared; fail, same as X axis.
  • the difficulty is that the X-axis and Y-axis need to be calculated separately, and the results need to be combined at the same time, so the algorithm uses two variables to store the values of the X-axis and Y-axis, and finally puts the combined result into a final variable Use this variable to trace the final result.
  • the key part of the implementation is as follows:
  • the specific content of the continuous failure algorithm of the site is that it takes a fail as the center, finds the same continuous site as it, and determines whether it is a fail. If the continuous fail is greater than expected, it will fail.
  • the difficulty is that almost all CPs will be re-tested. The final results need to be replaced with the previous test results, but the test order cannot be changed, and then their sites are consistent, and then the number of consecutive fail, so the sites are grouped first. Loop judgment, use a dictionary with XY coordinates as the key, test order as the value, replace the same XY as the key value after retesting, list all pass / fail results with a sequential list, and finally judge by the sequential list Whether the number of consecutive failures is greater than expected.
  • the key implementation code is as follows:
  • the specific content of the TD continuous failure algorithm is to find a continuous touchdown with a fail as the center. If there is a fail in the touchdown, the fail number is accumulated, and if it is greater than expected, it is invalid.
  • the difficulty lies in judging whether the touchdown is continuous, and it will also encounter retesting problems. Therefore, it is also necessary to replace the retested values with the previous ones, and then group them according to time for judgment. Use a sequential list to connect pass / fail. Can judge whether fail is continuous.
  • the key implementation code is as follows:
  • the original-> retesting distribution map lists all the retested dies and compares them with the previous BIN number. If it changes from fail to pass, it is displayed in green and fail to fail, but the BIN number has not changed and is indicated in yellow. The BIN number has also changed, it is shown in red. The difficulty lies in showing it in a visual chart. It is necessary to list all BINs, fill the numbers in the circles, and change the size of the circles accordingly according to the size of the numbers, and distinguish them with different colors.
  • the key part of the implementation is as follows:
  • the data analysis subsystem of the embodiment of the present invention is developed with grid tables and visualization, test time, test map and other online intelligent analysis modules such as final yield rate, initial yield rate, retest rate, and response rate. It includes Wafer Lot Yield summary, Wafer LotBinMap, Wafer LotS StackMap, Probe / Setting, 6sigma, Test time, SummaryCheck, Probe / Setting, Report and other multi-dimensional analysis functions, through the analysis results of big data, to achieve interconnection and interoperability between multiple platforms, through a certain algorithm Extraction, splitting, analysis, merging and other methods will transform these data into easy-to-understand files and charts, so that people in different fields can quickly get the desired analysis results.
  • the data analysis subsystem of the embodiment of the present invention can realize the real-time, mobility, and intelligence of the company's office; it has the characteristics of remote data interworking and remote data backup, high security, and continuous data accumulation, based on 6 months to 1 After years of data accumulation, the data analysis subsystem 30 introduces an industrial big data analysis model to achieve data retrieval, tracking, analysis, early warning, pre-judgment, etc. of the entire ecological chain test information, to guide production, improve production efficiency and test yield.
  • the method further includes: performing remote real-time monitoring of the integrated circuit test based on the visualization technology.
  • remote real-time monitoring of integrated circuit testing based on visualization technology may include: remote real-time monitoring of test probe stations and test machines in integrated circuit testing based on visualization technology; data in integrated circuit testing based on visualization technology Real-time remote real-time monitoring of acquisition, data processing, data analysis, and data storage; remote real-time monitoring and management of the entire process of integrated circuit testing based on visualization technology.
  • the method further includes: when an abnormality is detected in the test workshop, an alarm signal is issued; in response to the alarm signal, the abnormality is processed on the visual interface.
  • the remote real-time monitoring of the test probe station based on the visualization technology may specifically include: recording the number of continuous defective products and displaying them; if the number of recorded continuous defective products is greater than the misjudgment threshold entered, sending to the automated test probe station An instruction to stop the test, and also send an alarm instruction to indicate the alarm.
  • the above method can be implemented by a newly-added subsystem in the informatization management 100 of integrated circuit testing.
  • the informatization management 100 of integrated circuit testing further includes an industrial-level application subsystem similar to an unmanned workshop. 40.
  • the unmanned workshop-type industrial-level application subsystem 40 includes a processor 1, a memory 2, and a communication circuit 3.
  • the unmanned workshop-type industrial-level application subsystem 40 communicates with the communication circuit 3 respectively.
  • Integrated circuit test platform 200, device interconnection and data source fusion subsystem 10, resource management subsystem 20, and data analysis subsystem 30 are connected.
  • Processor 1, memory 2 and communication circuit 3 of an unmanned workshop industrial application subsystem 40 During work, the steps of remote real-time monitoring of integrated circuit testing based on visualization technology can be realized.
  • the unmanned workshop-like industrial-level application subsystem 40 of the embodiment of the present invention is a remote real-time monitoring and visualization system. Specifically, the system is controlled by the unmanned workshop monitoring system 40.
  • the test workshop 2002 performs monitoring and management.
  • the test workshop 2002 includes production testing equipment.
  • the unmanned workshop monitoring system 40 includes an automated test probe station (Prober) remote monitoring and management platform 401, an automated test machine (Test) remote monitoring and management platform 402, Data real-time monitoring platform 403, full-process monitoring remote management platform 404; test shop 2002 abnormal alarm, real-time monitoring and visualization system responds to abnormal mechanism and processing interface in time.
  • an automated test probe station (Prober) remote monitoring and management platform 401 includes: a processor 1, a memory 2, a communication circuit 3, a misjudgment counting module 4011, an input module 4012, and a display module. 4013, alarm 4014; the input module 4012 is connected to the memory 2 through the communication circuit 3, and the processor 1 is connected to the memory 2, the misjudgment counting module 4011, the alarm 4014, and the test probe station 2003 through the communication circuit 3, and the misjudgment count
  • the module 4011 is connected to the display module 4013 through the communication circuit 3.
  • the input module 4012 is used to input the misjudgment threshold and is stored in the memory 2.
  • the misjudgment counting module 4011 is used to record the number of consecutive defective products
  • the display module 4013 is used to display the number of consecutive defective products
  • the processor 1 is used to judge the misjudgment count. Whether the number of consecutive defective products recorded by the module is greater than the misjudgment threshold, decides whether to send a test stop instruction to the test probe station 2003, while the processor 1 sends a test stop instruction to the test probe station 2003, it also sends an alarm to the alarm device 4014.
  • the alarm instruction instructs the alarm device 4014 to give an alarm.
  • an automated test remote monitoring management platform 402 includes a camera 4021 and a smart terminal 4022.
  • a wireless communicator 40211 is fixedly installed in the camera 4021, and wireless communication is performed.
  • the device 4011 is connected to the server 4023, the server 4023 is connected to the smart terminal 4022, and the processor 4021 is fixedly installed inside the smart terminal 4022.
  • the processor 40221 is connected to the power interface 40222, USB interface 40223, decoder 40224, modem 40225, controller 40226, and A / D converter 40227, A / D converter 40227 is connected to video capture card 40228, and video capture card 40228 is connected to wireless communicator 40229.
  • This automated test machine remote monitoring and management platform 402 performs remote monitoring and management on the basis of mobile Internet.
  • the smart terminal 4022 uses a tablet.
  • the real-time data monitoring platform 403 includes a data acquisition module 4032, a single-chip microcomputer 4031, a wireless communication module 4033, a data processing module 4034, a data analysis module 4035, a data storage module 4036, and a data acquisition module 4032. It is connected to the single-chip microcomputer 4031, the single-chip microcomputer 4031 is connected to the wireless communication module 4033, and the data processing module 4034, the data analysis module 4035, and the data storage module 4036 are connected to the single-chip microcomputer 4031 to avoid the space distance of data monitoring. .
  • the whole process monitors the remote management platform 404, which consists of a real physical system connected to the Ethernet, a virtual information system, information feedback, information control, a monitoring management platform, design changes, manufacturing changes, data / information, and digital models.
  • the monitoring and management platform is based on the information perception layer of the Internet of Things, and uses virtual reality technology to establish a three-dimensional visual digital model of the workshop and production line objects for monitoring and management. It runs through the entire design, manufacturing and management to achieve a high degree of integration of real physical systems and virtual information systems. .
  • the information management system of the embodiment of the present invention can provide rich and fast online services, improve testing efficiency, improve testing productivity, and convert all states of the cleanliness workshop (including test prober, test machine, test data, and information graphics).
  • Real-time integration on the information system Operators only need to be on the workbench to monitor the status of the workshop in real time. The abnormalities can be responded to and located quickly, and they can be operated, controlled and resolved directly on the information system. Go to the equipment in person to solve it (reduction of more than 80% of the time), and greatly reduce labor costs (such as 100 test equipment, now monitored by 20 people, through the application of the present invention, only 2 to 3 people can meet).
  • the real-time monitoring and visualization system responds to the abnormal mechanism and processing interface in a timely manner, and realizes the transformation from the current personnel inspection monitoring mode to an unmanned class.
  • AI algorithm fusion analysis and early warning prediction play a vital role in improving test productivity, test yield and test quality.
  • the present invention also provides a machine-readable storage medium on which machine-executable instructions are stored, and the instructions are configured to enable a machine to perform the steps in any one of the methods above.

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Abstract

一种集成电路测试的信息化管理方法、系统及存储介质，该方法包括：提供集成电路测试平台进行集成电路测试产生的测试数据，所述集成电路测试平台是一级以上的集成电路测试平台，每级所述集成电路测试平台包括多个测试仪器(S101)；提供与所述集成电路测试相关、除所述测试数据之外的资源数据(S102)；根据所述集成电路测试的所述测试数据、所述资源数据，对所述集成电路测试进行分析，获得与所述集成电路测试相关的结果数据(S103)。通过这种方式，本方案能够为集成电路测试中产生的测试数据的价值体现提供技术支持。

Description

基于工业互联网的集成电路测试信息化管理系统 技术领域
本发明涉及集成电路测试技术领域，尤其涉及一种集成电路测试的信息化管理方法、集成电路测试的信息化管理系统及机器可读存储介质。
背景技术
最近几年，大数据一直是个非常热门的话题。当前，集成电路测试每天生成各种超过300G的大数据，每月测试2亿多颗芯片，每颗芯片测试参数平均约6000项，每颗芯片测试功能矢量平均约10,000,000条，测试数据还在持续增长中。
但是，本申请的发明人在长期的研发过程中发现，上述集成电路测试产生的测试数据的价值没有得到体现。
发明内容
本发明主要解决的技术问题是提供一种集成电路测试的信息化管理方法、集成电路测试的信息化管理系统及机器可读存储介质，能够为集成电路测试中产生的测试数据的价值体现提供技术支持。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种集成电路测试的信息化管理方法，所述方法包括：提供集成电路测试平台进行集成电路测试产生的测试数据，所述集成电路测试平台是一级以上的集成电路测试平台，每级所述集成电路测试平台包括多个测试仪器；提供与所述集成电路测试相关、除所述测试数据之外的资源数据；根据所述集成电路测试的所述测试数据、所述资源数据，对所述集成电路测试进行分析，获得与所述集成电路测试相关的结果数据。
其中，所述集成电路测试包括设计验证阶段的测试、生产环节的测试中的至少一种；所述设计验证阶段的测试包括晶圆测试；所述生产环节的测试包括晶圆制造阶段的过程工艺测试、晶圆测试以及成品测试中的至少一种。
其中，所述提供集成电路测试平台进行集成电路测试产生的测试数据，包括：获取所述集成电路测试平台进行所述集成电路测试产生的不同格式的 原始测试数据；将所述原始测试数据转换为统一格式的转换测试数据。
其中，所述集成电路测试是晶圆测试，所述测试数据是多种不同类型的测试机产生的，所述测试数据包括每片晶圆的测试数据，所述资源数据包括每片晶圆的测试记录数据，每片所述晶圆的测试记录数据与每片所述晶圆的测试数据相对应；其中，所述资源数据还包括每片晶圆的基本信息数据，每片所述晶圆的基本信息数据与每片所述晶圆的测试数据相对应；其中所述资源数据还包括每片所述晶圆测试时测试探针台的状态记录数据，所述探针台的状态记录数据与每片所述晶圆的测试数据相对应；其中，所述结果数据包括测试产品每片的良率、每天的良率波动情况、关键参数的变化趋势；所述方法还包括：将所述结果数据自动向相关人员进行推送；其中，将所述结果数据自动通过邮件或微信向相关人员进行推送。
其中，所述提供与所述集成电路测试相关、除所述测试数据之外的资源数据，包括：建立、管理并实时更新所述集成电路测试的测试流程；登记并管理所述集成电路测试的测试产品的信息；登记并管理所述集成电路测试的测试仪器的信息；监控并管理所述集成电路测试的任务状态；监控并管理生产环节的测试的信息；对测试产品的测试UID与服务器中的UID进行校验，并实时记录校验结果和测试版本号；对所述集成电路测试的测试产品的晶圆图相关信息进行修改、添加、删除管理；其中，所述集成电路测试是生产环节的测试；所述集成电路测试是生产环节的晶圆测试或成品测试。
其中，所述分析包括测试参数指标分析、测试良率分析、测试时间分析、晶圆Map图信息分析、测试总结检查及分析、探针卡扎针高度分析、结果数据反馈要求分析、测试记录历史信息分析中的至少一个；其中，所述根据所述集成电路测试的所述测试数据、所述资源数据，对所述集成电路测试进行分析，获得与所述集成电路测试相关的结果数据，包括：接收输入的用于查询资源数据的第一相关信息，所述第一相关信息包括测试产品名称、测试仪器、测试批号以及测试机台号；接收输入的用于查询资源数据的第二相关信息，所述第二相关信息包括起始时间和终止时间；接收输入的用于查询资源数据的第三相关信息，所述第三相关信息是晶圆测试或成品测试；接收输入的用于查询资源数据的第四相关信息，所述第三相关信息是查询数据库的数据或本地数据；根据所述第一相关信息、第二相关信息、第三相关信息以及 第四相关信息，读取资料数据的相关文件，并实时显示读取的进度和参数信息；
接收输入的、与实际需求对应的分析功能信息，并显示对应的数据格式；
根据所述分析功能信息，生成分析出来的结果数据；
其中，所述结果数据以文件、报表以及图表中的至少一种形式呈现；
所述方法还包括：
根据所述集成电路测试的所述测试数据、所述资源数据、所述结果数据的反馈要求，对所述集成电路测试进行分析，获得与所述集成电路测试相关的、与所述反馈要求对应的结果数据；将所述结果数据以文件、报表以及图表中的至少一种形式在可视界面显示；其中，所述测试参数指标分析对应的结果数据包括晶圆上每个晶片(die)在晶圆上的X坐标、Y坐标、XY坐标对应的工位、所述XY坐标通过或未通过的结果、测试项通过或未通过的结果，所述测试项的具体测试值；其中，所述测试参数指标分析对应的结果数据是将晶片未通过的值、测试项未通过的值、大于1.5倍测试值的四分位距的值、大于3倍测试值的四分位距的值剔除后得到的；其中，所述测试参数指标分析对应的结果数据以第一图表的形式呈现；其中，所述第一图表包括：正态分布图、散点图、柱状直方图、箱型图、测试项的Map图；其中，所述第一图表的标记类型包括：上限、下限、最大值、最小值、平均值、中位值、标准差、平均值加上3倍标准差、平均值减去3倍标准差、第一四分位数、第三四分位数；其中，数值分析为将数值进行平均值、标准差分析；其中，所述测试良率分析对应的结果数据包括：最终良率、最初良率、复测率、回复率、最终通过数、最初通过数、复测数量、回复数量、测试机编号、针卡编号；其中，所述测试良率分析对应的结果数据以第二图表的形式呈现；其中，所述第二图表包括：整改批良率分析图、探针卡良率分析图、工位良率分析线性图、失效序号分析图、单个工位失效分析图以及多个工位线性图；所述整改批良率分析图是指将不同批测试产品的值用不同颜色显示出来，以供分析测试产品批之间的良率差异；所述探针卡良率分析图是指将不同的测试条件形成测试良率分析图，以供分析不同硬件之间的良率差异；所述工位良率分析线性图是指将不同工位做成线性图表，以供分析工位之间良率差异；所述失效序号分析图是指将所有失效序号的数量从大到小排列，并且将每个 测试结果序号和之前的所有测试结果序号的数量累加，作出累加百分比线，以供分析主要失效是由哪几个测试结果序号造成，以及造成的影响有多大；所述单个工位失效分析图是指取最高数量的三个失效序号做成叠加柱状图，通过每个工位的高度分析工位良率差异；所述多个工位线性图是指取最高数量的三个失效序号做成线性图，以供分析是否由于工位差异造成的未通过数量变大；其中，所述测试时间分析对应的结果数据包括：总测试时间、正常测试时间、复测测试时间、正常测试过程中暂停时间、正常测试总时间、复测过程中暂停时间、复测总时间、复测的第一个晶片时间、测试机编号、针卡编号；所述测试时间分析对应的结果数据以整改批良率分析图的形式呈现，所述整改批良率分析图是指将不同批的值用不同颜色显示出来，以供分析批之间测试时间的差异；其中，所述探针卡扎针高度分析是指显示每个探针卡扎针高度的时间；其中，所述晶圆Map图信息分析包括：所有测试结果序号的分布、复测和回复测试结果序号的分布、通过多种分析算法分析后判断Map图是否异常，能够将多张Map图叠加起来，分析失效序号的分布；其中，所述晶圆Map图信息分析对应的结果数据包括：测试结果序号的数量、测试结果序号的百分比、工位差异个数、工位差异百分比、具体的工位信息；其中，所述晶圆Map图信息分析对应的结果数据以颜色区分回复/复测的形式呈现，所述颜色区分回复/复测能够分析出回复率的高低，判断是否出现明显的花纹图形，以供分析硬件差异，并指导后续测试和提高良率；其中，所述集成电路测试是生产环节的测试；所述集成电路测试是生产环节的晶圆测试或成品测试。
其中，所述方法还包括：基于可视化技术对所述集成电路测试进行远程实时监控；其中，所述基于可视化技术对所述集成电路测试进行远程实时监控，包括：基于可视化技术对所述集成电路测试中的测试探针台、测试机台进行远程实时监控；基于可视化技术对所述集成电路测试中的数据采集、数据处理、数据分析、数据存储进行远程实时监控；基于可视化技术对所述集成电路测试的全过程进行远程实时监控和管理；所述方法还包括：当监控到测试车间出现异常时，发出报警信号；响应所述报警信号，在可视化界面对所述异常进行处理；其中，所述基于可视化技术对测试探针台进行远程实时监控，包括：记录连续不良品数量并进行显示；若记录的连续不良品数量大 于输入的误判阈值，则向所述自动化测试探针台发送停止测试的指令，同时还发送报警指令，指示报警；其中，所述集成电路测试是生产环节的测试；所述集成电路测试是生产环节的晶圆测试或成品测试。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种集成电路测试的信息化管理系统，所述系统包括：处理器、存储器以及通信电路，所述处理器分别耦接所述存储器和所述通信电路，所述系统通过所述通信电路与集成电路测试平台连接，以采集所述集成电路测试平台进行集成电路测试产生的测试数据，其中，所述处理器、所述存储器以及所述通信电路在工作时能够实现如上任一项所述方法中的步骤。
其中，所述系统包括：设备互联和数据源融合子系统，包括处理器、存储器以及通信电路，所述设备互联和数据源融合子系统通过所述通信电路与所述集成电路测试平台连接，所述处理器、存储器以及通信电路在工作时能够实现所述提供集成电路测试平台进行集成电路测试产生的测试数据的步骤；资源管理子系统，包括处理器、存储器以及通信电路，所述处理器、存储器以及通信电路在工作时能够实现提供与所述集成电路测试相关、除所述测试数据之外的资源数据的步骤；数据分析子系统，包括处理器、存储器以及通信电路，所述处理器、存储器以及通信电路在工作时能够实现根据所述集成电路测试的所述测试数据和所述资源数据，对所述集成电路测试进行分析，获得与所述集成电路测试相关的结果数据的步骤；所述设备互联和数据源融合子系统、所述资源管理子系统以及所述数据分析子系统通过各自的通信电路连接。
其中，所述设备互联和数据源融合子系统包括中心服务器、数据预处理服务器以及第一数据库服务器；所述资源管理子系统包括第二数据库服务器；所述数据分析子系统包括分析服务器；所述数据预处理服务器、所述第一数据库服务器、所述第二数据库服务器、所述分析服务器以及所述测试机分别与所述中心服务器连接，所述第二数据库服务器还与所述测试机连接，所述数据预处理服务器还与所述第一数据库服务器连接，所述分析服务器还与所述第一数据库服务器连接；在每片晶圆测试时，向所述第二数据库服务器存入对应的测试记录数据，写入对应的每片所述晶圆的基本信息数据，同时也写入每片所述晶圆测试时测试探针台的状态记录数据；多种不同类型的测试 机产生的原始测试数据存放入所述中心服务器，所述中心服务器根据所述第二数据库服务器中晶圆的测试记录数据分发对应的原始测试数据给所述数据预处理服务器，所述数据预处理服务器对原始测试数据进行预处理，转换为统一格式的转换测试数据，提取关键参数，并将预处理后的数据存入所述第一数据库服务器，预处理结束后，所述中心服务器向所述分析服务器下达分析任务，所述分析任务携带有所述第二数据库服务器存放的、分析时需要用到的资源数据，所述分析服务器根据所述分析任务从所述第一数据库服务器中获取预处理后的数据，分析并生成所述结果数据，将所述结果数据自动通过邮件或微信向相关人员进行推送，以便相关人员实时掌握测试产品每片的良率、每天的良率波动情况、关键参数的变化趋势；其中，所述第一数据库服务器是MongoDB数据库服务器，所述第二数据库服务器是SQL数据库服务器。
其中，所述系统还包括：类无人车间工业级应用子系统，包括处理器、存储器以及通信电路，所述类无人车间工业级应用子系统通过所述通信电路分别与所述集成电路测试平台、所述设备互联和数据源融合子系统、所述资源管理子系统以及所述数据分析子系统连接，所述处理器、存储器以及通信电路在工作时能够实现所述基于可视化技术对所述集成电路测试进行远程实时监控的步骤。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种机器可读存储介质，其上存储有机器可执行指令，所述指令被配置为能使机器执行如上任一项所述方法中的步骤。
本发明的有益效果是：区别于现有技术的情况，本发明的集成电路测试的信息化管理系统和方法，一方面提供集成电路测试平台进行集成电路测试产生的测试数据，另一方面提供与集成电路测试相关、除测试数据之外的资源数据，根据集成电路测试的测试数据、资源数据，对集成电路测试进行分析，获得与集成电路测试相关的结果数据。由于结果数据不仅仅利用测试数据，而且利用资源数据，资源数据是与集成电路测试相关、除测试数据之外所有数据，根据不同的测试需求、测试阶段、测试目的等，能够利用不同的资源数据，结合测试数据，能够进行不同的分析，得到不同的结果数据，根 据不同的结果数据，结合不同的测试需求、测试阶段、测试目的等，能够灵活、有分别地利用测试数据的价值。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本发明集成电路测试的信息化管理方法一实施例的流程示意图；
图2是本发明集成电路测试的信息化管理系统一实施例的结构示意图；
图3是本发明集成电路测试的信息化管理系统另一实施例的结构示意图；
图4是本发明集成电路测试的信息化管理系统又一实施例的结构示意图；
图5是本发明集成电路测试的信息化管理系统又一实施例的结构示意图；
图6是本发明集成电路测试的信息化管理系统又一实施例的结构示意图；
图7是第六步显示参数信息的示意图；
图8是测试参数指标分析中具体数据显示的示意图；
图9是数值分析的示意图；
图10是具体的数据显示的示意图；
图11是Site良率分析线性图的示意图；
图12是Site线性图的示意图；
图13是时间分析中具体数据显示的示意图；
图14是TouchDown分析的示意图；
图15是TskMap具体数据显示的示意图；
图16是Recover/Retest颜色区分的示意图；
图17是SummaryCheck的示意图；
图18是本发明集成电路测试的信息化管理系统又一实施例的结构示意图；
图19是本发明集成电路测试的信息化管理系统又一实施例的结构示意图；
图20是本发明集成电路测试的信息化管理系统又一实施例的结构示意图；
图21是本发明集成电路测试的信息化管理系统又一实施例的结构示意图；
图22是本发明集成电路测试的信息化管理系统又一实施例的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
结合参见图1和图2，图1是本发明集成电路测试的信息化管理方法一实施例的流程示意图，图2是本发明集成电路测试的信息化管理系统一实施例的结构示意图，本发明实施例的信息化管理系统能够实现本发明实施例的信息化管理方法，此处为了描述的方便，将集成电路测试的信息化管理方法和集成电路测试的信息化管理系统结合在一起进行详细说明。
该集成电路测试的信息化管理系统100包括：处理器1、存储器2以及通信电路3，处理器1分别耦接存储器2和通信电路3，该系统100通过通信电路3与集成电路测试平台200连接，以采集集成电路测试平台200进行集成电路测试产生的测试数据，其中，处理器1、存储器2以及通信电路3在工作时能够实现如下任一集成电路测试的信息化管理方法中的步骤。
其中，该集成电路测试的信息化管理方法包括：
步骤S101：提供集成电路测试平台进行集成电路测试产生的测试数据，集成电路测试平台是一级以上的集成电路测试平台，每级集成电路测试平台包括多个测试仪器。
步骤S102：提供与集成电路测试相关、除测试数据之外的资源数据。
步骤S103：根据集成电路测试的测试数据、资源数据，对集成电路测试进行分析，获得与集成电路测试相关的结果数据。
集成电路测试平台的范围能够决定测试数据的大小与多少，能够决定资源数据的的大小与多少。集成电路测试平台的范围根据测试目的、测试阶段、或者利用集成电路测试相关数据所要达到的目的等等有多种不同的划分方法。例如，设计验证阶段(研发阶段)、生产环节阶段；又如：某一家公司对 某个产品的设计验证阶段、某一家公司对多个不同产品的设计验证阶段、多家公司对某个产品的设计验证阶段、多家公司对多个产品的设计验证阶段、某家公司多批产品的生产环节阶段、多家公司多批产品的生产环节阶段，等等。不同的测试目的、测试阶段，或者利用集成电路测试相关数据所要达到的不同目的等等，测试的项目不同，对测试数据、对资源数据的具体要求也不相同。因此，根据不同的测试目的、测试阶段，或者利用集成电路测试相关数据所要达到的不同目的等等，可以选择测试数据和资源数据进行分析，得到需要的结果数据。
测试数据是直接通过测试仪器测试后得出的数据，可以是具体定量的数据(具体的电压值、电流值，等等)，也可以是定性的数据(例如：测试通过与测试未通过，等等)。资源数据是与集成电路测试相关的、不是通过测试仪器直接测试出来的数据，例如：基本信息数据(批号、中转的日期、时间、地点、测试产品UID，等等)，测试流程，测试仪器信息，测试项目，测试参数，测试记录，等等。结果数据是根据测试数据和资源数据，对集成电路测试进行分析得到的。
例如：一堆产品是多个批号混合的产品，经过测试仪器测试后，测试数据是定性的“pass”“fail”，如果仅仅分析测试数据，可以得到这一堆产品中有多少数量的产品“pass”，有多少数量的产品“fail”，还可以得到这一堆产品的通过率和未通过率。如果这一堆产品中每个产品记录有批号(资源数据)，可以进一步分析得到“fail”的产品是某一批号的产品。如果这一批号的产品并不是所有的产品“fail”，同时这一堆产品中每个产品还记录有原材料(资源数据)，可以进一步分析得到“fail”的产品是某一批号原材料的产品。从中可以看出，测试数据结合与测试相关的资源数据，可以得到更加深入的结果数据，更加有助于深挖问题所在，以便有针对性、有效率的解决问题。
需要说明的是，集成电路测试的信息化管理系统100的处理器1、存储器2以及通信电路3在工作时能够实现上述的信息化管理方法中的步骤，但是在实际应用，处理器1、存储器2以及通信电路3的具体部署，需要根据具体的应用来确定，即处理器1、存储器2以及通信电路3的具体部署有很多种，本发明实施例并不限定集成电路测试的信息化管理系统100的具体部署。
结合参见图3，在一实施例中，为了方便集成电路测试的信息化管理系统 100后续的管理及升级要求，将上述的步骤S101、步骤S102以及步骤S103分别对应部署为一个子系统，即每个子系统能够实现一个步骤。具体地，集成电路测试的信息化管理系统100包括：设备互联和数据源融合子系统10、资源管理子系统20以及数据分析子系统30，每个子系统均包括处理器1、存储器2以及通信电路3。
设备互联和数据源融合子系统10通过通信电路3与集成电路测试平台200连接，其处理器1、存储器2以及通信电路3在工作时能够实现步骤S101；资源管理子系统20的处理器1、存储器2以及通信电路3在工作时能够实现步骤S102；数据分析子系统30的处理器1、存储器2以及通信电路3在工作时能够实现步骤S103；设备互联和数据源融合子系统10、资源管理子系统20以及数据分析子系统30根据实际应用需要通过各自的通信电路3连接。
具体地，设备互联和数据源融合子系统10以集成电路测试平台的测试仪器为基础，从其底层出发，采用数据源整合用户界面(UI，User Interface)，整合集成电路测试的复杂多样测试数据；设备互联和数据源融合子系统10通过改进的测试操作界面(OI，Operator Interface)让测试仪器生成原始测试数据，并通过运算及筛选，在云端进行所有的预处理。资源管理子系统20开展资源信息融合、系统功能升级，对测试流程进行管理和自动化实时更新。数据分析子系统30根据测试数据和资源数据，利用集成电路全生态链智能测试分析方法，最终可以得到结果数据，例如研发最终良率、最初良率、复测率、回复率的网格表和可视化、测试时间、晶圆图，等等。
本发明实施例的集成电路测试的信息化管理系统和方法，一方面提供集成电路测试平台进行集成电路测试产生的测试数据，另一方面提供与集成电路测试相关、除测试数据之外的资源数据，根据集成电路测试的测试数据、资源数据，对集成电路测试进行分析，获得与集成电路测试相关的结果数据。由于结果数据不仅仅利用测试数据，而且利用资源数据，资源数据是与集成电路测试相关、除测试数据之外所有数据，根据不同的测试需求、测试阶段、测试目的等，能够利用不同的资源数据，结合测试数据，能够进行不同的分析，得到不同的结果数据，根据不同的结果数据，结合不同的测试需求、测试阶段、测试目的等，能够灵活、有分别地利用测试数据的价值。
其中，集成电路测试包括设计验证阶段的测试、生产环节的测试中的至 少一种；设计验证阶段的测试包括晶圆测试；生产环节的测试包括晶圆制造阶段的过程工艺测试、晶圆测试以及成品测试中的至少一种。
在一实施例中，如果集成电路测试平台产生的原始测试数据的格式各不相同，为方便后续处理，需要对原始测试数据进行预处理，即步骤S101具体可以包括：获取集成电路测试平台进行集成电路测试产生的不同格式的原始测试数据；将原始测试数据转换为统一格式的转换测试数据。如果集成电路测试平台产生的原始测试数据的格式相同且满足分析的数据格式，此步骤可以省略。
其中，集成电路测试是晶圆测试，测试数据是多种不同类型的测试机产生的，测试数据包括每片晶圆的测试数据。当晶圆测试是比较小规模的测试，例如研发验证阶段的晶圆测试，或者对结果数据要求不多的时候，例如生产工艺的测试对结果数据要求不多，资源数据可以是较少的数据，对应的结果数据也不多。例如，在一实施例中，资源数据包括每片晶圆的测试记录数据，每片晶圆的测试记录数据与每片晶圆的测试数据相对应。资源数据还包括每片晶圆的基本信息数据，每片晶圆的基本信息数据与每片晶圆的测试数据相对应。资源数据还包括每片晶圆测试时测试探针台的状态记录数据，探针台的状态记录数据与每片晶圆的测试数据相对应。其中，结果数据包括测试产品每片的良率、每天的良率波动情况、关键参数的变化趋势。进一步，该信息化管理方法还包括：将结果数据自动向相关人员进行推送；其中，将结果数据自动通过邮件或微信向相关人员进行推送。
对应地，上述方法均能够通过集成电路测试的信息化管理系统的三个子系统实现，集成电路测试的信息化管理系统的三个子系统可以进一步具体部署。当晶圆测试是比较小规模的测试，或者对结果数据要求不多的时候，三个子系统可以简单部署。
例如，结合参见图4，在一实施例中，设备互联和数据源融合子系统10包括中心服务器101、数据预处理服务器102以及第一数据库服务器103；资源管理子系统20包括第二数据库服务器201；数据分析子系统30包括分析服务器301；数据预处理服务器102、第一数据库服务器103、第二数据库服务器201、分析服务器301以及测试机2001分别与中心服务器101连接，第二数据库服务器201还与测试机2001连接，数据预处理服务器102还与第一数 据库服务器103连接，分析服务器301还与第一数据库服务器103连接。
在每片晶圆测试时，向第二数据库服务器201存入对应的测试记录数据，写入对应的每片晶圆的基本信息数据，同时也写入每片晶圆测试时测试探针台的状态记录数据；多种不同类型的测试机产生的原始测试数据存放入中心服务器101，中心服务器101根据第二数据库服务器201中晶圆的测试记录数据分发对应的原始测试数据给数据预处理服务器102，数据预处理服务器102对原始测试数据进行预处理，转换为统一格式的转换测试数据，提取关键参数，并将预处理后的数据存入第一数据库服务器103，预处理结束后，中心服务器101向分析服务器301下达分析任务，分析任务携带有第二数据库服务器201存放的、分析时需要用到的资源数据，分析服务器201根据分析任务从第一数据库服务器103中获取预处理后的数据，分析并生成结果数据，将结果数据自动通过邮件或微信向相关人员进行推送，以便相关人员实时掌握测试产品每片的良率、每天的良率波动情况、关键参数的变化趋势。
其中，第一数据库服务器103是MongoDB数据库服务器，第二数据库服务器201是SQL数据库服务器。
具体地，1)原始测试数据包含但不限于原始未处理数据(RawData)及与测试系统无关的标准测试数据格式(STDF，Standard Test Data Format)，在每片晶圆(Wafer)开始测试和结束测试的时候，将必要的Wafer基本信息存入第二数据库服务器201(SQL Server)上，以便中心服务器101查询Wafer测试记录使用；另外，在每片Wafer开始和结束时需要操作界面(OI)在第二数据库服务器201(SQL Server)中写入Wafer的基本信息，包括这片Wafer的产品名、批号、片号、开始测试时间、结束测试时间、使用的测试机、测试探针台(Prober)、探针卡(ProberCard)等，以便在不需要进行详细数据分析的时候对这片Wafer进行快速分析。同时，还需要将测试探针台(Prober)的状态记录到第二数据库服务器201(SQL Server)中，以便对测试环境进行监控。
2)生成测试数据之后，将测试数据存放于中心服务器101，中心服务器101根据第二数据库服务器201(SQL Server)中Wafer的测试记录分发数据处理任务给数据预处理服务器102和分析服务器301，在数据预处理服务器102预处理完数据之后将预处理完的数据存入第一数据库服务器103(MongoDB)中，便于分析服务器103后续生成结果数据的报表。其中，数据预处理服务器102 和分析服务器301可以有多台服务器共同完成，根据数据和分析处理任务的强度动态分配工作负载。第一数据库服务器103(MongoDB)用于记录数据预处理后的数据，是基于分布式文件存储的数据库，介于关系数据库和非关系数据库之间，用于存储所有晶片(Die)的关键参数的值，其在改变关键参数时不需要重新生成表单记录，直接将新的参数作为新的关键参数(key)记入同一张数据库表。
3)在测试数据进行预处理之后，将生成的预处理数据存入第一数据库服务器103(MongoDB)，预处理完的数据包括但不限于晶圆图(WaferMap)、所有Die关键参数的详细数据，数据预处理服务器102由中心服务器101指派数据处理任务，由于不同的产品关注的参数不同，因此，预处理完的数据也不同，通过使用“主控+脚本”(主控是指测试软件界面集成的算法，脚本是另外写的优化程序，不是集成在软件中，可以调用)的形式来处理数据，不同的产品使用不同的处理脚本，在产品处理脚本中将该产品要处理的关键参数列出并提取保存到第一数据库服务器103(MongoDB)中。
4)在预处理数据之后，中心服务器101发送分析任务给分析服务器301，分析服务器301根据中心服务器101分发的分析任务从第一数据库服务器103(MongoDB)中获取预处理后的数据，分析并生成结果数据对应的分析报表，系统最后自动将分析报表通过邮件、微信形式推送给产品相关的工程师及其他用户，以便他们实时掌握被测产品每片的良率、每天的良率波动情况、关键参数的变化趋势。
如果产品增加，只需要增加数据处理脚本或者报表处理脚本即可。如果测试数据增加，现有的数据预处理服务器102无法满足需求时，只需要增加数据预处理服务器102和第一数据库服务器103(MongoDB)的数量，即可完成运算能力的扩充提升，如图5所示。
本发明实施例利用中心服务器、数据预处理服务器、分析服务器、第二数据库服务器(SQL Server)、第一数据库服务器(MongoDB)，为各种国际先进的大型自动化测试仪器组成的多级集成电路测试平台所产生的集成电路测试数据源进行整合，将不同类型测试设备产生的原始测试数据规划为统一格式转换测试数据作为数据源，测试数据格式包含RawData、STDF(Standard Test Data Format)格式的详细数据，在每片Wafer开始测试和结束测试的时候，将 必要的Wafer基本信息存入第二数据库服务器(SQL Server)上，以便中心服务器查询Wafer测试分析报告，并实时推送给用户。
其中，集成电路测试是生产环节的测试；集成电路测试是生产环节的晶圆测试或成品测试；步骤S102具体可以包括：建立、管理并实时更新集成电路测试的测试流程；登记并管理集成电路测试的测试产品的信息；登记并管理集成电路测试的测试仪器的信息；监控并管理集成电路测试的任务状态；监控并管理生产环节的测试的信息；对测试产品的测试UID与服务器中的UID进行校验，并实时记录校验结果和测试版本号；对集成电路测试的测试产品的晶圆图相关信息进行修改、添加、删除管理。
对应地，上述方法可以通过资源管理子系统20实现，根据实际应用的需要，也为了使资源管理子系统20满足灵活多变的需求，资源管理子系统20可以复杂部署，在具体应用的时候，可以选择性使用资源管理子系统20的相关功能和其提供的资源数据。例如，可以将资源管理子系统20划分为几个功能模块，每个功能模块对应实现上述步骤S102中的具体步骤。
具体地，结合参见图6，资源管理子系统20包括：建立测试任务模型模块202、产品信息登记及管理模块203、产品测试仪器信息模块204、测试任务状态监控模块204、测试生产管理模块206、矩阵身份证明编号(DiagUid)校验及管理模块207以及图谱编辑(MAPEDIT)信息管理模块208。
建立测试任务模型模块202，用于建立、管理并实时更新集成电路测试的测试流程；测试产品信息登记及管理模块203，用于登记并管理集成电路测试的测试产品的信息；测试仪器信息模块204，用于登记并管理集成电路测试的测试仪器的信息；测试任务状态监控模块205，用于监控并管理集成电路测试的任务状态；测试生产管理模块206，用于监控并管理生产环节的测试的信息；DiagUid校验及管理模块207，用于对测试产品的测试UID与服务器中的UID进行校验，并实时记录校验结果和测试版本号；MAPEDIT信息管理模块208，用于对集成电路测试的测试产品的晶圆图相关信息进行修改、添加、删除管理。
下面对每个模块的具体功能进行详细阐述：
(1)建立测试任务模型
建立“test(测试)”、“quality(质量)”、“baking(烘干)”、“ink(打点)” 以及设备、配件、测试探针卡、位置等关键流程模型，并可灵活配置和更改，其主要特征在于在产品进入测试之前，生成唯一可溯源性联动ID，ID将成产品唯一贯穿整个测试流程的信息，包括消耗物料、流程、收集的参数化的数据、入出、中转的日期、时间、地点等。
(2)自动获取测试流程
建立测试流程模型，对在线高低温测试、打点、墨水烘干、质量检验、老化等任务状态进行管理，根据“产品名称”调用设置文件，需加工的流程也会调用。
(3)测试产品信息登记
根据测试产品信息及测试要求，预先登记和入库，信息在任何需要调用产品列表的时候都可使用，需要注意的是产品名称是唯一不能重复的，包括测试产品名称、测试仪器(DEVICE)、测试程序及测试探针卡名称等，通过这种方式，能够为全程无纸化提供基础数据，无纸化信息自动获取、跟踪及监控。
(4)产品测试仪器信息管理
测试仪器信息共分“测试探针台(prober)”、“测试台(tester)”、“操作工程师(pe)”三类，任何测试仪器都可成为另外仪器的附属，即在“归属于ID”中填写附属仪器的ID，然后在仪器列表的操作工程师版列表中体现出来。
(5)测试任务状态监控
根据“产品名称”调用设置文件，需要加工测试的流程也被调用，默认的任务书产品数量为来料登记数量，系统支持临时更改、添加、删除，这些信息可在系统中进行自动修改和更新。
同时支持测试任务及测试程序的更新，另外，为了保证产业化测试的安全性，系统添加了安全机制，测试任务标号唯一性，即一个测试任务书标号只能是唯一的测试程序、测试流程及测试仪器信息等。
(6)测试生产管理
即对产品当前测试流程状态进行管理，包括流程卡号、任务书号、来料时间和状态运行时间等，实现测试生产的管理。
(7)DiagUid校验及管理
本模块在整改集成电路测试过程中应用，具有安全性、唯一性及可追溯 性，系统对所测试产品的UID与服务器中的UID信息进行校验，并实时记录测试版本号、校验结果，验证测试流程的正确性。主要校验信息包含测试测试结果序号(bin)合计数、每个工位(site)差异比对、每个工位(site)误测管芯数、每个工位(site)测试管芯数、总测试管芯数等，通过多维度进行校验和验证，保证每次测试的唯一性。
测试算法如下：
判断UID是否符合要求：
Figure PCTCN2019090313-appb-000001
DiagUid校验包含的信息：
Figure PCTCN2019090313-appb-000002
(8)MAPEDIT信息管理及在线自动校验验证
MAPEDIT信息管理主要是对产品每颗测试晶片(die)坐标(X.Y)、通过(PASS)、未通过(FAIL)等超过百项信息进行管理，包含了批号ID(LOT ID)、元件类型(Part Type)、任务名称(Job Name)、测试台类型(Tester Type)、建立时间(Setup Time)、起始时间(Start Time)、操作者姓名(Operator Name)、小批ID(Sublot ID)、测试代码(Test Code)、作业转速(Job Rev)、执行类型(Executive Type)、执行版本(Exec Version)、测试温度(Test Temp)、流ID(Flow ID)等超过百项的信息。同时进行在线自动校验验证。
另外，集成电路晶圆(wafer)测试过程中由于一些不可控原因，如实际测试范围与事先设定的范围不同，操作人员的信息输入与实际有差异、仪器参数异常等一些原因，导致最终的量产测试结果与实际不符。为了避免此类事情发生，须测试系统的详细参数(TestSystemPLUS)在数据上传至数据中心前做一个全面的校验验证，在进行验证前，系统会自动获取测试产品信息，进行相应的规则设置及配置，过程是将客户要求的测试范围通过基本地图(Basic Map，即期望达到理想状态的测试良率分布图)导入系统中、检查测试项目通过综合配线(BDF，Building Distribution Frame)软件模块导入系统， 使用的测试探针卡信息通过探针卡释放(ProberCard Release，即测试探针卡扎针次数，扎针次数会影响测试结果)导入系统中，最终进行信息校验验证。
Figure PCTCN2019090313-appb-000003
系统校验正确后，根据测试要求调度，智能分配、决策，开始测试，整合测试数据集聚区信息，实时监控测试数据，并上传服务器，完成信息化管理。
其中，集成电路测试是生产环节的测试；集成电路测试是生产环节的晶圆测试或成品测试。
本发明实施例的资源管理子系统集成从测试产品入库到出库一整套信息登记和信息管理，功能完备、实用简单、过程可控，可通过安全的在线远程进行访问控制，是一套模块管理、可视化、完善的、标准化的资源管理子系 统，其功能包括测试流程、产品登记、测试程序调用、DEVICE调用、探针卡管理、测试设备、来料登记、下达测试任务、测试流程卡管理、生产进程跟踪、进度查询、产品登记、DiagUid、自动更新、MAPEDIT、Map数据统计、密码修改、测试Map偏移检查等整套集成电路测试信息的登记和管理，方便测试监控、查询、分析及追溯。
其中，分析包括测试参数指标分析、测试良率分析、测试时间分析、晶圆Map图信息分析、测试总结检查及分析、探针卡扎针高度分析、结果数据反馈要求分析、测试记录历史信息分析中的至少一个。
其中，步骤S103具体可以包括：接收输入的用于查询资源数据的第一相关信息，第一相关信息包括测试产品名称、测试仪器、测试批号以及测试机台号；接收输入的用于查询资源数据的第二相关信息，第二相关信息包括起始时间和终止时间；接收输入的用于查询资源数据的第三相关信息，第三相关信息是晶圆测试或成品测试；接收输入的用于查询资源数据的第四相关信息，第三相关信息是查询数据库的数据或本地数据；根据第一相关信息、第二相关信息、第三相关信息以及第四相关信息，读取资料数据的相关文件，并实时显示读取的进度和参数信息；接收输入的、与实际需求对应的分析功能信息，并显示对应的数据格式；根据分析功能信息，生成分析出来的结果数据。其中，结果数据以文件、报表以及图表中的至少一种形式呈现。
该方法还包括：根据集成电路测试的测试数据、资源数据、结果数据的反馈要求，对集成电路测试进行分析，获得与集成电路测试相关的、与反馈要求对应的结果数据；将结果数据以文件、报表以及图表中的至少一种形式在可视界面显示。
其中，测试参数指标分析对应的结果数据包括晶圆上每个晶片(die)在晶圆上的X坐标、Y坐标、XY坐标对应的工位、XY坐标通过或未通过的结果、测试项通过或未通过的结果，测试项的具体测试值。
其中，测试参数指标分析对应的结果数据是将晶片未通过的值、测试项未通过的值、大于1.5倍测试值的四分位距的值、大于3倍测试值的四分位距的值剔除后得到的。
其中，测试参数指标分析对应的结果数据以第一图表的形式呈现。
其中，第一图表包括：正态分布图、散点图、柱状直方图、箱型图、测 试项的Map图；第一图表的标记类型包括：上限、下限、最大值、最小值、平均值、中位值、标准差、平均值加上3倍标准差、平均值减去3倍标准差、第一四分位数、第三四分位数；数值分析为将数值进行平均值、标准差分析。
其中，测试良率分析对应的结果数据包括：最终良率、最初良率、复测率、回复率、最终通过数、最初通过数、复测数量、回复数量、测试机编号、针卡编号；测试良率分析对应的结果数据以第二图表的形式呈现；第二图表包括：整改批良率分析图、探针卡良率分析图、工位良率分析线性图、失效序号分析图、单个工位失效分析图以及多个工位线性图；整改批良率分析图是指将不同批测试产品的值用不同颜色显示出来，以供分析测试产品批之间的良率差异；探针卡良率分析图是指将不同的测试条件形成测试良率分析图，以供分析不同硬件之间的良率差异；工位良率分析线性图是指将不同工位做成线性图表，以供分析工位之间良率差异；失效序号(FailBin)分析图是指将所有失效序号的数量从大到小排列，并且将每个测试结果序号(bin)和之前的所有测试结果序号的数量累加，作出累加百分比线，以供分析主要失效是由哪几个测试结果序号造成，以及造成的影响有多大；单个工位失效分析图是指取最高数量的三个失效序号做成叠加柱状图，通过每个工位的高度分析工位良率差异；多个工位线性图是指取最高数量的三个失效序号做成线性图，以供分析是否由于工位差异造成的未通过数量变大。
其中，测试时间分析对应的结果数据包括：总测试时间、正常测试时间、复测测试时间、正常测试过程中暂停时间、正常测试总时间、复测过程中暂停时间、复测总时间、复测的第一个晶片时间、测试机编号、针卡编号；测试时间分析对应的结果数据以整改批良率分析图的形式呈现，整改批良率分析图是指将不同批的值用不同颜色显示出来，以供分析批之间测试时间的差异。
其中，探针卡扎针高度(TouchDown)分析是指显示每个探针卡扎针高度的时间。
其中，晶圆Map图信息分析包括：所有测试结果序号的分布、复测和回复测试结果序号的分布、通过多种分析算法分析后判断Map图是否异常，能够将多张Map图叠加起来，分析失效序号的分布；晶圆Map图信息分析对应的结果数据包括：测试结果序号的数量、测试结果序号的百分比、工位差异 个数、工位差异百分比、具体的工位信息；晶圆Map图信息分析对应的结果数据以颜色区分回复/复测的形式呈现，颜色区分回复/复测能够分析出回复率的高低，判断是否出现明显的花纹图形，以供分析硬件差异，并指导后续测试和提高良率。
其中，所述集成电路测试是生产环节的测试；所述集成电路测试是生产环节的晶圆测试或成品测试。
对应地，上述方法均能够通过数据分析子系统30实现，集成电路测试的信息化管理系统的数据分析子系统30的具体功能如下：
数据分析子系统30包括：数据采集层、大数据处理分析层以及应用层，数据采集层主要是分别从设备互联和数据源融合子系统10和资源管理子系统20获取测试数据和资源数据，大数据处理分析层主要是对获取的测试数据和资源数据进行分析处理，应用层主要是对分析处理后的结果数据的利用。总的来说，数据分析子系统30提供集成电路测试参数指标分析、晶圆测试良率分析、测试时间分析、晶圆MAP图信息分析、测试总结检查(SummaryCheck)及分析、探针卡扎针高度分析、报告(Report)、测试记录(SQLHistory)分析。
本集成电路测试的信息化管理系统的各个子系统具有数据互通和数据备份的特点，安全性高，数据分析子系统30能实现对全生态链信息的数据检索、追踪和分析的功能，利于后续实时监控测试结果。
在一具体应用中，数据分析子系统30的具体实现流程说明如下：
第一步：在R1里输入产品名称、测试仪器(Device)、测试批号(Lot)、测试机台号(Tester)等信息值，默认为空，即进行全搜索。
第二步：在R3里选择需要的起始时间和终止时间，默认起始时间为工具开启时间往前30天，默认终止时间为工具开启时间。
第三步：在R4里选择晶圆测试(CP)或成品测试(FT)，关系到搜索的数据库位置。
第四步：在R5里选择使用数据库的数据还是本地数据，然后在L1里会显示所有符合条件的信息，最后再根据实际需要选择具体哪些数据需要读取，读取temp文件或者csv文件。主要数据查询途径包括：“SQL Search”为查询SQL数据库里的temp文件；“SQL Read”为读取SQL数据库里的temp文 件；“SQL DC Parameter”为读取SQL数据库里的csv文件；“Local Search”为获取本地盘符里的temp文件；“Local Read”为读取本地盘符里的temp文件；“Local DC Parameter”为读取本地盘符里的csv文件。
第五步：读取中的文件会在R5里显示进度，读取完成后会在R7里显示，实时显示读取的片数和进度。
第六步：如果读取的是CSV文件，会在L1里显示所有的参数信息，具体包括如下全参数信息：
L11：TC为测试总数量；RC为复测数量；WC为测试总数量减去复测数量。
L12：产品名，可以有多个产品名。
L13：指定产品名下的批号名。
L14：指定产品名批号名下的WaferID和FlowID。
L15：产品名的批号统计信息，LC为批号数量，TC为此产品测试总数量；RC为此产品复测数量；WC为此产品测试总数量减去复测数量。
L16：指定批号的统计信息，TC为此批号测试总数量；RC为此批号复测数量；WC为此批号测试总数量减去复测数量。
L17：指定WaferID的测试结束时间。
L18：如图7，表示此为复测的数据。
第七步：选择U1里的特色功能按钮，不同功能会在C1里显示不同的数据格式。主要包括的功能如下：“测试参数指标分析”，主要分析DC参数的具体指标；“良率分析”，主要分析wafer或FT文件的良率信息和具体site、Bin信息；“时间分析”，主要分析wafer或FT文件的测试时间信息和touchdown信息；“TskMap”，主要查看wafer的Map图信息及各种map相关检查功能；“SummaryCheck”，主要查看wafer或FT文件的summary及分析结果；“TouchDown”，主要分析完整的一片wafer的实际touchdown个数和site测试个数；“Report”，主要生成不同客户要求的不同报表；“SQLHistory”，主要查看SQL数据库里的信息，包括CP测试记录、FT测试记录等。
第八步：在U1里根据实际需求选择相应功能，生成新的分析数据。
第九步：选择C1的不同tab，可以微信推送、邮件推送、本地保存等多终端显示。
特色功能具体说明：
(1)测试参数指标分析
数据整合：U311：X、Y、Site、FlowPF为固定列，XY代表其在晶圆上的XY坐标，Site代表此坐标是具体哪个工位测试的，FlowPF代表此坐标的最终结果是pass还是fail。后面列根据所选测试项不同会相应显示出不同数据，一个测试项为两列，第一列为其测试项的pass/fail结果，第二列为测试项的具体测试值。
U312：晶圆上测试了多少die，就有多少行信息。
U313：具体的数据显示，如图8。
实现设定：Remove FlowFail：将此颗die最终结果是fail的值剔除；
Remove ItemFail：将此测试项结果是fail的值剔除；
Remove Outliers：将大于1.5倍测试值的四分位距的值剔除；
Remove ExOutliers：将大于3倍测试值的四分位距的值剔除；
By Site：统计时是否需要分site进行计算；
测试结果超过预先设定值的1.5倍的值属于离线值，测试结果超过预先设定值的3倍的值属于极限离线值；四分位距的值是指统计学中的离散程度，是指将各个变量值按大小顺序排列，然后将此数列分成四等份，所得第三个四分位上的值与第一个四分位上的值的差；测试值的四分位距的值是指将各个测试值按大小顺序排列，然后将此数列分成四等份，所得第三个四分位上的值与第一个四分位上的值的差；差反映中间50％数据的离散程度，其数值越小，说明中间的数据越集中；数值越大，说明中间的数据越分散。
支持的图表类型：
NormalDistribution：正态分布图
ScatterPlot：散点图
BarHistogram：柱状直方图
BoxPlot：箱型图
ValueMap：测试项的Map图
图表标记类型：
HighLimit：上限
LowLimit：下限
Max：最大值
Min：最小值
Mean：平均值
Median：中位值
Sigma：标准差
+3Sigma：平均值加上3倍标准差
-3Sigma：平均值减去3倍标准差
Quartile1：第一四分位数
Quartile3：第三四分位数
“数值分析”为将数值进行平均值、标准差等分析，如图9。
测试参数指标分析的优势：通过将几百甚至几千项的测试参数，转换成直观的可视化图表，同时，可以将任何一个测试参数在一张map图的分布，形成测试值Map，通过颜色变化能清晰看出是否具有区域性和趋势性，能更直观地判断晶圆本身是否存在问题，整张map的测试值分布对于制造晶圆的工厂来说也是非常重要。
(2)测试良率分析
数据整合：U321：列标题为固定参数，包括：FinalYield、FirstYield、RetestYield、RecoverYield、FinalPass、FirstPass、RetestCount、RecoverCount、TesterID、PCID，其分别代表最终良率、最初良率、复测率、回复率、最终pass数、最初pass数、复测数量、回复数量、测试机编号、针卡编号。
U322：选择源数据数量，有多少个数据文件就有多少行。
U323：具体的数据显示，如图10。
支持的图表类型：
整改Lot良率分析图：将不同Lot的值用不同颜色显示出来，可以清晰看出LOT之间的良率差异；
ProberCard良率分析图：根据不同的测试条件形成测试良率分析图，来查看不同硬件之间的良率差异；
Site良率分析线性图：将不同site做成线性图表，直观看出site之间良率差异，如图11；
FailBin分析图：将所有failbin的数量从大到小排列，并且将每个测试结 果序号和之前的所有测试结果序号的数量累加，做条累加百分比线，可以看出主要失效是由哪几个测试结果序号造成的，并且造成的影响有多大。
单个工位失效分析图：取最高数量的三个failbin做成叠加柱状图，通过每个工位的高度直观的看出工位良率差异。
多个工位(Site)线性图：取最高数量的三个failbin做成线性图，看看是否由于工位差异造成的fail数量变大，如图12。
测试良率分析优势：从整改Lot良率、ProberCard影响因素、测试site之间、FailBin因素等多维度去分析测试良率图，从最终良率、最初良率、复测率、回复率，快速统计每个Lot的summary，能清晰看出和分析区域性和趋势性。
(3)时间分析
数据整合：U331：列标题为固定参数，包括TotalTime、NormalTestTime、RetestTestTime、NormalPauseTime、NormalTotalTime、RetestPauseTime、RetestTotalTime、RetestFirstDieTime、TesterID、PCID，其分别代表总测试时间、正常测试时间、复测测试时间、正常测试过程中暂停时间、正常测试总时间、复测过程中暂停时间、复测总时间、复测的第一个die时间、测试机编号、针卡编号。
U332：选择源数据数量，有多少个数据文件就有多少行。
U333：具体的数据显示，如图13。
整改Lot良率分析图：将不同Lot的值用不同颜色显示出来，可以清晰看出LOT之间测试时间差异。
TouchDown分析：TouchDowndetail，显示每个touchdown的时间，如图14。
时间分析优势：通过查看每片的测试时间，能得出每片实际的测试时间。并且针对测试时间长的片子可以通过touchdown去看时间间隔，找到时间变长的原因，从而提高生产效率。
(4)TskMap
主要是分析CP测试的MAP图，包括所有测试结果序号的分布、复测和回复测试结果序号的分布、通过各种算法后判断MAP图是否异常等，还可以将多张map叠加起来，分析失效序号的分布。
数据整合：U351：列标题前4列为固定参数，包括BinCount、BinYield、S2S Count、S2S Yield，其分别代表测试结果序号的数量、测试结果序号的百分比、工位差异个数、工位差异百分比，后面是具体的工位信息，有多少工位就有多少列数据，代表各工位各测试结果序号的数量。
U332：选择源数据数量，有多少个数据文件就有多少行。
U333：具体的数据显示，如图15。
Recover/Retest颜色区分：直观看出回复率的高低，如果有明显的pattern图形，则说明硬件有差异，对后续测试和提高良率进行指导意见，如图16。
“SummaryCheck”，查看测试summary，并根据具体产品的判断规则进行自动判断，快速找出异常数据。
良率判断：通过颜色直观看出问题所在；还可以直接先测试失效或异常的测试数项，如图17。
本实施例数据分析子系统30还具有另外的优势：
(1)系统功能自动更新，为了保证每个人所使用的exe为最新版本，需要对exe版本做个判断，如果低于最新版本就会从服务器上重新下载一个最新的exe可执行文件，可在工具打开后最上方找到其版本号。实现代码如下：
Figure PCTCN2019090313-appb-000004
(2)所有配置文件共享、以配置文件误操作防范：数据分析子系统30聚集有很多配置文件，每个配置文件都有其对应的功能，例如device setting配置了map的范围，yield setting配置了产品的判断规则。如果管理员更新了 配置文件，其他人也应该使用最新的配置文件。在任何对配置文件有操作后可以选择将修改后的配置文件上传到服务器，每次使用配置文件前又会将服务器上的配置文件下到本地使用。另外如果有任何误操作或不确定时，也可以选择不将修改后的配置文件上传，仅更新本地的配置文件，当确认无误后再选择上传服务器，避免误操作使所有人使用的配置文件都被误更新。
Figure PCTCN2019090313-appb-000005
(3)分析核心算法：
以某一个fail为中心，在其周围一圈8个点(左上、上、右上、右、右下、下、左下、左)再找任意一个fail，如果没有即认为9宫格fail数为当前fail总和，如果有继续以任意一个fail再为中心，当然之前那个fail点不能算在其中，一直到周围8个点没有fail为止，如果fail总数大于判断的标准即认为fail，在图上显示出来。
其难点在于判断时需要将之前那个fail去除在外，不能重复计算，因此在循环过程中会有两个列表变量，一个是当前所有统计到的fail列表，另一个是以当前fail为中心的fail列表，动态更新两个列表，保证不重复计算。实现部分关键代码如下：
Figure PCTCN2019090313-appb-000006
Map图横竖连续失效算法具体内容为，以一个fail为中心，先以X轴横向两边寻找fail，连续fail数大于预期则为失效，如果当中有pass，则全部清零；然后以Y轴纵向寻找fail，同X轴。
其难点在于X轴和Y轴需要分别计算，又同时需要将结果合并，所以进行算法时使用两个变量存储X轴和Y轴的值，最后再将合起来的结果放到最终的一个变量中，使用这个变量描出最终结果。实现部分关键代码如下：
Figure PCTCN2019090313-appb-000007
Site连续失效算法具体内容为，以一个fail为中心，找到和它相同的连续的site，判断是否fail，如果连续fail大于预期，则为失效。
其难点在于几乎所有的CP都会进行复测，需要将最终结果替换掉之前的测试结果，但不能改变其测试顺序，然后判断其site是否一致，再判断连续fail的数量，因此先将site分组进行循环判断，使用一个字典将XY坐标作为key，测试顺序作为value，将复测后相同的XY为key的value替换掉，用一个顺序列表将所有pass/fail结果列出，最后通过顺序列表去判断连续失效的数量是否大于预期。实现关键代码如下：
Figure PCTCN2019090313-appb-000008
TD连续失效算法具体内容为，以一个fail为中心，找到和它连续的touchdown，如果touchdown里有一个fail，则累加fail数，一旦大于预期，则为失效。其难点在于判断touchdown是否连续，同样会遇到复测问题，因此也需要将复测后的值替换掉之前的，然后根据时间来分组进行判断，用一个顺序列表将pass/fail连起来，就能判断是否fail连续。实现关键代码如下：
Figure PCTCN2019090313-appb-000009
原始->复测分布图，列出所有复测的die，和之前的BIN号做对比，如果从fail到pass了，则用绿色表示，fail到fail，但是BIN号没变，用黄色表示，BIN号也变了，则用红色表示。其难点在于用可视化图表表现出来，需要将 所有BIN都列出来，将数字填入圆圈之中，并且根据数字大小来相应改变圆圈大小，并且用不同颜色区分。实现部分关键代码如下：
Figure PCTCN2019090313-appb-000010
本发明实施例的数据分析子系统通过研发最终良率、最初良率、复测率、回复率的网格表和可视化、测试时间、测试Map图等在线智能分析模块，具备Wafer Lot Yield summary、Wafer Lot BinMap、Wafer Lot StackMap、Probe/Setting、6sigma、Test time、SummaryCheck、Probe/Setting、Report等多维度的分析功能，通过大数据的分析结果，实现多平台间的互联互通，通过一定的算法提取、拆分、分析、合并等方法，将这些数据转化成简单易懂的文件和图表，让不同领域的人都能快速得到想要的分析结果。
本发明实施例的数据分析子系统能够实现公司办公的实时性、移动性和智能性；具有远程数据互通和远程数据备份的特点，安全性高，通过不断的数据积累，基于6个月到1年的数据积累，数据分析子系统30引入工业大数据分析模型，实现对全生态链测试信息的数据检索、追踪、分析、预警、预判等，指导生产，提升生产效率及测试良率。
在一实施例中，该方法还包括：基于可视化技术对集成电路测试进行远程实时监控。
具体地，基于可视化技术对集成电路测试进行远程实时监控，可以包括：基于可视化技术对集成电路测试中的测试探针台、测试机台进行远程实时监控；基于可视化技术对集成电路测试中的数据采集、数据处理、数据分析、数据存储进行远程实时监控；基于可视化技术对集成电路测试的全过程进行远程实时监控和管理。
该方法还包括：当监控到测试车间出现异常时，发出报警信号；响应报警信号，在可视化界面对异常进行处理。
其中，基于可视化技术对测试探针台进行远程实时监控，具体可以包括：记录连续不良品数量并进行显示；若记录的连续不良品数量大于输入的误判阈值，则向自动化测试探针台发送停止测试的指令，同时还发送报警指令，指示报警。
对应地，上述方法可以通过集成电路测试的信息化管理100中的新增的子系统来实现，在一实施例中，集成电路测试的信息化管理100还包括类无人车间工业级应用子系统40。
结合参见图18，在一实施例中，类无人车间工业级应用子系统40，包括处理器1、存储器2以及通信电路3，类无人车间工业级应用子系统40通过通信电路3分别与集成电路测试平台200、设备互联和数据源融合子系统10、资源管理子系统20以及数据分析子系统30连接，类无人车间工业级应用子系统40的处理器1、存储器2以及通信电路3在工作时能够实现基于可视化技术对集成电路测试进行远程实时监控的步骤。
结合参见图19，在一实施例中，本发明实施例的类无人车间工业级应用子系统40，是一种远程实时监控及可视化系统，具体地，该系统通过无人车间监控系统40对测试车间2002进行监控管理，测试车间2002内包括生产测试设备，无人车间监控系统40包括自动化测试探针台(Prober)远程监控管理平台401、自动化测试机台(Test)远程监控管理平台402、数据实时监控平台403、全过程监控远程管理平台404；测试车间2002异常报警，实时监控和可视化系统及时响应异常机制及处理界面。
结合参见图20，在一实施例中，自动化测试探针台(Prober)远程监控 管理平台401，包括：处理器1、存储器2、通信电路3、误判计数模块4011、输入模块4012、显示模块4013、报警器4014；输入模块4012与存储器2通过通信电路3连接，处理器1通过通信电路3分别与存储器2、误判计数模块4011、报警器4014以及测试探针台2003连接，误判计数模块4011通过通信电路3与显示模块4013连接。输入模块4012用于输入误判阈值，并存入存储器2，误判计数模块4011用于记录连续不良品数量，显示模块4013用于显示连续不良品数量，处理器1用于通过判断误判计数模块记录的连续不良品数量是否大于误判阈值，决定是否向测试探针台2003发送停止测试的指令，处理器1向测试探针台2003发送停止测试的指令的同时，还向报警器4014发送报警指令，指示报警器4014报警。
结合参见图21，在一实施例中，自动化测试机台(Test)远程监控管理平台402，包括：摄像头4021和智能终端4022，所述摄像头4021的内部固定安装有无线通讯器40211，且无线通讯器40211连接服务器4023，服务器4023连接智能终端4022，且智能终端4022的内部固定安装有处理器40221，处理器40221分别连接电源接口40222、USB接口40223、解码器40224、调制解调器40225、控制器40226和A/D转换器40227，A/D转换器40227连接视频采集卡40228，视频采集卡40228连接无线通讯器40229，该自动化测试机台远程监控管理平台402在移动互联网的基础上进行远程监控管理，其中，智能终端4022使用平板。
结合参见图22，在一实施例中，数据实时监控平台403，包括数据采集模块4032、单片机4031、无线通信模块4033、数据处理模块4034、数据分析模块4035、数据存储模块4036，数据采集模块4032与单片机4031相连，单片机4031与无线通信模块4033相连，数据处理模块4034、数据分析模块4035、数据存储模块4036均与单片机4031连接，避免数据监控的空间距离，组网灵活，性能可靠，成本低廉。
全过程监控远程管理平台404，该平台系统由以太网连接的真实物理系统、虚拟信息系统、信息反馈、信息控制、监控管理平台、设计变更、制造变更、数据/信息和数字模型组成，所述监控管理平台基于物联网信息感知层，利用虚拟现实技术，建立车间及生产线对象的三维可视化数字模型进行监控管理工作，贯穿于整个设计、制造和管理，达到真实物理系统和虚拟信息系 统的高度融合。
综上，本发明实施例的信息化管理系统能够提供丰富快速的线上服务，提高测试效率，提升测试产能，将洁净度车间所有状态(包括测试prober、测试机台、测试数据、信息图表化)实时集成在信息化系统上，操作人员只需在工作台上，能实时监控车间里的状态，异常能及时响应、快速定位，直接在信息化系统上操作、控制及解决异常，并不需要亲自到设备旁边解决(减少80％以上时间)，同时大幅度减少人力成本(如100台测试设备，现在由20人监控，通过本发明应用，只需要2到3人就能满足)。通过测试车间异常报警，实时监控和可视化系统及时响应异常机制及处理界面，实现由现在人员巡视监控模式转型升级为类无人车间，异常处理、测试效率等提升30％，提升通过大数据量与AI算法融合分析，预警预判，为测试产能、测试良率及测试质量提升起到至关重要作用。
本发明还提供一种机器可读存储介质，其上存储有机器可执行指令，指令被配置为能使机器执行如上任一项方法中的步骤。
以上仅为本发明的优选实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

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  1. 一种集成电路测试的信息化管理方法，其特征在于，所述方法包括：
    提供集成电路测试平台进行集成电路测试产生的测试数据，所述集成电路测试平台是一级以上的集成电路测试平台，每级所述集成电路测试平台包括多个测试仪器；
    提供与所述集成电路测试相关、除所述测试数据之外的资源数据；
    根据所述集成电路测试的所述测试数据、所述资源数据，对所述集成电路测试进行分析，获得与所述集成电路测试相关的结果数据。
  2. 根据权利要求1所述的方法，其特征在于，所述集成电路测试包括设计验证阶段的测试、生产环节的测试中的至少一种；所述设计验证阶段的测试包括晶圆测试；所述生产环节的测试包括晶圆制造阶段的过程工艺测试、晶圆测试以及成品测试中的至少一种。
  3. 根据权利要求2所述的方法，其特征在于，所述提供集成电路测试平台进行集成电路测试产生的测试数据，包括：
    获取所述集成电路测试平台进行所述集成电路测试产生的不同格式的原始测试数据；
    将所述原始测试数据转换为统一格式的转换测试数据。
  4. 根据权利要求3所述的方法，其特征在于，所述集成电路测试是晶圆测试，所述测试数据是多种不同类型的测试机产生的，所述测试数据包括每片晶圆的测试数据，所述资源数据包括每片晶圆的测试记录数据，每片所述晶圆的测试记录数据与每片所述晶圆的测试数据相对应；
    其中，所述资源数据还包括每片晶圆的基本信息数据，每片所述晶圆的基本信息数据与每片所述晶圆的测试数据相对应；
    其中所述资源数据还包括每片所述晶圆测试时测试探针台的状态记录数据，所述探针台的状态记录数据与每片所述晶圆的测试数据相对应；
    其中，所述结果数据包括测试产品每片的良率、每天的良率波动情况、关键参数的变化趋势；
    所述方法还包括：将所述结果数据自动向相关人员进行推送；其中，将所述结果数据自动通过邮件或微信向相关人员进行推送。
  5. 根据权利要求2所述的方法，其特征在于，所述提供与所述集成电路测试相关、除所述测试数据之外的资源数据，包括：
    建立、管理并实时更新所述集成电路测试的测试流程；
    登记并管理所述集成电路测试的测试产品的信息；
    登记并管理所述集成电路测试的测试仪器的信息；
    监控并管理所述集成电路测试的任务状态；
    监控并管理生产环节的测试的信息；
    对测试产品的测试UID与服务器中的UID进行校验，并实时记录校验结果和测试版本号；
    对所述集成电路测试的测试产品的晶圆图相关信息进行修改、添加、删除管理；
    其中，所述集成电路测试是生产环节的测试；所述集成电路测试是生产环节的晶圆测试或成品测试。
  6. 根据权利要求2所述的方法，其特征在于，所述分析包括测试参数指标分析、测试良率分析、测试时间分析、晶圆Map图信息分析、测试总结检查及分析、探针卡扎针高度(TouchDown)分析、结果数据反馈要求分析、测试记录历史信息分析中的至少一个；
    其中，所述根据所述集成电路测试的所述测试数据、所述资源数据，对所述集成电路测试进行分析，获得与所述集成电路测试相关的结果数据，包括：
    接收输入的用于查询资源数据的第一相关信息，所述第一相关信息包括测试产品名称、测试仪器、测试批号以及测试机台号；
    接收输入的用于查询资源数据的第二相关信息，所述第二相关信息包括起始时间和终止时间；
    接收输入的用于查询资源数据的第三相关信息，所述第三相关信息是晶圆测试或成品测试；
    接收输入的用于查询资源数据的第四相关信息，所述第三相关信息是查询数据库的数据或本地数据；
    根据所述第一相关信息、第二相关信息、第三相关信息以及第四相关信息，读取资料数据的相关文件，并实时显示读取的进度和参数信息；
    接收输入的、与实际需求对应的分析功能信息，并显示对应的数据格式；
    根据所述分析功能信息，生成分析出来的结果数据；
    其中，所述结果数据以文件、报表以及图表中的至少一种形式呈现；
    所述方法还包括：
    根据所述集成电路测试的所述测试数据、所述资源数据、所述结果数据的反馈要求，对所述集成电路测试进行分析，获得与所述集成电路测试相关的、与所述反馈要求对应的结果数据；
    将所述结果数据以文件、报表以及图表中的至少一种形式在可视界面显示；
    其中，所述测试参数指标分析对应的结果数据包括晶圆上每个晶片(die)在晶圆上的X坐标、Y坐标、XY坐标对应的工位、所述XY坐标通过或未通过的结果、测试项通过或未通过的结果，所述测试项的具体测试值；
    其中，所述测试参数指标分析对应的结果数据是将晶片未通过的值、测试项未通过的值、大于1.5倍测试值的四分位距的值、大于3倍测试值的四分位距的值剔除后得到的；
    其中，所述测试参数指标分析对应的结果数据以第一图表的形式呈现；
    其中，所述第一图表包括：正态分布图、散点图、柱状直方图、箱型图、测试项的Map图；
    其中，所述第一图表的标记类型包括：上限、下限、最大值、最小值、平均值、中位值、标准差、平均值加上3倍标准差、平均值减去3倍标准差、第一四分位数、第三四分位数；
    其中，数值分析为将数值进行平均值、标准差分析；
    其中，所述测试良率分析对应的结果数据包括：最终良率、最初良率、复测率、回复率、最终通过数、最初通过数、复测数量、回复数量、测试机编号、针卡编号；
    其中，所述测试良率分析对应的结果数据以第二图表的形式呈现；
    其中，所述第二图表包括：整改批良率分析图、探针卡良率分析图、工位良率分析线性图、失效序号分析图、单个工位失效分析图以及多个工位线性图；所述整改批良率分析图是指将不同批测试产品的值用不同颜色显示出来，以供分析测试产品批之间的良率差异；所述探针卡良率分析图是指将不 同的测试条件形成测试良率分析图，以供分析不同硬件之间的良率差异；所述工位良率分析线性图是指将不同工位做成线性图表，以供分析工位之间良率差异；所述失效序号(FailBin)分析图是指将所有失效序号的数量从大到小排列，并且将每个测试结果序号(bin)和之前的所有测试结果序号的数量累加，作出累加百分比线，以供分析主要失效是由哪几个测试结果序号造成，以及造成的影响有多大；所述单个工位失效分析图是指取最高数量的三个失效序号做成叠加柱状图，通过每个工位的高度分析工位良率差异；所述多个工位线性图是指取最高数量的三个失效序号做成线性图，以供分析是否由于工位差异造成的未通过数量变大；
    其中，所述测试时间分析对应的结果数据包括：总测试时间、正常测试时间、复测测试时间、正常测试过程中暂停时间、正常测试总时间、复测过程中暂停时间、复测总时间、复测的第一个晶片时间、测试机编号、针卡编号；所述测试时间分析对应的结果数据以整改批良率分析图的形式呈现，所述整改批良率分析图是指将不同批的值用不同颜色显示出来，以供分析批之间测试时间的差异；
    其中，所述探针卡扎针高度分析分析是指显示每个探针卡扎针高度的时间；
    其中，所述晶圆Map图信息分析包括：所有测试结果序号的分布、复测和回复测试结果序号的分布、通过多种分析算法分析后判断Map图是否异常，能够将多张Map图叠加起来，分析失效序号的分布；
    其中，所述晶圆Map图信息分析对应的结果数据包括：测试结果序号的数量、测试结果序号的百分比、工位差异个数、工位差异百分比、具体的工位信息；
    其中，所述晶圆Map图信息分析对应的结果数据以颜色区分回复/复测的形式呈现，所述颜色区分回复/复测能够分析出回复率的高低，判断是否出现明显的花纹图形，以供分析硬件差异，并指导后续测试和提高良率；
    其中，所述集成电路测试是生产环节的测试；所述集成电路测试是生产环节的晶圆测试或成品测试。
  7. 根据权利要求2所述的方法，其特征在于，所述方法还包括：基于可视化技术对所述集成电路测试进行远程实时监控；
    其中，所述基于可视化技术对所述集成电路测试进行远程实时监控，包括：
    基于可视化技术对所述集成电路测试中的测试探针台、测试机台进行远程实时监控；
    基于可视化技术对所述集成电路测试中的数据采集、数据处理、数据分析、数据存储进行远程实时监控；
    基于可视化技术对所述集成电路测试的全过程进行远程实时监控和管理；
    所述方法还包括：
    当监控到测试车间出现异常时，发出报警信号；
    响应所述报警信号，在可视化界面对所述异常进行处理；
    其中，所述基于可视化技术对测试探针台进行远程实时监控，包括：
    记录连续不良品数量并进行显示；
    若记录的连续不良品数量大于输入的误判阈值，则向所述自动化测试探针台发送停止测试的指令，同时还发送报警指令，指示报警；
    其中，所述集成电路测试是生产环节的测试；所述集成电路测试是生产环节的晶圆测试或成品测试。
  8. 一种集成电路测试的信息化管理系统，其特征在于，所述系统包括：处理器、存储器以及通信电路，所述处理器分别耦接所述存储器和所述通信电路，所述系统通过所述通信电路与集成电路测试平台连接，以采集所述集成电路测试平台进行集成电路测试产生的测试数据，其中，所述处理器、所述存储器以及所述通信电路在工作时能够实现如权利要求1-7任一项所述方法中的步骤。
  9. 根据权利要求8所述的系统，其特征在于，所述系统包括：
    设备互联和数据源融合子系统，包括处理器、存储器以及通信电路，所述设备互联和数据源融合子系统通过所述通信电路与所述集成电路测试平台连接，所述处理器、存储器以及通信电路在工作时能够实现所述提供集成电路测试平台进行集成电路测试产生的测试数据的步骤；
    资源管理子系统，包括处理器、存储器以及通信电路，所述处理器、存储器以及通信电路在工作时能够实现提供与所述集成电路测试相关、除所述 测试数据之外的资源数据的步骤；
    数据分析子系统，包括处理器、存储器以及通信电路，所述处理器、存储器以及通信电路在工作时能够实现根据所述集成电路测试的所述测试数据和所述资源数据，对所述集成电路测试进行分析，获得与所述集成电路测试相关的结果数据的步骤；
    所述设备互联和数据源融合子系统、所述资源管理子系统以及所述数据分析子系统通过各自的通信电路连接。
  10. 根据权利要求9所述的系统，其特征在于，所述设备互联和数据源融合子系统包括中心服务器、数据预处理服务器以及第一数据库服务器；所述资源管理子系统包括第二数据库服务器；所述数据分析子系统包括分析服务器；所述数据预处理服务器、所述第一数据库服务器、所述第二数据库服务器、所述分析服务器以及所述测试机分别与所述中心服务器连接，所述第二数据库服务器还与所述测试机连接，所述数据预处理服务器还与所述第一数据库服务器连接，所述分析服务器还与所述第一数据库服务器连接；
    在每片晶圆测试时，向所述第二数据库服务器存入对应的测试记录数据，写入对应的每片所述晶圆的基本信息数据，同时也写入每片所述晶圆测试时测试探针台的状态记录数据；多种不同类型的测试机产生的原始测试数据存放入所述中心服务器，所述中心服务器根据所述第二数据库服务器中晶圆的测试记录数据分发对应的原始测试数据给所述数据预处理服务器，所述数据预处理服务器对原始测试数据进行预处理，转换为统一格式的转换测试数据，提取关键参数，并将预处理后的数据存入所述第一数据库服务器，预处理结束后，所述中心服务器向所述分析服务器下达分析任务，所述分析任务携带有所述第二数据库服务器存放的、分析时需要用到的资源数据，所述分析服务器根据所述分析任务从所述第一数据库服务器中获取预处理后的数据，分析并生成所述结果数据，将所述结果数据自动通过邮件或微信向相关人员进行推送，以便相关人员实时掌握测试产品每片的良率、每天的良率波动情况、关键参数的变化趋势；
    其中，所述第一数据库服务器是MongoDB数据库服务器，所述第二数据库服务器是SQL数据库服务器。
  11. 根据权利要求9所述的系统，其特征在于，所述系统还包括：
    类无人车间工业级应用子系统，包括处理器、存储器以及通信电路，所述类无人车间工业级应用子系统通过所述通信电路分别与所述集成电路测试平台、所述设备互联和数据源融合子系统、所述资源管理子系统以及所述数据分析子系统连接，所述处理器、存储器以及通信电路在工作时能够实现所述基于可视化技术对所述集成电路测试进行远程实时监控的步骤。
  12. 一种机器可读存储介质，其上存储有机器可执行指令，其特征在于，所述指令被配置为能使机器执行如权利要求1-7任一项所述方法中的步骤。
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