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WO2019104823A1 - 一种goa电路及液晶面板、显示装置 - Google Patents

一种goa电路及液晶面板、显示装置 Download PDF

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Publication number
WO2019104823A1
WO2019104823A1 PCT/CN2018/070020 CN2018070020W WO2019104823A1 WO 2019104823 A1 WO2019104823 A1 WO 2019104823A1 CN 2018070020 W CN2018070020 W CN 2018070020W WO 2019104823 A1 WO2019104823 A1 WO 2019104823A1
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Prior art keywords
signal
thin film
film transistor
gate
module
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PCT/CN2018/070020
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English (en)
French (fr)
Inventor
龚强
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武汉华星光电技术有限公司
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Priority to US15/749,303 priority Critical patent/US10302985B1/en
Publication of WO2019104823A1 publication Critical patent/WO2019104823A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a GOA (Gate Driver On Array) circuit, a liquid crystal panel, and a display device.
  • GOA Gate Driver On Array
  • the GOA technology utilizes an existing thin film transistor liquid crystal display array process to fabricate a gate line scan driving signal circuit on an array substrate to form a scan driving of the liquid crystal panel.
  • COF Chip On Flex/Film
  • GOA technology not only can greatly save manufacturing costs, but also eliminates the Bonging process of the Gate side COF, which is also extremely beneficial to the production capacity improvement. Therefore, GOA is the key technology for the development of LCD panels in the future.
  • the integrated touch (In-Cell Touch) panel technology has matured and is widely used in high-end mobile phones.
  • the panel since the display refresh time is separated, the panel usually performs the touch scan with the vacant time (ie, the stop time in the touch screen), thereby causing the working state of the GOA circuit of the panel to no longer be used.
  • the vacant time ie, the stop time in the touch screen
  • a GOA optimization circuit is needed, which can overcome the problem that the GOA circuit has insufficient stopping ability in the touch screen, and achieve the purpose of reducing the risk of failure of the GOA circuit level transmission, and the circuit is more stable.
  • the technical problem to be solved by the embodiments of the present invention is to provide a GOA circuit, a liquid crystal panel, and a display device, which can overcome the problem that the GOA circuit has insufficient stopping ability in the touch screen, and achieve the risk of reducing the failure of the GOA circuit level transmission.
  • the purpose is to make the circuit more stable.
  • an embodiment of the present invention provides a GOA circuit including a plurality of cascaded GOA structural units, and each single-level GOA structural unit is corresponding to the display area of the display panel according to the Nth-level GOA structural unit.
  • the Nth stage GOA structure unit includes forward and reverse scans for controlling forward or reverse scanning of the GOA circuit by using a forward DC scan control signal and a reverse DC scan control signal a control module, a node signal control input module for realizing a low potential output of the GOA circuit in a non-working phase, an output control module for controlling a gate drive signal output, a voltage stabilization module for maintaining a first node level, a Q-point pull-down module for pulling down the first node level, a P-point pull-down module for pulling down the second node level, for pulling down the level of the gate drive signal level, and controlling the during the touch screen scanning a gate signal pull-down module of the gate drive signal output of the current stage, for using the first GAS signal and the second GAS signal) to realize all gate drive signal opening work of the GOA circuit
  • GAS module is responsible for the first node and a
  • the voltage stabilizing module includes a first thin film transistor, and a gate of the first thin film transistor is connected to a third GAS signal, and a source is simultaneously connected to the forward and reverse scan control module and the Q point pull-down module, and the drain Connecting the first node; wherein the third GAS signal is a constant voltage high potential VGH signal during the touch screen scanning, and is a constant voltage low potential VGL signal during the stop of the touch screen.
  • the forward and reverse scan control module comprises a second thin film transistor and a third thin film transistor;
  • a gate of the second thin film transistor is connected to a gate driving signal of the N-2th GOA structural unit, a source is connected to the forward DC scan control signal, and a drain is simultaneously connected to the first film of the voltage regulator module. a transistor source and a drain of the third thin film transistor;
  • the gate of the third thin film transistor is connected to the gate driving signal of the N+2 stage GOA structural unit, and the source is connected to the reverse DC scanning control signal.
  • the node signal control input module includes a fourth thin film transistor, a fifth thin film transistor, and a sixth thin film transistor;
  • a gate of the fourth thin film transistor is connected to the forward DC scan control signal, a source is connected to a clock signal of the N+1th GOA structural unit, and a drain is connected to a drain and a drain of the fifth thin film transistor. a gate of the sixth thin film transistor;
  • a gate of the fifth thin film transistor is connected to the reverse DC scan control signal, and a source is connected to a clock signal of the N-1th GOA structural unit;
  • the source of the sixth thin film transistor is connected to the constant voltage high potential VGH signal, and the drain is connected to the second node connected to the Q point pull-down module, the P point pull-down module, the gate signal pull-down module and the GAS signal action module. .
  • the output control module includes a seventh thin film transistor, a gate of the seventh thin film transistor is connected to the first node, a source is connected to a clock signal of the current stage, and a drain is connected to the gate drive signal of the current stage.
  • the Q-point pull-down module includes an eighth thin film transistor, a gate of the eighth thin film transistor is connected to the second node, a source is connected to a constant voltage low potential VGL signal, and a drain is connected to the voltage regulator module. A source of the first thin film transistor is connected to the first node through the first thin film transistor.
  • the P-point pull-down module includes a ninth thin film transistor, and the gate of the ninth thin film transistor is simultaneously connected to the drain of the second thin film transistor and the drain of the third thin film transistor in the forward and reverse scan control module, and the source A constant voltage low potential VGL signal is connected, and a drain is connected to the second node.
  • the gate signal pull-down module includes a tenth thin film transistor, a gate of the tenth thin film transistor is connected to the second node, a source is connected to a constant voltage low potential VGL signal, and a drain is connected to the current gate Pole drive signal.
  • the GAS signal function module includes an eleventh thin film transistor, a twelfth thin film transistor, and a thirteenth thin film transistor; wherein
  • a gate of the eleventh thin film transistor is connected to the first GAS signal, a source is connected to a constant voltage low potential VGL signal, and a drain is connected to the second node;
  • a gate of the twelfth thin film transistor is connected to the first GAS signal and is in short-circuit connection with a source thereof, and a drain is connected to the gate driving signal of the current stage;
  • the gate of the thirteenth thin film transistor is connected to the second GAS signal, the source is connected to the constant voltage low potential VGL signal, and the drain is connected to the gate driving signal of the current stage.
  • an embodiment of the present invention further provides a liquid crystal panel including a GOA circuit, the GOA circuit includes a plurality of cascaded GOA structural units, and each single-level GOA structural unit is displayed according to the Nth-level GOA structural unit.
  • the Nth stage GOA structure unit includes means for controlling the forward or reverse of the GOA circuit by using a forward DC scan control signal and a reverse DC scan control signal a scanned forward and reverse scan control module, a node signal control input module for implementing a low potential output of the GOA circuit in a non-working phase, an output control module for controlling a gate drive signal output, for maintaining a first node level Voltage stabilizing module, Q-point pull-down module for pulling down the first node level, P-point pull-down module for pulling down the second node level, for pulling down the level of the gate driving signal level and in the touch a gate signal pull-down module for controlling the output of the gate drive signal of the current stage during the screen scan, for realizing all gate drives of the GOA circuit by using the first GAS signal and the second GAS signal) a signal opening function and a GAS signal function module for controlling the output of the gate driving signal of the stage during the scanning of the
  • the voltage stabilizing module includes a first thin film transistor, and a gate of the first thin film transistor is connected to a third GAS signal, and a source is simultaneously connected to the forward and reverse scan control module and the Q point pull-down module, and the drain Connecting the first node; wherein the third GAS signal is a constant voltage high potential VGH signal during the touch screen scanning, and is a constant voltage low potential VGL signal during the stop of the touch screen.
  • the forward and reverse scan control module comprises a second thin film transistor and a third thin film transistor;
  • a gate of the second thin film transistor is connected to a gate driving signal of the N-2th GOA structural unit, a source is connected to the forward DC scan control signal, and a drain is simultaneously connected to the first film of the voltage regulator module. a transistor source and a drain of the third thin film transistor;
  • the gate of the third thin film transistor is connected to the gate driving signal of the N+2 stage GOA structural unit, and the source is connected to the reverse DC scanning control signal.
  • the node signal control input module includes a fourth thin film transistor, a fifth thin film transistor, and a sixth thin film transistor;
  • a gate of the fourth thin film transistor is connected to the forward DC scan control signal, a source is connected to a clock signal of the N+1th GOA structural unit, and a drain is connected to a drain and a drain of the fifth thin film transistor. a gate of the sixth thin film transistor;
  • a gate of the fifth thin film transistor is connected to the reverse DC scan control signal, and a source is connected to a clock signal of the N-1th GOA structural unit;
  • the source of the sixth thin film transistor is connected to the constant voltage high potential VGH signal, and the drain is connected to the second node connected to the Q point pull-down module, the P point pull-down module, the gate signal pull-down module and the GAS signal action module. .
  • the output control module includes a seventh thin film transistor, a gate of the seventh thin film transistor is connected to the first node, a source is connected to a clock signal of the current stage, and a drain is connected to the gate driving signal of the current stage.
  • the Q-point pull-down module includes an eighth thin film transistor, a gate of the eighth thin film transistor is connected to the second node, a source is connected to a constant voltage low potential VGL signal, and a drain is connected to the voltage regulator module. A source of the first thin film transistor is connected to the first node through the first thin film transistor.
  • the P-point pull-down module includes a ninth thin film transistor, and the gate of the ninth thin film transistor is simultaneously connected to the drain of the second thin film transistor and the drain of the third thin film transistor in the forward and reverse scan control module, and the source A constant voltage low potential VGL signal is connected, and a drain is connected to the second node.
  • the gate signal pull-down module includes a tenth thin film transistor, a gate of the tenth thin film transistor is connected to the second node, a source is connected to a constant voltage low potential VGL signal, and a drain is connected to the current gate Pole drive signal.
  • the GAS signal function module includes an eleventh thin film transistor, a twelfth thin film transistor, and a thirteenth thin film transistor; wherein
  • a gate of the eleventh thin film transistor is connected to the first GAS signal, a source is connected to a constant voltage low potential VGL signal, and a drain is connected to the second node;
  • a gate of the twelfth thin film transistor is connected to the first GAS signal and is in short-circuit connection with a source thereof, and a drain is connected to the gate driving signal of the current stage;
  • the gate of the thirteenth thin film transistor is connected to the second GAS signal, the source is connected to the constant voltage low potential VGL signal, and the drain is connected to the gate driving signal of the current stage.
  • the embodiment of the present invention further provides a display device, including a liquid crystal panel, where the liquid crystal panel includes a GOA circuit;
  • the GOA circuit includes a plurality of cascaded GOA structural units, each of which outputs a line scan signal to a corresponding row of pixel units in a display area of the display panel according to the Nth stage GOA structural unit;
  • the stage GOA structural unit includes a forward and reverse scan control module for controlling forward or reverse scanning of the GOA circuit by using a forward DC scan control signal and a reverse DC scan control signal for implementing a non-working phase of the GOA circuit a low-potential output node signal control input module, an output control module for controlling the gate drive signal output, a voltage stabilization module for maintaining the first node level, and a Q-point pull-down for pulling down the first node level a module, a P-point pull-down module for pulling down the second node level, a gate signal pull-down module for pulling down the level of the gate drive signal level, and controlling the output of the gate drive signal during the touch screen scan Implementing all gate driving signal opening functions of the GOA circuit by using the first GAS signal and the second G
  • the voltage stabilizing module includes a first thin film transistor, and a gate of the first thin film transistor is connected to a third GAS signal, and a source is simultaneously connected to the forward and reverse scan control module and the Q point pull-down module, and the drain Connecting the first node; wherein the third GAS signal is a constant voltage high potential VGH signal during the touch screen scanning, and is a constant voltage low potential VGL signal during the stop of the touch screen.
  • the forward and reverse scan control module comprises a second thin film transistor and a third thin film transistor;
  • a gate of the second thin film transistor is connected to a gate driving signal of the N-2th GOA structural unit, a source is connected to the forward DC scan control signal, and a drain is simultaneously connected to the first film of the voltage regulator module. a transistor source and a drain of the third thin film transistor;
  • the gate of the third thin film transistor is connected to the gate driving signal of the N+2 stage GOA structural unit, and the source is connected to the reverse DC scanning control signal.
  • the node signal control input module includes a fourth thin film transistor, a fifth thin film transistor, and a sixth thin film transistor;
  • a gate of the fourth thin film transistor is connected to the forward DC scan control signal, a source is connected to a clock signal of the N+1th GOA structural unit, and a drain is connected to a drain and a drain of the fifth thin film transistor. a gate of the sixth thin film transistor;
  • a gate of the fifth thin film transistor is connected to the reverse DC scan control signal, and a source is connected to a clock signal of the N-1th GOA structural unit;
  • the source of the sixth thin film transistor is connected to the constant voltage high potential VGH signal, and the drain is connected to the second node connected to the Q point pull-down module, the P point pull-down module, the gate signal pull-down module and the GAS signal action module. .
  • the output control module includes a seventh thin film transistor, a gate of the seventh thin film transistor is connected to the first node, a source is connected to a clock signal of the current stage, and a drain is connected to the gate drive signal of the current stage.
  • the gate access signal of the first thin film transistor NT1 on the voltage stabilizing module of each single-stage GOA structural unit is set to a constant voltage high potential VGH during the touch screen scanning in the GOA circuit.
  • the third GAS signal of the constant voltage low potential VGL is stopped during the stop of the touch screen, so that the voltage regulator module can be prevented from being turned on during the stop of the touch screen, and the Q point potential of the first node is prevented from leaking to the constant point along the Q point pulldown module.
  • FIG. 1 is a circuit diagram of a single-stage GOA structural unit in a GOA circuit according to Embodiment 1 of the present invention
  • FIG. 2 is a timing diagram of a voltage-stabilizing module connected to a constant-voltage high-potential VGH signal in a single-stage GOA structural unit in a GOA circuit according to Embodiment 1 of the present invention
  • FIG. 3 is a timing diagram of a single-stage GOA structural unit in a GOA circuit according to Embodiment 1 of the present invention.
  • a GOA circuit including a plurality of cascaded GOA structural units, each of which has a corresponding row of pixels in a display area of the display panel according to the Nth-level GOA structural unit.
  • the unit outputs a line scan signal, which is described in detail in the Nth stage GOA structural unit for convenience of description, and N is a positive integer.
  • the Nth-level GOA structural unit includes:
  • a forward-reverse scan control module 1 for controlling forward or reverse scanning of a GOA circuit by using a forward DC scan control signal U2D and a reverse DC scan control signal D2U;
  • a node signal control input module 2 for implementing a low potential output of a non-working phase of a GOA circuit
  • An output control module 3 for controlling gate drive signal output
  • a voltage stabilizing module 4 for maintaining a first node Q (N) level
  • a Q-point pull-down module 5 for pulling down the first node Q(N) level
  • P point pulldown module 6 for pulling down the second node P(N) level
  • a gate signal pull-down module 7 for pulling down the level of the gate drive signal G(N) level and controlling the output of the gate drive signal G(N) of the stage during the touch screen scanning;
  • the GAS signal function module 8 for realizing all the gate drive signal opening functions of the GOA circuit and controlling the output of the gate drive signal G(N) of the current stage during the touch screen scanning by using the first GAS signal GAS1 and the second GAS signal GAS2; as well as
  • a bootstrap capacitor 9 for being responsible for the secondary rise of the first node Q(N) level.
  • the forward and reverse scan control module 1 includes a second thin film transistor NT2 and a third thin film transistor NT3.
  • the gate of the second thin film transistor NT2 is connected to the gate drive signal G of the N-2th GOA structural unit (N- 2)
  • the source is connected to the forward DC scan control signal U2D, and the drain is simultaneously connected to the drain of the first thin film transistor NT1 and the drain of the third thin film transistor NT3 in the voltage stabilizing module 4; the gate connection of the third thin film transistor NT3
  • the gate drive signal G(N+2) of the N+2th GOA structural unit is connected to the reverse DC scan control signal D2U.
  • the node signal control input module 2 includes a fourth thin film transistor NT4, a fifth thin film transistor NT5, and a sixth thin film transistor NT6.
  • the gate of the fourth thin film transistor NT4 is connected to the forward DC scan control signal U2D, and the source is connected.
  • the clock signal CK(N+1) of the N+1th GOA structural unit is connected, the drain is connected to the drain of the fifth thin film transistor NT5 and the gate of the sixth thin film transistor NT6; and the gate of the fifth thin film transistor NT5 is connected.
  • the reverse DC scan control signal D2U the source is connected to the clock signal CK(N-1) of the N-1th GOA structural unit; the source of the sixth thin film transistor NT6 is connected to the constant voltage high potential VGH signal, and the drain connection
  • the second node P(N) is connected to the Q point pull-down module 5, the P point pull-down module 6, the gate signal pull-down module 7, and the GAS signal action module 8.
  • the output control module 3 includes a seventh thin film transistor NT7.
  • the gate of the seventh thin film transistor NT7 is connected to the first node Q(N), the source is connected to the clock signal CK(N) of the current stage, and the drain is connected to the gate of the current stage. Drive signal G(N).
  • the voltage stabilizing module 4 includes a first thin film transistor NT1, and the gate of the first thin film transistor NT1 is connected to the third GAS signal GAS3, and the source is simultaneously connected to the forward and reverse scan control module 1 and the Q point pull-down module 5, and the drain Connect the first node (Q(N).
  • the Q-point pull-down module 5 includes an eighth thin film transistor NT8.
  • the gate of the eighth thin film transistor NT8 is connected to the second node P(N), the source is connected to the constant voltage low potential VGL signal, and the drain is connected to the voltage stabilizing module 4.
  • the source of the first thin film transistor NT1 is connected to the first node Q(N) through the first thin film transistor NT1.
  • the P-point pull-down module 6 includes a ninth thin film transistor NT9.
  • the gate of the ninth thin film transistor NT9 is simultaneously connected to the drain of the second thin film transistor NT2 and the drain of the third thin film transistor NT3 in the forward and reverse scan control module 1.
  • the constant voltage low potential VGL signal is connected, and the drain is connected to the second node P(N).
  • the gate signal pull-down module 7 includes a tenth thin film transistor NT10, the gate of the tenth thin film transistor NT10 is connected to the second node P(N), the source is connected to the constant voltage low potential VGL signal, and the drain is connected to the current level. Gate drive signal G(N).
  • the GAS signal function module 8 includes an eleventh thin film transistor NT11, a twelfth thin film transistor NT12, and a thirteenth thin film transistor NT13.
  • the gate of the eleventh thin film transistor NT11 is connected to the first GAS signal GAS1, the source.
  • the constant voltage low potential VGL signal is connected, and the drain is connected to the second node P(N); the gate of the twelfth thin film transistor NT12 is connected to the first GAS signal GAS1 and is short-circuited with the source thereof, and the drain is connected to the present
  • the bootstrap capacitor 9 includes a first capacitor C1. One end of the first capacitor C1 is connected to the constant voltage low potential VGL signal, and the other end is connected to the source of the first thin film transistor NT1 of the voltage regulator module 4 and passes through the first thin film transistor. NT1 is connected to the first node Q(N) to achieve a secondary rise of the potential of the first node Q(N).
  • the inventor found that if the third GAS signal GAS3 connected to the gate of the first thin film transistor NT1 in the voltage stabilizing module 4 is always maintained as a constant voltage high potential VGH signal, the voltage regulator module 4 is once in the touch screen.
  • the gate of the first thin film transistor NT1 is always at a high potential and is continuously turned on, so that the charge of the first node Q(N) leaks along the source of the first thin film transistor NT1 and the seventh thin film transistor NT7 of the Q-point pull-down module 5.
  • a low potential forward DC scan control signal U2D or reverse DC scan control signal D2U To the constant voltage low potential VGL signal or along the first thin film transistor NT1 source and the forward and reverse scan control module 1 is a low potential forward DC scan control signal U2D or reverse DC scan control signal D2U, so that the touch screen After the end of the stop, the potential of the first node Q(N) is low enough to completely turn on the seventh thin film transistor NT7 in the output control module 3, thereby causing an abnormality in the GOA structural unit of the present stage, but failing to completely open the next-level GOA structure.
  • Figure 2 for the specific timing diagram.
  • both the forward DC scan control signal U2D and the reverse DC scan control signal D2U are different at the same time, and the leakage path of the first node Q(N) needs to be scanned according to the forward and reverse directions.
  • the control module 1 scans the direction to determine, for example, the positive DC scan control signal U2D is high and the reverse DC scan control signal D2U is low, so that the first node Q(N) leaks to the reverse DC scan control. On the signal D2U, the leakage is forwarded to the DC scan control signal U2D.
  • the inventor has the gate of the first thin film transistor NT1 in the voltage stabilizing module 4.
  • the third GAS signal GAS3 is improved, so that the third GAS signal GAS3 is a constant voltage high potential VGH signal during the touch screen scanning, and is a constant voltage low potential VGL signal during the stop of the touch screen, so that Turning off the opening of the first thin film transistor NT1 in the voltage stabilizing module 4 during the stop of the touch screen prevents the charge leakage of the first node Q(N). See FIG. 3 for a specific timing chart.
  • the thin film transistors of the GOA structural unit all adopt N-type thin film transistors, and the level of the constant voltage high potential VGH signal is 10V, and the level of the constant voltage low potential VGL signal is -7V, forward direct current.
  • the scan control signal U2D is at a high potential, the level is 10V, and when the forward DC scan control signal U2D is at a low level, the level is -7V.
  • the reverse DC scan control signal D2U is low, the level is -7V, and when the reverse DC scan control signal D2U is high, the level is 10V.
  • the second embodiment of the present invention provides a liquid crystal panel, which includes the GOA circuit of the first embodiment of the present invention, and has the same structure and connection relationship with the GOA circuit of the first embodiment of the present invention.
  • a liquid crystal panel which includes the GOA circuit of the first embodiment of the present invention, and has the same structure and connection relationship with the GOA circuit of the first embodiment of the present invention.
  • the third embodiment of the present invention further provides a display device comprising the liquid crystal panel of the second embodiment of the present invention, which has the same structure and the liquid crystal panel of the second embodiment of the present invention.
  • a display device comprising the liquid crystal panel of the second embodiment of the present invention, which has the same structure and the liquid crystal panel of the second embodiment of the present invention.
  • the gate access signal of the first thin film transistor NT1 on the voltage stabilizing module of each single-stage GOA structural unit is set to a constant voltage high potential VGH during the touch screen scanning in the GOA circuit.
  • the third GAS signal of the constant voltage low potential VGL is stopped during the stop of the touch screen, so that the voltage regulator module can be prevented from being turned on during the stop of the touch screen, and the Q point potential of the first node is prevented from leaking to the constant point along the Q point pulldown module.

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Abstract

一种GOA电路，包括多个级联的GOA结构单元，每一个单级GOA结构单元均依照第N级GOA结构单元向显示面板的显示区域内相应的一行像素单元输出行扫描信号；第N级GOA结构单元包括正反向扫描控制模块（1）、节点信号控制输入模块（2）、输出控制模块（3）、稳压模块（4）、Q点下拉模块（5）、P点下拉模块（6）、栅极信号下拉模块（7）、GAS信号作用模块（8）和自举电容（9）；稳压模块（4）的第一薄膜晶体管（NT1）栅极接入第三GAS信号（GAS3），源极连接正反向扫描控制模块（1）及Q点下拉模块（5），漏极连接第一节点（Q（N））；第三GAS信号（GAS3）在触控屏扫描期间为VGH信号，在中停期间为VGL信号，能克服GOA电路在触控屏中停时保持能力不足的问题，达到降低GOA电路级传失效风险的目的，使电路更稳定。

Description

一种GOA电路及液晶面板、显示装置
本申请要求于2017年11月28日提交中国专利局、申请号为201711217027.6、发明名称为“一种GOA电路及液晶面板、显示装置”的中国专利申请的优先权，上述专利的全部内容通过引用结合在本申请中。
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种GOA(Gate Driver On Array，阵列基板行驱动)电路及液晶面板、显示装置。
背景技术
GOA技术利用现有薄膜晶体管液晶显示器阵列制程将栅极行扫描驱动信号电路制作在阵列基板上，形成对液晶面板的扫描驱动。GOA技术相比传统COF(Chip On Flex/Film，覆晶薄膜)技术，不仅可以大幅度节约制造成本，而且省去了Gate侧COF的Bonging制程，对产能提升也是极为有利的。因此，GOA是未来液晶面板发展的重点技术。
随着低温多晶硅(LTPS)半导体薄膜晶体管的发展，而且由于LTPS半导体本身超高载流子迁移率的特性，相应的面板周边集成电路也成为大家关注的焦点，并且很多人投入到系统面板(SOP)的相关技术研究，并逐步成为现实。
目前因集成触控(In-Cell Touch)面板技术发展成熟而在高端手机上得到广泛应用。在集成触控面板中，由于显示刷新的时间被分隔开，导致面板通常会以空出时间(即触控屏中停时间)做触控扫描，从而造成面板的GOA电路的工作状态不再连续，出现每扫描一定的级数并保持一段时间后，再继 续扫描的现象。然而，在GOA电路处于保持状态时，很容易出现电路维持能力不足的问题，使GOA电路级传失效，出现显示异常。
因此，亟需一种GOA优化电路，能克服该GOA电路在触控屏中停时保持能力不足的问题，达到降低该GOA电路级传失效风险的目的，使电路更稳定。
发明内容
本发明实施例所要解决的技术问题在于，提供一种GOA电路及液晶面板、显示装置，能克服GOA电路在触控屏中停时保持能力不足的问题，达到降低该GOA电路级传失效风险的目的，使电路更稳定。
为了解决上述技术问题，本发明实施例提供了一种GOA电路，包括多个级联的GOA结构单元，每一个单级GOA结构单元均依照第N级GOA结构单元向显示面板的显示区域内相应的一行像素单元输出行扫描信号；所述第N级GOA结构单元包括用于利用正向直流扫描控制信号和反向直流扫描控制信号控制所述GOA电路正向或反向扫描的正反向扫描控制模块、用于实现所述GOA电路非工作阶段低电位输出的节点信号控制输入模块、用于控制栅极驱动信号输出的输出控制模块、用于维持第一节点电平的稳压模块、用于下拉所述第一节点电平的Q点下拉模块、用于下拉第二节点电平的P点下拉模块、用于下拉本级栅极驱动信号电平及在触控屏扫描期间控制所述本级栅极驱动信号输出的栅极信号下拉模块、用于利用第一GAS信号和第二GAS信号)实现所述GOA电路所有栅极驱动信号打开功能及在所述触控屏扫描期间控制本级栅极驱动信号输出的GAS信号作用模块)和用于负责所述第一节点电平二次抬升的自举电容，且N为正整数；其中，
所述稳压模块包括第一薄膜晶体管，且所述第一薄膜晶体管的栅极接入第三GAS信号，源极同时连接所述正反向扫描控制模块及所述Q点下拉模块，漏极连接所述第一节点；其中，所述第三GAS信号在所述触控屏扫描 期间为恒压高电位VGH信号，并在所述触控屏中停期间为恒压低电位VGL信号。
其中，所述正反向扫描控制模块包括第二薄膜晶体管和第三薄膜晶体管；其中，
所述第二薄膜晶体管的栅极连接第N-2级GOA结构单元的栅极驱动信号，源极接入所述正向直流扫描控制信号，漏极同时连接所述稳压模块中第一薄膜晶体管源极及所述第三薄膜晶体管的漏极；
所述第三薄膜晶体管的栅极连接第N+2级GOA结构单元的栅极驱动信号，源极接入所述反向直流扫描控制信号。
其中，所述节点信号控制输入模块包括第四薄膜晶体管、第五薄膜晶体管和第六薄膜晶体管；其中，
所述第四薄膜晶体管的栅极接入所述正向直流扫描控制信号，源极接入第N+1级GOA结构单元的时钟信号，漏极连接所述第五薄膜晶体管的漏极和所述第六薄膜晶体管的栅极；
所述第五薄膜晶体管的栅极接入所述反向直流扫描控制信号，源极接入第N-1级GOA结构单元的时钟信号；
所述第六薄膜晶体管的源极接入恒压高电位VGH信号，漏极连接与所述Q点下拉模块、P点下拉模块、栅极信号下拉模块及GAS信号作用模块均相连的第二节点。
其中，所述输出控制模块包括第七薄膜晶体管，所述第七薄膜晶体管的栅极连接所述第一节点，源极接入本级时钟信号，漏极连接所述本级栅极驱动信号。
其中，所述Q点下拉模块包括第八薄膜晶体管，所述第八薄膜晶体管的栅极连接所述第二节点，源极接入恒压低电位VGL信号，漏极连接所述稳压模块中第一薄膜晶体管源极并通过所述第一薄膜晶体管与所述第一节点相连。
其中，所述P点下拉模块包括第九薄膜晶体管，所述第九薄膜晶体管的栅极同时连接所述正反向扫描控制模块中第二薄膜晶体管漏极和第三薄膜晶体管漏极，源极接入恒压低电位VGL信号，漏极连接所述第二节点。
其中，所述栅极信号下拉模块包括第十薄膜晶体管，所述第十薄膜晶体管的栅极连接所述第二节点，源极接入恒压低电位VGL信号，漏极连接所述本级栅极驱动信号。
其中，所述GAS信号作用模块包括第十一薄膜晶体管、第十二薄膜晶体管和第十三薄膜晶体管；其中，
所述第十一薄膜晶体管的栅极接入所述第一GAS信号，源极接入恒压低电位VGL信号，漏极接入所述第二节点；
所述第十二薄膜晶体管的栅极接入所述第一GAS信号并与其源极短接连通，漏极接入所述本级栅极驱动信号；
所述第十三薄膜晶体管的栅极接入所述第二GAS信号，源极接入恒压低电位VGL信号，漏极接入所述本级栅极驱动信号。
相应的，本发明实施例还提供了一种液晶面板，包括GOA电路，所述GOA电路包括多个级联的GOA结构单元，每一个单级GOA结构单元均依照第N级GOA结构单元向显示面板的显示区域内相应的一行像素单元输出行扫描信号；所述第N级GOA结构单元包括用于利用正向直流扫描控制信号和反向直流扫描控制信号控制所述GOA电路正向或反向扫描的正反向扫描控制模块、用于实现所述GOA电路非工作阶段低电位输出的节点信号控制输入模块、用于控制栅极驱动信号输出的输出控制模块、用于维持第一节点电平的稳压模块、用于下拉所述第一节点电平的Q点下拉模块、用于下拉第二节点电平的P点下拉模块、用于下拉本级栅极驱动信号电平及在触控屏扫描期间控制所述本级栅极驱动信号输出的栅极信号下拉模块、用于利用第一GAS信号和第二GAS信号)实现所述GOA电路所有栅极驱动信号打开功能及在所述触控屏扫描期间控制本级栅极驱动信号输出的GAS信号作用 模块)和用于负责所述第一节点电平二次抬升的自举电容，且N为正整数；其中，
所述稳压模块包括第一薄膜晶体管，且所述第一薄膜晶体管的栅极接入第三GAS信号，源极同时连接所述正反向扫描控制模块及所述Q点下拉模块，漏极连接所述第一节点；其中，所述第三GAS信号在所述触控屏扫描期间为恒压高电位VGH信号，并在所述触控屏中停期间为恒压低电位VGL信号。
其中，所述正反向扫描控制模块包括第二薄膜晶体管和第三薄膜晶体管；其中，
所述第二薄膜晶体管的栅极连接第N-2级GOA结构单元的栅极驱动信号，源极接入所述正向直流扫描控制信号，漏极同时连接所述稳压模块中第一薄膜晶体管源极及所述第三薄膜晶体管的漏极；
所述第三薄膜晶体管的栅极连接第N+2级GOA结构单元的栅极驱动信号，源极接入所述反向直流扫描控制信号。
其中，所述节点信号控制输入模块包括第四薄膜晶体管、第五薄膜晶体管和第六薄膜晶体管；其中，
所述第四薄膜晶体管的栅极接入所述正向直流扫描控制信号，源极接入第N+1级GOA结构单元的时钟信号，漏极连接所述第五薄膜晶体管的漏极和所述第六薄膜晶体管的栅极；
所述第五薄膜晶体管的栅极接入所述反向直流扫描控制信号，源极接入第N-1级GOA结构单元的时钟信号；
所述第六薄膜晶体管的源极接入恒压高电位VGH信号，漏极连接与所述Q点下拉模块、P点下拉模块、栅极信号下拉模块及GAS信号作用模块均相连的第二节点。
其中，所述输出控制模块包括第七薄膜晶体管，所述第七薄膜晶体管的栅极连接所述第一节点，源极接入本级时钟信号，漏极连接所述本级栅极驱 动信号。
其中，所述Q点下拉模块包括第八薄膜晶体管，所述第八薄膜晶体管的栅极连接所述第二节点，源极接入恒压低电位VGL信号，漏极连接所述稳压模块中第一薄膜晶体管源极并通过所述第一薄膜晶体管与所述第一节点相连。
其中，所述P点下拉模块包括第九薄膜晶体管，所述第九薄膜晶体管的栅极同时连接所述正反向扫描控制模块中第二薄膜晶体管漏极和第三薄膜晶体管漏极，源极接入恒压低电位VGL信号，漏极连接所述第二节点。
其中，所述栅极信号下拉模块包括第十薄膜晶体管，所述第十薄膜晶体管的栅极连接所述第二节点，源极接入恒压低电位VGL信号，漏极连接所述本级栅极驱动信号。
其中，所述GAS信号作用模块包括第十一薄膜晶体管、第十二薄膜晶体管和第十三薄膜晶体管；其中，
所述第十一薄膜晶体管的栅极接入所述第一GAS信号，源极接入恒压低电位VGL信号，漏极接入所述第二节点；
所述第十二薄膜晶体管的栅极接入所述第一GAS信号并与其源极短接连通，漏极接入所述本级栅极驱动信号；
所述第十三薄膜晶体管的栅极接入所述第二GAS信号，源极接入恒压低电位VGL信号，漏极接入所述本级栅极驱动信号。
相应的，本发明实施例又提供了一种显示装置，包括液晶面板，所述液晶面板包括GOA电路；其中，
所述GOA电路包括多个级联的GOA结构单元，每一个单级GOA结构单元均依照第N级GOA结构单元向显示面板的显示区域内相应的一行像素单元输出行扫描信号；所述第N级GOA结构单元包括用于利用正向直流扫描控制信号和反向直流扫描控制信号控制所述GOA电路正向或反向扫描的正反向扫描控制模块、用于实现所述GOA电路非工作阶段低电位输出的节 点信号控制输入模块、用于控制栅极驱动信号输出的输出控制模块、用于维持第一节点电平的稳压模块、用于下拉所述第一节点电平的Q点下拉模块、用于下拉第二节点电平的P点下拉模块、用于下拉本级栅极驱动信号电平及在触控屏扫描期间控制所述本级栅极驱动信号输出的栅极信号下拉模块、用于利用第一GAS信号和第二GAS信号)实现所述GOA电路所有栅极驱动信号打开功能及在所述触控屏扫描期间控制本级栅极驱动信号输出的GAS信号作用模块)和用于负责所述第一节点电平二次抬升的自举电容，且N为正整数；其中，
所述稳压模块包括第一薄膜晶体管，且所述第一薄膜晶体管的栅极接入第三GAS信号，源极同时连接所述正反向扫描控制模块及所述Q点下拉模块，漏极连接所述第一节点；其中，所述第三GAS信号在所述触控屏扫描期间为恒压高电位VGH信号，并在所述触控屏中停期间为恒压低电位VGL信号。
其中，所述正反向扫描控制模块包括第二薄膜晶体管和第三薄膜晶体管；其中，
所述第二薄膜晶体管的栅极连接第N-2级GOA结构单元的栅极驱动信号，源极接入所述正向直流扫描控制信号，漏极同时连接所述稳压模块中第一薄膜晶体管源极及所述第三薄膜晶体管的漏极；
所述第三薄膜晶体管的栅极连接第N+2级GOA结构单元的栅极驱动信号，源极接入所述反向直流扫描控制信号。
其中，所述节点信号控制输入模块包括第四薄膜晶体管、第五薄膜晶体管和第六薄膜晶体管；其中，
所述第四薄膜晶体管的栅极接入所述正向直流扫描控制信号，源极接入第N+1级GOA结构单元的时钟信号，漏极连接所述第五薄膜晶体管的漏极和所述第六薄膜晶体管的栅极；
所述第五薄膜晶体管的栅极接入所述反向直流扫描控制信号，源极接入 第N-1级GOA结构单元的时钟信号；
所述第六薄膜晶体管的源极接入恒压高电位VGH信号，漏极连接与所述Q点下拉模块、P点下拉模块、栅极信号下拉模块及GAS信号作用模块均相连的第二节点。
其中，所述输出控制模块包括第七薄膜晶体管，所述第七薄膜晶体管的栅极连接所述第一节点，源极接入本级时钟信号，漏极连接所述本级栅极驱动信号。
在本发明实施例中，通过在GOA电路中将每一个单级GOA结构单元的稳压模块上第一薄膜晶体管NT1的栅极接入信号设置为在触控屏扫描期间为恒压高电位VGH并在触控屏中停期间为恒压低电位VGL的第三GAS信号，这样可以在触控屏中停期间避免稳压模块开启，阻止第一节点Q点电位沿Q点下拉模块漏电至恒压低电位VGL信号或沿正反向扫描控制模块漏电至相应的低电位直流扫描控制信号，从而确保触控屏中停结束后输出控制模块能够正常开启并能完全打开下一级GOA结构单元，从而能克服GOA电路在触控屏中停时保持能力不足的问题，达到降低该GOA电路级传失效风险的目的，使电路更稳定。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，根据这些附图获得其他的附图仍属于本发明的范畴。
图1为本发明实施例一提供的GOA电路中单级GOA结构单元的电路图；
图2为本发明实施例一提供的GOA电路中单级GOA结构单元中稳压 模块接入恒压高电位VGH信号的时序图；
图3为本发明实施例一提供的GOA电路中单级GOA结构单元的时序图。
具体实施方式
下面参考附图对本发明的优选实施例进行描述。
在本发明实施例一中，提供一种GOA电路，包括多个级联的GOA结构单元，每一个单级GOA结构单元均依照第N级GOA结构单元向显示面板的显示区域内相应的一行像素单元输出行扫描信号，为了叙述方便，以第N级GOA结构单元进行详细说明，且N为正整数。
如图1所示，第N级GOA结构单元包括：
用于利用正向直流扫描控制信号U2D和反向直流扫描控制信号D2U控制GOA电路正向或反向扫描的正反向扫描控制模块1；
用于实现GOA电路非工作阶段低电位输出的节点信号控制输入模块2；
用于控制栅极驱动信号输出的输出控制模块3；
用于维持第一节点Q(N)电平的稳压模块4；
用于下拉第一节点Q(N)电平的Q点下拉模块5；
用于下拉第二节点P(N)电平的P点下拉模块6；
用于下拉本级栅极驱动信号G(N)电平及在触控屏扫描期间控制本级栅极驱动信号G(N)输出的栅极信号下拉模块7；
用于利用第一GAS信号GAS1和第二GAS信号GAS2实现GOA电路所有栅极驱动信号打开功能及在触控屏扫描期间控制本级栅极驱动信号G(N)输出的GAS信号作用模块8；以及
用于负责第一节点Q(N)电平二次抬升的自举电容9。
其中，正反向扫描控制模块1包括第二薄膜晶体管NT2和第三薄膜晶体管NT3；其中，第二薄膜晶体管NT2的栅极连接第N-2级GOA结构单元 的栅极驱动信号G(N-2)，源极接入正向直流扫描控制信号U2D，漏极同时连接稳压模块4中第一薄膜晶体管NT1源极及第三薄膜晶体管NT3的漏极；第三薄膜晶体管NT3的栅极连接第N+2级GOA结构单元的栅极驱动信号G(N+2)，源极接入反向直流扫描控制信号D2U。
其中，节点信号控制输入模块2包括第四薄膜晶体管NT4、第五薄膜晶体管NT5和第六薄膜晶体管NT6；其中，第四薄膜晶体管NT4的栅极接入正向直流扫描控制信号U2D，源极接入第N+1级GOA结构单元的时钟信号CK(N+1)，漏极连接第五薄膜晶体管NT5的漏极和第六薄膜晶体管NT6的栅极；第五薄膜晶体管NT5的栅极接入反向直流扫描控制信号D2U，源极接入第N-1级GOA结构单元的时钟信号CK(N-1)；第六薄膜晶体管NT6的源极接入恒压高电位VGH信号，漏极连接与Q点下拉模块5、P点下拉模块6、栅极信号下拉模块7及GAS信号作用模块8均相连的第二节点P(N)。
其中，输出控制模块3包括第七薄膜晶体管NT7，第七薄膜晶体管NT7的栅极连接第一节点Q(N)，源极接入本级时钟信号CK(N)，漏极连接本级栅极驱动信号G(N)。
其中，稳压模块4包括第一薄膜晶体管NT1，且第一薄膜晶体管NT1的栅极接入第三GAS信号GAS3，源极同时连接正反向扫描控制模块1及Q点下拉模块5，漏极连接第一节点(Q(N)。
其中，Q点下拉模块5包括第八薄膜晶体管NT8，第八薄膜晶体管NT8的栅极连接第二节点P(N)，源极接入恒压低电位VGL信号，漏极连接稳压模块4中第一薄膜晶体管NT1源极并通过第一薄膜晶体管NT1与第一节点Q(N)相连。
其中，P点下拉模块6包括第九薄膜晶体管NT9，第九薄膜晶体管NT9的栅极同时连接正反向扫描控制模块1中第二薄膜晶体管NT2漏极和第三薄膜晶体管NT3漏极，源极接入恒压低电位VGL信号，漏极连接第二节点P(N)。
其中，栅极信号下拉模块7包括第十薄膜晶体管NT10，第十薄膜晶体管NT10的栅极连接第二节点P(N)，源极接入恒压低电位VGL信号，漏极连接所述本级栅极驱动信号G(N)。
其中，GAS信号作用模块8包括第十一薄膜晶体管NT11、第十二薄膜晶体管NT12和第十三薄膜晶体管NT13；其中，第十一薄膜晶体管NT11的栅极接入第一GAS信号GAS1，源极接入恒压低电位VGL信号，漏极接入第二节点P(N)；第十二薄膜晶体管NT12的栅极接入第一GAS信号GAS1并与其源极短接连通，漏极接入本级栅极驱动信号G(N)；第十三薄膜晶体管NT13的栅极接入第二GAS信号GAS2，源极接入恒压低电位VGL信号，漏极接入本级栅极驱动信号G(N)。
其中，自举电容9包括第一电容C1，第一电容C1的一端接入入恒压低电位VGL信号，另一端连接稳压模块4中第一薄膜晶体管NT1的源极并通过第一薄膜晶体管NT1与第一节点Q(N)相连，实现第一节点Q(N)电位的二次抬升。
经过试验发明人发现，稳压模块4中第一薄膜晶体管NT1栅极接入的第三GAS信号GAS3如果一直保持为恒压高电位VGH信号，则一旦处于触摸屏中停期间，因稳压模块4中第一薄膜晶体管NT1栅极一直处于高电位而持续导通，使得第一节点Q(N)的电荷会沿着第一薄膜晶体管NT1源极及Q点下拉模块5中第七薄膜晶体管NT7漏电至恒压低电位VGL信号上或沿着第一薄膜晶体管NT1源极及正反向扫描控制模块1中为低电位的正向直流扫描控制信号U2D或反向直流扫描控制信号D2U上，使得触摸屏中停结束后，第一节点Q(N)的电位较低不足以完全开启输出控制模块3中第七薄膜晶体管NT7，从而导致本级GOA结构单元出现异常，却无法完全打开下一级GOA结构单元，具体的时序图请参见图2。应当说明的是，正向直流扫描控制信号U2D和反向直流扫描控制信号D2U二者的电位在同一时刻上是相异的，而第一节点Q(N)的漏电路径需要根据正反向扫描控制模 块1扫描方向来确定，如正扫时，正向直流扫描控制信号U2D为高电位和反向直流扫描控制信号D2U为低电位，使得第一节点Q(N)漏电至反向直流扫描控制信号D2U上，反之则漏电正向直流扫描控制信号U2D上。
为了克服GOA电路在触控屏中停时保持能力不足的问题，达到降低该GOA电路级传失效风险的目的，使电路更稳定，因此发明人对稳压模块4中第一薄膜晶体管NT1栅极接入的第三GAS信号GAS3进行了改进，使得第三GAS信号GAS3在触控屏扫描期间为恒压高电位VGH信号，在触控屏中停期间为恒压低电位VGL信号，这样就可以在触摸屏中停期间截止稳压模块4中第一薄膜晶体管NT1的开启，避免第一节点Q(N)的电荷漏电，具体的时序图请参见图3。
在本发明实施例一中，GOA结构单元的薄膜晶体管均采用N型薄膜晶体管，且恒压高电位VGH信号的电平为10V，恒压低电位VGL信号的电平为-7V，正向直流扫描控制信号U2D为高电位时，电平为10V，正向直流扫描控制信号U2D为低电位时，电平为-7V。同理，反向直流扫描控制信号D2U为低电位时，电平为-7V，反向直流扫描控制信号D2U为高电位时，电平为10V。
相应于本发明实施例一的GOA电路，本发明实施例二提供了一种液晶面板，包括本发明实施例一的GOA电路，与本发明实施例一的GOA电路具有相同的结构和连接关系，具体请参见本发明实施例一中的相关内容，在此不再一一赘述。
相应于本发明实施例二的液晶面板，本发明实施例三又提供了一种显示装置，包括本发明实施例二中的液晶面板，与本发明实施例二中的液晶面板具有相同的结构和连接关系，具体请参见本发明实施例二中的相关内容，在此不再一一赘述。
实施本发明实施例，具有如下有益效果：
在本发明实施例中，通过在GOA电路中将每一个单级GOA结构单元 的稳压模块上第一薄膜晶体管NT1的栅极接入信号设置为在触控屏扫描期间为恒压高电位VGH并在触控屏中停期间为恒压低电位VGL的第三GAS信号，这样可以在触控屏中停期间避免稳压模块开启，阻止第一节点Q点电位沿Q点下拉模块漏电至恒压低电位VGL信号或沿正反向扫描控制模块漏电至相应的低电位直流扫描控制信号，从而确保触控屏中停结束后输出控制模块能够正常开启并能完全打开下一级GOA结构单元，从而能克服GOA电路在触控屏中停时保持能力不足的问题，达到降低该GOA电路级传失效风险的目的，使电路更稳定。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (20)

  1. 一种GOA电路，其中，包括多个级联的GOA结构单元，每一个单级GOA结构单元均依照第N级GOA结构单元向显示面板的显示区域内相应的一行像素单元输出行扫描信号；所述第N级GOA结构单元包括用于利用正向直流扫描控制信号(U2D)和反向直流扫描控制信号(D2U)控制所述GOA电路正向或反向扫描的正反向扫描控制模块(1)、用于实现所述GOA电路非工作阶段低电位输出的节点信号控制输入模块(2)、用于控制栅极驱动信号输出的输出控制模块(3)、用于维持第一节点(Q(N))电平的稳压模块(4)、用于下拉所述第一节点(Q(N))电平的Q点下拉模块(5)、用于下拉第二节点(P(N))电平的P点下拉模块(6)、用于下拉本级栅极驱动信号(G(N))电平及在触控屏扫描期间控制所述本级栅极驱动信号(G(N))输出的栅极信号下拉模块(7)、用于利用第一GAS信号(GAS1)和第二GAS信号(GAS2)实现所述GOA电路所有栅极驱动信号打开功能及在所述触控屏扫描期间控制本级栅极驱动信号(G(N))输出的GAS信号作用模块(8)和用于负责所述第一节点(Q(N))电平二次抬升的自举电容(9)，且N为正整数；其中，
    所述稳压模块(4)包括第一薄膜晶体管(NT1)，且所述第一薄膜晶体管(NT1)的栅极接入第三GAS信号(GAS3)，源极同时连接所述正反向扫描控制模块(1)及所述Q点下拉模块(5)，漏极连接所述第一节点(Q(N))；其中，所述第三GAS信号(GAS3)在所述触控屏扫描期间为恒压高电位VGH信号，并在所述触控屏中停期间为恒压低电位VGL信号。
  2. 如权利要求1所述的GOA电路，其中，所述正反向扫描控制模块(1)包括第二薄膜晶体管(NT2)和第三薄膜晶体管(NT3)；其中，
    所述第二薄膜晶体管(NT2)的栅极连接第N-2级GOA结构单元的栅极驱动信号(G(N-2))，源极接入所述正向直流扫描控制信号(U2D)，漏 极同时连接所述稳压模块(4)中第一薄膜晶体管(NT1)源极及所述第三薄膜晶体管(NT3)的漏极；
    所述第三薄膜晶体管(NT3)的栅极连接第N+2级GOA结构单元的栅极驱动信号(G(N+2))，源极接入所述反向直流扫描控制信号(D2U)。
  3. 如权利要求2所述的GOA电路，其中，所述节点信号控制输入模块(2)包括第四薄膜晶体管(NT4)、第五薄膜晶体管(NT5)和第六薄膜晶体管(NT6)；其中，
    所述第四薄膜晶体管(NT4)的栅极接入所述正向直流扫描控制信号(U2D)，源极接入第N+1级GOA结构单元的时钟信号(CK(N+1))，漏极连接所述第五薄膜晶体管(NT5)的漏极和所述第六薄膜晶体管(NT6)的栅极；
    所述第五薄膜晶体管(NT5)的栅极接入所述反向直流扫描控制信号(D2U)，源极接入第N-1级GOA结构单元的时钟信号(CK(N-1))；
    所述第六薄膜晶体管(NT6)的源极接入恒压高电位VGH信号，漏极连接与所述Q点下拉模块(5)、P点下拉模块(6)、栅极信号下拉模块(7)及GAS信号作用模块(8)均相连的第二节点(P(N))。
  4. 如权利要求3所述的GOA电路，其中，所述输出控制模块(3)包括第七薄膜晶体管(NT7)，所述第七薄膜晶体管(NT7)的栅极连接所述第一节点(Q(N))，源极接入本级时钟信号(CK(N))，漏极连接所述本级栅极驱动信号(G(N))。
  5. 如权利要求4所述的GOA电路，其中，所述Q点下拉模块(5)包括第八薄膜晶体管(NT8)，所述第八薄膜晶体管(NT8)的栅极连接所述第二节点(P(N))，源极接入恒压低电位VGL信号，漏极连接所述稳压模块(4)中第一薄膜晶体管(NT1)源极并通过所述第一薄膜晶体管(NT1)与所述第一节点(Q(N))相连。
  6. 如权利要求5所述的GOA电路，其中，所述P点下拉模块(6)包 括第九薄膜晶体管(NT9)，所述第九薄膜晶体管(NT9)的栅极同时连接所述正反向扫描控制模块(1)中第二薄膜晶体管(NT2)漏极和第三薄膜晶体管(NT3)漏极，源极接入恒压低电位VGL信号，漏极连接所述第二节点(P(N))。
  7. 如权利要求6所述的GOA电路，其中，所述栅极信号下拉模块(7)包括第十薄膜晶体管(NT10)，所述第十薄膜晶体管(NT10)的栅极连接所述第二节点(P(N))，源极接入恒压低电位VGL信号，漏极连接所述本级栅极驱动信号(G(N))。
  8. 如权利要求7所述的GOA电路，其中，所述GAS信号作用模块(8)包括第十一薄膜晶体管(NT11)、第十二薄膜晶体管(NT12)和第十三薄膜晶体管(NT13)；其中，
    所述第十一薄膜晶体管(NT11)的栅极接入所述第一GAS信号(GAS1)，源极接入恒压低电位VGL信号，漏极接入所述第二节点(P(N))；
    所述第十二薄膜晶体管(NT12)的栅极接入所述第一GAS信号(GAS1)并与其源极短接连通，漏极接入所述本级栅极驱动信号(G(N))；
    所述第十三薄膜晶体管(NT13)的栅极接入所述第二GAS信号(GAS2)，源极接入恒压低电位VGL信号，漏极接入所述本级栅极驱动信号(G(N))。
  9. 一种液晶面板，其中，包括GOA电路，所述GOA电路包括多个级联的GOA结构单元，每一个单级GOA结构单元均依照第N级GOA结构单元向显示面板的显示区域内相应的一行像素单元输出行扫描信号；所述第N级GOA结构单元包括用于利用正向直流扫描控制信号(U2D)和反向直流扫描控制信号(D2U)控制所述GOA电路正向或反向扫描的正反向扫描控制模块(1)、用于实现所述GOA电路非工作阶段低电位输出的节点信号控制输入模块(2)、用于控制栅极驱动信号输出的输出控制模块(3)、用于维持第一节点(Q(N))电平的稳压模块(4)、用于下拉所述第一节点(Q(N))电平的Q点下拉模块(5)、用于下拉第二节点(P(N))电平的P点下拉模 块(6)、用于下拉本级栅极驱动信号(G(N))电平及在触控屏扫描期间控制所述本级栅极驱动信号(G(N))输出的栅极信号下拉模块(7)、用于利用第一GAS信号(GAS1)和第二GAS信号(GAS2)实现所述GOA电路所有栅极驱动信号打开功能及在所述触控屏扫描期间控制本级栅极驱动信号(G(N))输出的GAS信号作用模块(8)和用于负责所述第一节点(Q(N))电平二次抬升的自举电容(9)，且N为正整数；其中，
    所述稳压模块(4)包括第一薄膜晶体管(NT1)，且所述第一薄膜晶体管(NT1)的栅极接入第三GAS信号(GAS3)，源极同时连接所述正反向扫描控制模块(1)及所述Q点下拉模块(5)，漏极连接所述第一节点(Q(N))；其中，所述第三GAS信号(GAS3)在所述触控屏扫描期间为恒压高电位VGH信号，并在所述触控屏中停期间为恒压低电位VGL信号。
  10. 如权利要求9所述的液晶面板，其中，所述正反向扫描控制模块(1)包括第二薄膜晶体管(NT2)和第三薄膜晶体管(NT3)；其中，
    所述第二薄膜晶体管(NT2)的栅极连接第N-2级GOA结构单元的栅极驱动信号(G(N-2))，源极接入所述正向直流扫描控制信号(U2D)，漏极同时连接所述稳压模块(4)中第一薄膜晶体管(NT1)源极及所述第三薄膜晶体管(NT3)的漏极；
    所述第三薄膜晶体管(NT3)的栅极连接第N+2级GOA结构单元的栅极驱动信号(G(N+2))，源极接入所述反向直流扫描控制信号(D2U)。
  11. 如权利要求10所述的液晶面板，其中，所述节点信号控制输入模块(2)包括第四薄膜晶体管(NT4)、第五薄膜晶体管(NT5)和第六薄膜晶体管(NT6)；其中，
    所述第四薄膜晶体管(NT4)的栅极接入所述正向直流扫描控制信号(U2D)，源极接入第N+1级GOA结构单元的时钟信号(CK(N+1))，漏极连接所述第五薄膜晶体管(NT5)的漏极和所述第六薄膜晶体管(NT6)的栅极；
    所述第五薄膜晶体管(NT5)的栅极接入所述反向直流扫描控制信号(D2U)，源极接入第N-1级GOA结构单元的时钟信号(CK(N-1))；
    所述第六薄膜晶体管(NT6)的源极接入恒压高电位VGH信号，漏极连接与所述Q点下拉模块(5)、P点下拉模块(6)、栅极信号下拉模块(7)及GAS信号作用模块(8)均相连的第二节点(P(N))。
  12. 如权利要求11所述的液晶面板，其中，所述输出控制模块(3)包括第七薄膜晶体管(NT7)，所述第七薄膜晶体管(NT7)的栅极连接所述第一节点(Q(N))，源极接入本级时钟信号(CK(N))，漏极连接所述本级栅极驱动信号(G(N))。
  13. 如权利要求12所述的液晶面板，其中，所述Q点下拉模块(5)包括第八薄膜晶体管(NT8)，所述第八薄膜晶体管(NT8)的栅极连接所述第二节点(P(N))，源极接入恒压低电位VGL信号，漏极连接所述稳压模块(4)中第一薄膜晶体管(NT1)源极并通过所述第一薄膜晶体管(NT1)与所述第一节点(Q(N))相连。
  14. 如权利要求13所述的液晶面板，其中，所述P点下拉模块(6)包括第九薄膜晶体管(NT9)，所述第九薄膜晶体管(NT9)的栅极同时连接所述正反向扫描控制模块(1)中第二薄膜晶体管(NT2)漏极和第三薄膜晶体管(NT3)漏极，源极接入恒压低电位VGL信号，漏极连接所述第二节点(P(N))。
  15. 如权利要求14所述的液晶面板，其中，所述栅极信号下拉模块(7)包括第十薄膜晶体管(NT10)，所述第十薄膜晶体管(NT10)的栅极连接所述第二节点(P(N))，源极接入恒压低电位VGL信号，漏极连接所述本级栅极驱动信号(G(N))。
  16. 如权利要求15所述的液晶面板，其中，所述GAS信号作用模块(8)包括第十一薄膜晶体管(NT11)、第十二薄膜晶体管(NT12)和第十三薄膜晶体管(NT13)；其中，
    所述第十一薄膜晶体管(NT11)的栅极接入所述第一GAS信号(GAS1)，源极接入恒压低电位VGL信号，漏极接入所述第二节点(P(N))；
    所述第十二薄膜晶体管(NT12)的栅极接入所述第一GAS信号(GAS1)并与其源极短接连通，漏极接入所述本级栅极驱动信号(G(N))；
    所述第十三薄膜晶体管(NT13)的栅极接入所述第二GAS信号(GAS2)，源极接入恒压低电位VGL信号，漏极接入所述本级栅极驱动信号(G(N))。。
  17. 一种显示装置，其中，包括液晶面板，所述液晶面板包括GOA电路；其中，
    所述GOA电路包括多个级联的GOA结构单元，每一个单级GOA结构单元均依照第N级GOA结构单元向显示面板的显示区域内相应的一行像素单元输出行扫描信号；所述第N级GOA结构单元包括用于利用正向直流扫描控制信号(U2D)和反向直流扫描控制信号(D2U)控制所述GOA电路正向或反向扫描的正反向扫描控制模块(1)、用于实现所述GOA电路非工作阶段低电位输出的节点信号控制输入模块(2)、用于控制栅极驱动信号输出的输出控制模块(3)、用于维持第一节点(Q(N))电平的稳压模块(4)、用于下拉所述第一节点(Q(N))电平的Q点下拉模块(5)、用于下拉第二节点(P(N))电平的P点下拉模块(6)、用于下拉本级栅极驱动信号(G(N))电平及在触控屏扫描期间控制所述本级栅极驱动信号(G(N))输出的栅极信号下拉模块(7)、用于利用第一GAS信号(GAS1)和第二GAS信号(GAS2)实现所述GOA电路所有栅极驱动信号打开功能及在所述触控屏扫描期间控制本级栅极驱动信号(G(N))输出的GAS信号作用模块(8)和用于负责所述第一节点(Q(N))电平二次抬升的自举电容(9)，且N为正整数；其中，
    所述稳压模块(4)包括第一薄膜晶体管(NT1)，且所述第一薄膜晶体管(NT1)的栅极接入第三GAS信号(GAS3)，源极同时连接所述正反向扫描控制模块(1)及所述Q点下拉模块(5)，漏极连接所述第一节点(Q (N))；其中，所述第三GAS信号(GAS3)在所述触控屏扫描期间为恒压高电位VGH信号，并在所述触控屏中停期间为恒压低电位VGL信号。
  18. 如权利要求17所述的显示装置，其中，所述正反向扫描控制模块(1)包括第二薄膜晶体管(NT2)和第三薄膜晶体管(NT3)；其中，
    所述第二薄膜晶体管(NT2)的栅极连接第N-2级GOA结构单元的栅极驱动信号(G(N-2))，源极接入所述正向直流扫描控制信号(U2D)，漏极同时连接所述稳压模块(4)中第一薄膜晶体管(NT1)源极及所述第三薄膜晶体管(NT3)的漏极；
    所述第三薄膜晶体管(NT3)的栅极连接第N+2级GOA结构单元的栅极驱动信号(G(N+2))，源极接入所述反向直流扫描控制信号(D2U)。
  19. 如权利要求18所述的显示装置，其中，所述节点信号控制输入模块(2)包括第四薄膜晶体管(NT4)、第五薄膜晶体管(NT5)和第六薄膜晶体管(NT6)；其中，
    所述第四薄膜晶体管(NT4)的栅极接入所述正向直流扫描控制信号(U2D)，源极接入第N+1级GOA结构单元的时钟信号(CK(N+1))，漏极连接所述第五薄膜晶体管(NT5)的漏极和所述第六薄膜晶体管(NT6)的栅极；
    所述第五薄膜晶体管(NT5)的栅极接入所述反向直流扫描控制信号(D2U)，源极接入第N-1级GOA结构单元的时钟信号(CK(N-1))；
    所述第六薄膜晶体管(NT6)的源极接入恒压高电位VGH信号，漏极连接与所述Q点下拉模块(5)、P点下拉模块(6)、栅极信号下拉模块(7)及GAS信号作用模块(8)均相连的第二节点(P(N))。
  20. 如权利要求19所述的显示装置，其中，所述输出控制模块(3)包括第七薄膜晶体管(NT7)，所述第七薄膜晶体管(NT7)的栅极连接所述第一节点(Q(N))，源极接入本级时钟信号(CK(N))，漏极连接所述本级栅极驱动信号(G(N))。
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